2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/of_address.h>
10 #include <linux/of_irq.h>
11 #include <linux/slab.h>
12 #include <linux/irqchip.h>
13 #include <linux/syscore_ops.h>
16 #define GPC_MAX_IRQS (IMR_NUM * 32)
18 #define GPC_IMR1_CORE0 0x30
19 #define GPC_IMR1_CORE1 0x40
21 struct gpcv2_irqchip_data
{
22 struct raw_spinlock rlock
;
23 void __iomem
*gpc_base
;
24 u32 wakeup_sources
[IMR_NUM
];
25 u32 saved_irq_mask
[IMR_NUM
];
29 static struct gpcv2_irqchip_data
*imx_gpcv2_instance
;
32 * Interface for the low level wakeup code.
34 u32
imx_gpcv2_get_wakeup_source(u32
**sources
)
36 if (!imx_gpcv2_instance
)
40 *sources
= imx_gpcv2_instance
->wakeup_sources
;
45 static int gpcv2_wakeup_source_save(void)
47 struct gpcv2_irqchip_data
*cd
;
51 cd
= imx_gpcv2_instance
;
55 for (i
= 0; i
< IMR_NUM
; i
++) {
56 reg
= cd
->gpc_base
+ cd
->cpu2wakeup
+ i
* 4;
57 cd
->saved_irq_mask
[i
] = readl_relaxed(reg
);
58 writel_relaxed(cd
->wakeup_sources
[i
], reg
);
64 static void gpcv2_wakeup_source_restore(void)
66 struct gpcv2_irqchip_data
*cd
;
70 cd
= imx_gpcv2_instance
;
74 for (i
= 0; i
< IMR_NUM
; i
++) {
75 reg
= cd
->gpc_base
+ cd
->cpu2wakeup
+ i
* 4;
76 writel_relaxed(cd
->saved_irq_mask
[i
], reg
);
80 static struct syscore_ops imx_gpcv2_syscore_ops
= {
81 .suspend
= gpcv2_wakeup_source_save
,
82 .resume
= gpcv2_wakeup_source_restore
,
85 static int imx_gpcv2_irq_set_wake(struct irq_data
*d
, unsigned int on
)
87 struct gpcv2_irqchip_data
*cd
= d
->chip_data
;
88 unsigned int idx
= d
->hwirq
/ 32;
93 raw_spin_lock_irqsave(&cd
->rlock
, flags
);
94 reg
= cd
->gpc_base
+ cd
->cpu2wakeup
+ idx
* 4;
95 mask
= 1 << d
->hwirq
% 32;
96 val
= cd
->wakeup_sources
[idx
];
98 cd
->wakeup_sources
[idx
] = on
? (val
& ~mask
) : (val
| mask
);
99 raw_spin_unlock_irqrestore(&cd
->rlock
, flags
);
102 * Do *not* call into the parent, as the GIC doesn't have any
103 * wake-up facility...
109 static void imx_gpcv2_irq_unmask(struct irq_data
*d
)
111 struct gpcv2_irqchip_data
*cd
= d
->chip_data
;
115 raw_spin_lock(&cd
->rlock
);
116 reg
= cd
->gpc_base
+ cd
->cpu2wakeup
+ d
->hwirq
/ 32 * 4;
117 val
= readl_relaxed(reg
);
118 val
&= ~(1 << d
->hwirq
% 32);
119 writel_relaxed(val
, reg
);
120 raw_spin_unlock(&cd
->rlock
);
122 irq_chip_unmask_parent(d
);
125 static void imx_gpcv2_irq_mask(struct irq_data
*d
)
127 struct gpcv2_irqchip_data
*cd
= d
->chip_data
;
131 raw_spin_lock(&cd
->rlock
);
132 reg
= cd
->gpc_base
+ cd
->cpu2wakeup
+ d
->hwirq
/ 32 * 4;
133 val
= readl_relaxed(reg
);
134 val
|= 1 << (d
->hwirq
% 32);
135 writel_relaxed(val
, reg
);
136 raw_spin_unlock(&cd
->rlock
);
138 irq_chip_mask_parent(d
);
141 static struct irq_chip gpcv2_irqchip_data_chip
= {
143 .irq_eoi
= irq_chip_eoi_parent
,
144 .irq_mask
= imx_gpcv2_irq_mask
,
145 .irq_unmask
= imx_gpcv2_irq_unmask
,
146 .irq_set_wake
= imx_gpcv2_irq_set_wake
,
147 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
149 .irq_set_affinity
= irq_chip_set_affinity_parent
,
153 static int imx_gpcv2_domain_xlate(struct irq_domain
*domain
,
154 struct device_node
*controller
,
156 unsigned int intsize
,
157 unsigned long *out_hwirq
,
158 unsigned int *out_type
)
160 /* Shouldn't happen, really... */
161 if (domain
->of_node
!= controller
)
164 /* Not GIC compliant */
168 /* No PPI should point to this domain */
172 *out_hwirq
= intspec
[1];
173 *out_type
= intspec
[2];
177 static int imx_gpcv2_domain_alloc(struct irq_domain
*domain
,
178 unsigned int irq
, unsigned int nr_irqs
,
181 struct of_phandle_args
*args
= data
;
182 struct of_phandle_args parent_args
;
183 irq_hw_number_t hwirq
;
186 /* Not GIC compliant */
187 if (args
->args_count
!= 3)
190 /* No PPI should point to this domain */
191 if (args
->args
[0] != 0)
194 /* Can't deal with this */
195 hwirq
= args
->args
[1];
196 if (hwirq
>= GPC_MAX_IRQS
)
199 for (i
= 0; i
< nr_irqs
; i
++) {
200 irq_domain_set_hwirq_and_chip(domain
, irq
+ i
, hwirq
+ i
,
201 &gpcv2_irqchip_data_chip
, domain
->host_data
);
205 parent_args
.np
= domain
->parent
->of_node
;
206 return irq_domain_alloc_irqs_parent(domain
, irq
, nr_irqs
, &parent_args
);
209 static struct irq_domain_ops gpcv2_irqchip_data_domain_ops
= {
210 .xlate
= imx_gpcv2_domain_xlate
,
211 .alloc
= imx_gpcv2_domain_alloc
,
212 .free
= irq_domain_free_irqs_common
,
215 static int __init
imx_gpcv2_irqchip_init(struct device_node
*node
,
216 struct device_node
*parent
)
218 struct irq_domain
*parent_domain
, *domain
;
219 struct gpcv2_irqchip_data
*cd
;
223 pr_err("%s: no parent, giving up\n", node
->full_name
);
227 parent_domain
= irq_find_host(parent
);
228 if (!parent_domain
) {
229 pr_err("%s: unable to get parent domain\n", node
->full_name
);
233 cd
= kzalloc(sizeof(struct gpcv2_irqchip_data
), GFP_KERNEL
);
235 pr_err("kzalloc failed!\n");
239 cd
->gpc_base
= of_iomap(node
, 0);
241 pr_err("fsl-gpcv2: unable to map gpc registers\n");
246 domain
= irq_domain_add_hierarchy(parent_domain
, 0, GPC_MAX_IRQS
,
247 node
, &gpcv2_irqchip_data_domain_ops
, cd
);
249 iounmap(cd
->gpc_base
);
253 irq_set_default_host(domain
);
255 /* Initially mask all interrupts */
256 for (i
= 0; i
< IMR_NUM
; i
++) {
257 writel_relaxed(~0, cd
->gpc_base
+ GPC_IMR1_CORE0
+ i
* 4);
258 writel_relaxed(~0, cd
->gpc_base
+ GPC_IMR1_CORE1
+ i
* 4);
259 cd
->wakeup_sources
[i
] = ~0;
262 /* Let CORE0 as the default CPU to wake up by GPC */
263 cd
->cpu2wakeup
= GPC_IMR1_CORE0
;
266 * Due to hardware design failure, need to make sure GPR
267 * interrupt(#32) is unmasked during RUN mode to avoid entering
270 writel_relaxed(~0x1, cd
->gpc_base
+ cd
->cpu2wakeup
);
272 imx_gpcv2_instance
= cd
;
273 register_syscore_ops(&imx_gpcv2_syscore_ops
);
278 IRQCHIP_DECLARE(imx_gpcv2
, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init
);