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perf report: Fix format string for x86-32 compilation
[linux-2.6/btrfs-unstable.git] / drivers / pci / probe.c
blob5e1ca3c58a7d4502b966974ec13c55a892e9be2b
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 static LIST_HEAD(pci_host_bridges);
19
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
23
24
25 static int find_anything(struct device *dev, void *data)
26 {
27 return 1;
28 }
29
30 /*
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
34 */
35 int no_pci_devices(void)
36 {
37 struct device *dev;
38 int no_devices;
39
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL);
42 put_device(dev);
43 return no_devices;
44 }
45 EXPORT_SYMBOL(no_pci_devices);
46
47 static struct pci_host_bridge *pci_host_bridge(struct pci_dev *dev)
48 {
49 struct pci_bus *bus;
50 struct pci_host_bridge *bridge;
51
52 bus = dev->bus;
53 while (bus->parent)
54 bus = bus->parent;
55
56 list_for_each_entry(bridge, &pci_host_bridges, list) {
57 if (bridge->bus == bus)
58 return bridge;
59 }
60
61 return NULL;
62 }
63
64 static bool resource_contains(struct resource *res1, struct resource *res2)
65 {
66 return res1->start <= res2->start && res1->end >= res2->end;
67 }
68
69 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
70 struct resource *res)
71 {
72 struct pci_host_bridge *bridge = pci_host_bridge(dev);
73 struct pci_host_bridge_window *window;
74 resource_size_t offset = 0;
75
76 list_for_each_entry(window, &bridge->windows, list) {
77 if (resource_type(res) != resource_type(window->res))
78 continue;
79
80 if (resource_contains(window->res, res)) {
81 offset = window->offset;
82 break;
83 }
84 }
85
86 region->start = res->start - offset;
87 region->end = res->end - offset;
88 }
89 EXPORT_SYMBOL(pcibios_resource_to_bus);
90
91 static bool region_contains(struct pci_bus_region *region1,
92 struct pci_bus_region *region2)
93 {
94 return region1->start <= region2->start && region1->end >= region2->end;
95 }
96
97 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
98 struct pci_bus_region *region)
99 {
100 struct pci_host_bridge *bridge = pci_host_bridge(dev);
101 struct pci_host_bridge_window *window;
102 struct pci_bus_region bus_region;
103 resource_size_t offset = 0;
104
105 list_for_each_entry(window, &bridge->windows, list) {
106 if (resource_type(res) != resource_type(window->res))
107 continue;
108
109 bus_region.start = window->res->start - window->offset;
110 bus_region.end = window->res->end - window->offset;
111
112 if (region_contains(&bus_region, region)) {
113 offset = window->offset;
114 break;
115 }
116 }
117
118 res->start = region->start + offset;
119 res->end = region->end + offset;
120 }
121 EXPORT_SYMBOL(pcibios_bus_to_resource);
122
123 /*
124 * PCI Bus Class
125 */
126 static void release_pcibus_dev(struct device *dev)
127 {
128 struct pci_bus *pci_bus = to_pci_bus(dev);
129
130 if (pci_bus->bridge)
131 put_device(pci_bus->bridge);
132 pci_bus_remove_resources(pci_bus);
133 pci_release_bus_of_node(pci_bus);
134 kfree(pci_bus);
135 }
136
137 static struct class pcibus_class = {
138 .name = "pci_bus",
139 .dev_release = &release_pcibus_dev,
140 .dev_attrs = pcibus_dev_attrs,
141 };
142
143 static int __init pcibus_class_init(void)
144 {
145 return class_register(&pcibus_class);
146 }
147 postcore_initcall(pcibus_class_init);
148
149 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
150 {
151 u64 size = mask & maxbase; /* Find the significant bits */
152 if (!size)
153 return 0;
154
155 /* Get the lowest of them to find the decode size, and
156 from that the extent. */
157 size = (size & ~(size-1)) - 1;
158
159 /* base == maxbase can be valid only if the BAR has
160 already been programmed with all 1s. */
161 if (base == maxbase && ((base | size) & mask) != mask)
162 return 0;
163
164 return size;
165 }
166
167 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
168 {
169 u32 mem_type;
170 unsigned long flags;
171
172 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
173 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
174 flags |= IORESOURCE_IO;
175 return flags;
176 }
177
178 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
179 flags |= IORESOURCE_MEM;
180 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
181 flags |= IORESOURCE_PREFETCH;
182
183 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
184 switch (mem_type) {
185 case PCI_BASE_ADDRESS_MEM_TYPE_32:
186 break;
187 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
188 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
189 break;
190 case PCI_BASE_ADDRESS_MEM_TYPE_64:
191 flags |= IORESOURCE_MEM_64;
192 break;
193 default:
194 dev_warn(&dev->dev,
195 "mem unknown type %x treated as 32-bit BAR\n",
196 mem_type);
197 break;
198 }
199 return flags;
200 }
201
202 /**
203 * pci_read_base - read a PCI BAR
204 * @dev: the PCI device
205 * @type: type of the BAR
206 * @res: resource buffer to be filled in
207 * @pos: BAR position in the config space
208 *
209 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
210 */
211 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
212 struct resource *res, unsigned int pos)
213 {
214 u32 l, sz, mask;
215 u16 orig_cmd;
216 struct pci_bus_region region;
217
218 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
219
220 if (!dev->mmio_always_on) {
221 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
222 pci_write_config_word(dev, PCI_COMMAND,
223 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
224 }
225
226 res->name = pci_name(dev);
227
228 pci_read_config_dword(dev, pos, &l);
229 pci_write_config_dword(dev, pos, l | mask);
230 pci_read_config_dword(dev, pos, &sz);
231 pci_write_config_dword(dev, pos, l);
232
233 if (!dev->mmio_always_on)
234 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
235
236 /*
237 * All bits set in sz means the device isn't working properly.
238 * If the BAR isn't implemented, all bits must be 0. If it's a
239 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
240 * 1 must be clear.
241 */
242 if (!sz || sz == 0xffffffff)
243 goto fail;
244
245 /*
246 * I don't know how l can have all bits set. Copied from old code.
247 * Maybe it fixes a bug on some ancient platform.
248 */
249 if (l == 0xffffffff)
250 l = 0;
251
252 if (type == pci_bar_unknown) {
253 res->flags = decode_bar(dev, l);
254 res->flags |= IORESOURCE_SIZEALIGN;
255 if (res->flags & IORESOURCE_IO) {
256 l &= PCI_BASE_ADDRESS_IO_MASK;
257 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
258 } else {
259 l &= PCI_BASE_ADDRESS_MEM_MASK;
260 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
261 }
262 } else {
263 res->flags |= (l & IORESOURCE_ROM_ENABLE);
264 l &= PCI_ROM_ADDRESS_MASK;
265 mask = (u32)PCI_ROM_ADDRESS_MASK;
266 }
267
268 if (res->flags & IORESOURCE_MEM_64) {
269 u64 l64 = l;
270 u64 sz64 = sz;
271 u64 mask64 = mask | (u64)~0 << 32;
272
273 pci_read_config_dword(dev, pos + 4, &l);
274 pci_write_config_dword(dev, pos + 4, ~0);
275 pci_read_config_dword(dev, pos + 4, &sz);
276 pci_write_config_dword(dev, pos + 4, l);
277
278 l64 |= ((u64)l << 32);
279 sz64 |= ((u64)sz << 32);
280
281 sz64 = pci_size(l64, sz64, mask64);
282
283 if (!sz64)
284 goto fail;
285
286 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
287 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
288 pos);
289 goto fail;
290 }
291
292 if ((sizeof(resource_size_t) < 8) && l) {
293 /* Address above 32-bit boundary; disable the BAR */
294 pci_write_config_dword(dev, pos, 0);
295 pci_write_config_dword(dev, pos + 4, 0);
296 region.start = 0;
297 region.end = sz64;
298 pcibios_bus_to_resource(dev, res, &region);
299 } else {
300 region.start = l64;
301 region.end = l64 + sz64;
302 pcibios_bus_to_resource(dev, res, &region);
303 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
304 pos, res);
305 }
306 } else {
307 sz = pci_size(l, sz, mask);
308
309 if (!sz)
310 goto fail;
311
312 region.start = l;
313 region.end = l + sz;
314 pcibios_bus_to_resource(dev, res, &region);
315
316 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
317 }
318
319 out:
320 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
321 fail:
322 res->flags = 0;
323 goto out;
324 }
325
326 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
327 {
328 unsigned int pos, reg;
329
330 for (pos = 0; pos < howmany; pos++) {
331 struct resource *res = &dev->resource[pos];
332 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
333 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
334 }
335
336 if (rom) {
337 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
338 dev->rom_base_reg = rom;
339 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
340 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
341 IORESOURCE_SIZEALIGN;
342 __pci_read_base(dev, pci_bar_mem32, res, rom);
343 }
344 }
345
346 static void __devinit pci_read_bridge_io(struct pci_bus *child)
347 {
348 struct pci_dev *dev = child->self;
349 u8 io_base_lo, io_limit_lo;
350 unsigned long base, limit;
351 struct pci_bus_region region;
352 struct resource *res, res2;
353
354 res = child->resource[0];
355 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
356 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
357 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
358 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
359
360 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
361 u16 io_base_hi, io_limit_hi;
362 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
363 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
364 base |= (io_base_hi << 16);
365 limit |= (io_limit_hi << 16);
366 }
367
368 if (base && base <= limit) {
369 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
370 res2.flags = res->flags;
371 region.start = base;
372 region.end = limit + 0xfff;
373 pcibios_bus_to_resource(dev, &res2, &region);
374 if (!res->start)
375 res->start = res2.start;
376 if (!res->end)
377 res->end = res2.end;
378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
379 }
380 }
381
382 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
383 {
384 struct pci_dev *dev = child->self;
385 u16 mem_base_lo, mem_limit_lo;
386 unsigned long base, limit;
387 struct pci_bus_region region;
388 struct resource *res;
389
390 res = child->resource[1];
391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
393 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
395 if (base && base <= limit) {
396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
397 region.start = base;
398 region.end = limit + 0xfffff;
399 pcibios_bus_to_resource(dev, res, &region);
400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
401 }
402 }
403
404 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
405 {
406 struct pci_dev *dev = child->self;
407 u16 mem_base_lo, mem_limit_lo;
408 unsigned long base, limit;
409 struct pci_bus_region region;
410 struct resource *res;
411
412 res = child->resource[2];
413 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
414 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
415 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
416 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
417
418 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
419 u32 mem_base_hi, mem_limit_hi;
420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
422
423 /*
424 * Some bridges set the base > limit by default, and some
425 * (broken) BIOSes do not initialize them. If we find
426 * this, just assume they are not being used.
427 */
428 if (mem_base_hi <= mem_limit_hi) {
429 #if BITS_PER_LONG == 64
430 base |= ((long) mem_base_hi) << 32;
431 limit |= ((long) mem_limit_hi) << 32;
432 #else
433 if (mem_base_hi || mem_limit_hi) {
434 dev_err(&dev->dev, "can't handle 64-bit "
435 "address space for bridge\n");
436 return;
437 }
438 #endif
439 }
440 }
441 if (base && base <= limit) {
442 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
443 IORESOURCE_MEM | IORESOURCE_PREFETCH;
444 if (res->flags & PCI_PREF_RANGE_TYPE_64)
445 res->flags |= IORESOURCE_MEM_64;
446 region.start = base;
447 region.end = limit + 0xfffff;
448 pcibios_bus_to_resource(dev, res, &region);
449 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
450 }
451 }
452
453 void __devinit pci_read_bridge_bases(struct pci_bus *child)
454 {
455 struct pci_dev *dev = child->self;
456 struct resource *res;
457 int i;
458
459 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
460 return;
461
462 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
463 child->secondary, child->subordinate,
464 dev->transparent ? " (subtractive decode)" : "");
465
466 pci_bus_remove_resources(child);
467 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
468 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
469
470 pci_read_bridge_io(child);
471 pci_read_bridge_mmio(child);
472 pci_read_bridge_mmio_pref(child);
473
474 if (dev->transparent) {
475 pci_bus_for_each_resource(child->parent, res, i) {
476 if (res) {
477 pci_bus_add_resource(child, res,
478 PCI_SUBTRACTIVE_DECODE);
479 dev_printk(KERN_DEBUG, &dev->dev,
480 " bridge window %pR (subtractive decode)\n",
481 res);
482 }
483 }
484 }
485 }
486
487 static struct pci_bus * pci_alloc_bus(void)
488 {
489 struct pci_bus *b;
490
491 b = kzalloc(sizeof(*b), GFP_KERNEL);
492 if (b) {
493 INIT_LIST_HEAD(&b->node);
494 INIT_LIST_HEAD(&b->children);
495 INIT_LIST_HEAD(&b->devices);
496 INIT_LIST_HEAD(&b->slots);
497 INIT_LIST_HEAD(&b->resources);
498 b->max_bus_speed = PCI_SPEED_UNKNOWN;
499 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
500 }
501 return b;
502 }
503
504 static unsigned char pcix_bus_speed[] = {
505 PCI_SPEED_UNKNOWN, /* 0 */
506 PCI_SPEED_66MHz_PCIX, /* 1 */
507 PCI_SPEED_100MHz_PCIX, /* 2 */
508 PCI_SPEED_133MHz_PCIX, /* 3 */
509 PCI_SPEED_UNKNOWN, /* 4 */
510 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
511 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
512 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
513 PCI_SPEED_UNKNOWN, /* 8 */
514 PCI_SPEED_66MHz_PCIX_266, /* 9 */
515 PCI_SPEED_100MHz_PCIX_266, /* A */
516 PCI_SPEED_133MHz_PCIX_266, /* B */
517 PCI_SPEED_UNKNOWN, /* C */
518 PCI_SPEED_66MHz_PCIX_533, /* D */
519 PCI_SPEED_100MHz_PCIX_533, /* E */
520 PCI_SPEED_133MHz_PCIX_533 /* F */
521 };
522
523 static unsigned char pcie_link_speed[] = {
524 PCI_SPEED_UNKNOWN, /* 0 */
525 PCIE_SPEED_2_5GT, /* 1 */
526 PCIE_SPEED_5_0GT, /* 2 */
527 PCIE_SPEED_8_0GT, /* 3 */
528 PCI_SPEED_UNKNOWN, /* 4 */
529 PCI_SPEED_UNKNOWN, /* 5 */
530 PCI_SPEED_UNKNOWN, /* 6 */
531 PCI_SPEED_UNKNOWN, /* 7 */
532 PCI_SPEED_UNKNOWN, /* 8 */
533 PCI_SPEED_UNKNOWN, /* 9 */
534 PCI_SPEED_UNKNOWN, /* A */
535 PCI_SPEED_UNKNOWN, /* B */
536 PCI_SPEED_UNKNOWN, /* C */
537 PCI_SPEED_UNKNOWN, /* D */
538 PCI_SPEED_UNKNOWN, /* E */
539 PCI_SPEED_UNKNOWN /* F */
540 };
541
542 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
543 {
544 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
545 }
546 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
547
548 static unsigned char agp_speeds[] = {
549 AGP_UNKNOWN,
550 AGP_1X,
551 AGP_2X,
552 AGP_4X,
553 AGP_8X
554 };
555
556 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
557 {
558 int index = 0;
559
560 if (agpstat & 4)
561 index = 3;
562 else if (agpstat & 2)
563 index = 2;
564 else if (agpstat & 1)
565 index = 1;
566 else
567 goto out;
568
569 if (agp3) {
570 index += 2;
571 if (index == 5)
572 index = 0;
573 }
574
575 out:
576 return agp_speeds[index];
577 }
578
579
580 static void pci_set_bus_speed(struct pci_bus *bus)
581 {
582 struct pci_dev *bridge = bus->self;
583 int pos;
584
585 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
586 if (!pos)
587 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
588 if (pos) {
589 u32 agpstat, agpcmd;
590
591 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
592 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
593
594 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
595 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
596 }
597
598 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
599 if (pos) {
600 u16 status;
601 enum pci_bus_speed max;
602 pci_read_config_word(bridge, pos + 2, &status);
603
604 if (status & 0x8000) {
605 max = PCI_SPEED_133MHz_PCIX_533;
606 } else if (status & 0x4000) {
607 max = PCI_SPEED_133MHz_PCIX_266;
608 } else if (status & 0x0002) {
609 if (((status >> 12) & 0x3) == 2) {
610 max = PCI_SPEED_133MHz_PCIX_ECC;
611 } else {
612 max = PCI_SPEED_133MHz_PCIX;
613 }
614 } else {
615 max = PCI_SPEED_66MHz_PCIX;
616 }
617
618 bus->max_bus_speed = max;
619 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
620
621 return;
622 }
623
624 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
625 if (pos) {
626 u32 linkcap;
627 u16 linksta;
628
629 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
630 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
631
632 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
633 pcie_update_link_speed(bus, linksta);
634 }
635 }
636
637
638 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
639 struct pci_dev *bridge, int busnr)
640 {
641 struct pci_bus *child;
642 int i;
643
644 /*
645 * Allocate a new bus, and inherit stuff from the parent..
646 */
647 child = pci_alloc_bus();
648 if (!child)
649 return NULL;
650
651 child->parent = parent;
652 child->ops = parent->ops;
653 child->sysdata = parent->sysdata;
654 child->bus_flags = parent->bus_flags;
655
656 /* initialize some portions of the bus device, but don't register it
657 * now as the parent is not properly set up yet. This device will get
658 * registered later in pci_bus_add_devices()
659 */
660 child->dev.class = &pcibus_class;
661 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
662
663 /*
664 * Set up the primary, secondary and subordinate
665 * bus numbers.
666 */
667 child->number = child->secondary = busnr;
668 child->primary = parent->secondary;
669 child->subordinate = 0xff;
670
671 if (!bridge)
672 return child;
673
674 child->self = bridge;
675 child->bridge = get_device(&bridge->dev);
676 pci_set_bus_of_node(child);
677 pci_set_bus_speed(child);
678
679 /* Set up default resource pointers and names.. */
680 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
681 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
682 child->resource[i]->name = child->name;
683 }
684 bridge->subordinate = child;
685
686 return child;
687 }
688
689 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
690 {
691 struct pci_bus *child;
692
693 child = pci_alloc_child_bus(parent, dev, busnr);
694 if (child) {
695 down_write(&pci_bus_sem);
696 list_add_tail(&child->node, &parent->children);
697 up_write(&pci_bus_sem);
698 }
699 return child;
700 }
701
702 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
703 {
704 struct pci_bus *parent = child->parent;
705
706 /* Attempts to fix that up are really dangerous unless
707 we're going to re-assign all bus numbers. */
708 if (!pcibios_assign_all_busses())
709 return;
710
711 while (parent->parent && parent->subordinate < max) {
712 parent->subordinate = max;
713 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
714 parent = parent->parent;
715 }
716 }
717
718 /*
719 * If it's a bridge, configure it and scan the bus behind it.
720 * For CardBus bridges, we don't scan behind as the devices will
721 * be handled by the bridge driver itself.
722 *
723 * We need to process bridges in two passes -- first we scan those
724 * already configured by the BIOS and after we are done with all of
725 * them, we proceed to assigning numbers to the remaining buses in
726 * order to avoid overlaps between old and new bus numbers.
727 */
728 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
729 {
730 struct pci_bus *child;
731 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
732 u32 buses, i, j = 0;
733 u16 bctl;
734 u8 primary, secondary, subordinate;
735 int broken = 0;
736
737 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
738 primary = buses & 0xFF;
739 secondary = (buses >> 8) & 0xFF;
740 subordinate = (buses >> 16) & 0xFF;
741
742 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
743 secondary, subordinate, pass);
744
745 if (!primary && (primary != bus->number) && secondary && subordinate) {
746 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
747 primary = bus->number;
748 }
749
750 /* Check if setup is sensible at all */
751 if (!pass &&
752 (primary != bus->number || secondary <= bus->number)) {
753 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
754 broken = 1;
755 }
756
757 /* Disable MasterAbortMode during probing to avoid reporting
758 of bus errors (in some architectures) */
759 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
760 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
761 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
762
763 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
764 !is_cardbus && !broken) {
765 unsigned int cmax;
766 /*
767 * Bus already configured by firmware, process it in the first
768 * pass and just note the configuration.
769 */
770 if (pass)
771 goto out;
772
773 /*
774 * If we already got to this bus through a different bridge,
775 * don't re-add it. This can happen with the i450NX chipset.
776 *
777 * However, we continue to descend down the hierarchy and
778 * scan remaining child buses.
779 */
780 child = pci_find_bus(pci_domain_nr(bus), secondary);
781 if (!child) {
782 child = pci_add_new_bus(bus, dev, secondary);
783 if (!child)
784 goto out;
785 child->primary = primary;
786 child->subordinate = subordinate;
787 child->bridge_ctl = bctl;
788 }
789
790 cmax = pci_scan_child_bus(child);
791 if (cmax > max)
792 max = cmax;
793 if (child->subordinate > max)
794 max = child->subordinate;
795 } else {
796 /*
797 * We need to assign a number to this bus which we always
798 * do in the second pass.
799 */
800 if (!pass) {
801 if (pcibios_assign_all_busses() || broken)
802 /* Temporarily disable forwarding of the
803 configuration cycles on all bridges in
804 this bus segment to avoid possible
805 conflicts in the second pass between two
806 bridges programmed with overlapping
807 bus ranges. */
808 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
809 buses & ~0xffffff);
810 goto out;
811 }
812
813 /* Clear errors */
814 pci_write_config_word(dev, PCI_STATUS, 0xffff);
815
816 /* Prevent assigning a bus number that already exists.
817 * This can happen when a bridge is hot-plugged, so in
818 * this case we only re-scan this bus. */
819 child = pci_find_bus(pci_domain_nr(bus), max+1);
820 if (!child) {
821 child = pci_add_new_bus(bus, dev, ++max);
822 if (!child)
823 goto out;
824 }
825 buses = (buses & 0xff000000)
826 | ((unsigned int)(child->primary) << 0)
827 | ((unsigned int)(child->secondary) << 8)
828 | ((unsigned int)(child->subordinate) << 16);
829
830 /*
831 * yenta.c forces a secondary latency timer of 176.
832 * Copy that behaviour here.
833 */
834 if (is_cardbus) {
835 buses &= ~0xff000000;
836 buses |= CARDBUS_LATENCY_TIMER << 24;
837 }
838
839 /*
840 * We need to blast all three values with a single write.
841 */
842 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
843
844 if (!is_cardbus) {
845 child->bridge_ctl = bctl;
846 /*
847 * Adjust subordinate busnr in parent buses.
848 * We do this before scanning for children because
849 * some devices may not be detected if the bios
850 * was lazy.
851 */
852 pci_fixup_parent_subordinate_busnr(child, max);
853 /* Now we can scan all subordinate buses... */
854 max = pci_scan_child_bus(child);
855 /*
856 * now fix it up again since we have found
857 * the real value of max.
858 */
859 pci_fixup_parent_subordinate_busnr(child, max);
860 } else {
861 /*
862 * For CardBus bridges, we leave 4 bus numbers
863 * as cards with a PCI-to-PCI bridge can be
864 * inserted later.
865 */
866 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
867 struct pci_bus *parent = bus;
868 if (pci_find_bus(pci_domain_nr(bus),
869 max+i+1))
870 break;
871 while (parent->parent) {
872 if ((!pcibios_assign_all_busses()) &&
873 (parent->subordinate > max) &&
874 (parent->subordinate <= max+i)) {
875 j = 1;
876 }
877 parent = parent->parent;
878 }
879 if (j) {
880 /*
881 * Often, there are two cardbus bridges
882 * -- try to leave one valid bus number
883 * for each one.
884 */
885 i /= 2;
886 break;
887 }
888 }
889 max += i;
890 pci_fixup_parent_subordinate_busnr(child, max);
891 }
892 /*
893 * Set the subordinate bus number to its real value.
894 */
895 child->subordinate = max;
896 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
897 }
898
899 sprintf(child->name,
900 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
901 pci_domain_nr(bus), child->number);
902
903 /* Has only triggered on CardBus, fixup is in yenta_socket */
904 while (bus->parent) {
905 if ((child->subordinate > bus->subordinate) ||
906 (child->number > bus->subordinate) ||
907 (child->number < bus->number) ||
908 (child->subordinate < bus->number)) {
909 dev_info(&child->dev, "[bus %02x-%02x] %s "
910 "hidden behind%s bridge %s [bus %02x-%02x]\n",
911 child->number, child->subordinate,
912 (bus->number > child->subordinate &&
913 bus->subordinate < child->number) ?
914 "wholly" : "partially",
915 bus->self->transparent ? " transparent" : "",
916 dev_name(&bus->dev),
917 bus->number, bus->subordinate);
918 }
919 bus = bus->parent;
920 }
921
922 out:
923 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
924
925 return max;
926 }
927
928 /*
929 * Read interrupt line and base address registers.
930 * The architecture-dependent code can tweak these, of course.
931 */
932 static void pci_read_irq(struct pci_dev *dev)
933 {
934 unsigned char irq;
935
936 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
937 dev->pin = irq;
938 if (irq)
939 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
940 dev->irq = irq;
941 }
942
943 void set_pcie_port_type(struct pci_dev *pdev)
944 {
945 int pos;
946 u16 reg16;
947
948 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
949 if (!pos)
950 return;
951 pdev->is_pcie = 1;
952 pdev->pcie_cap = pos;
953 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
954 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
955 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
956 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
957 }
958
959 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
960 {
961 int pos;
962 u16 reg16;
963 u32 reg32;
964
965 pos = pci_pcie_cap(pdev);
966 if (!pos)
967 return;
968 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
969 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
970 return;
971 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
972 if (reg32 & PCI_EXP_SLTCAP_HPC)
973 pdev->is_hotplug_bridge = 1;
974 }
975
976 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
977
978 /**
979 * pci_setup_device - fill in class and map information of a device
980 * @dev: the device structure to fill
981 *
982 * Initialize the device structure with information about the device's
983 * vendor,class,memory and IO-space addresses,IRQ lines etc.
984 * Called at initialisation of the PCI subsystem and by CardBus services.
985 * Returns 0 on success and negative if unknown type of device (not normal,
986 * bridge or CardBus).
987 */
988 int pci_setup_device(struct pci_dev *dev)
989 {
990 u32 class;
991 u8 hdr_type;
992 struct pci_slot *slot;
993 int pos = 0;
994 struct pci_bus_region region;
995 struct resource *res;
996
997 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
998 return -EIO;
999
1000 dev->sysdata = dev->bus->sysdata;
1001 dev->dev.parent = dev->bus->bridge;
1002 dev->dev.bus = &pci_bus_type;
1003 dev->hdr_type = hdr_type & 0x7f;
1004 dev->multifunction = !!(hdr_type & 0x80);
1005 dev->error_state = pci_channel_io_normal;
1006 set_pcie_port_type(dev);
1007
1008 list_for_each_entry(slot, &dev->bus->slots, list)
1009 if (PCI_SLOT(dev->devfn) == slot->number)
1010 dev->slot = slot;
1011
1012 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1013 set this higher, assuming the system even supports it. */
1014 dev->dma_mask = 0xffffffff;
1015
1016 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1017 dev->bus->number, PCI_SLOT(dev->devfn),
1018 PCI_FUNC(dev->devfn));
1019
1020 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1021 dev->revision = class & 0xff;
1022 dev->class = class >> 8; /* upper 3 bytes */
1023
1024 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1025 dev->vendor, dev->device, dev->hdr_type, dev->class);
1026
1027 /* need to have dev->class ready */
1028 dev->cfg_size = pci_cfg_space_size(dev);
1029
1030 /* "Unknown power state" */
1031 dev->current_state = PCI_UNKNOWN;
1032
1033 /* Early fixups, before probing the BARs */
1034 pci_fixup_device(pci_fixup_early, dev);
1035 /* device class may be changed after fixup */
1036 class = dev->class >> 8;
1037
1038 switch (dev->hdr_type) { /* header type */
1039 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1040 if (class == PCI_CLASS_BRIDGE_PCI)
1041 goto bad;
1042 pci_read_irq(dev);
1043 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1044 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1045 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1046
1047 /*
1048 * Do the ugly legacy mode stuff here rather than broken chip
1049 * quirk code. Legacy mode ATA controllers have fixed
1050 * addresses. These are not always echoed in BAR0-3, and
1051 * BAR0-3 in a few cases contain junk!
1052 */
1053 if (class == PCI_CLASS_STORAGE_IDE) {
1054 u8 progif;
1055 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1056 if ((progif & 1) == 0) {
1057 region.start = 0x1F0;
1058 region.end = 0x1F7;
1059 res = &dev->resource[0];
1060 res->flags = LEGACY_IO_RESOURCE;
1061 pcibios_bus_to_resource(dev, res, &region);
1062 region.start = 0x3F6;
1063 region.end = 0x3F6;
1064 res = &dev->resource[1];
1065 res->flags = LEGACY_IO_RESOURCE;
1066 pcibios_bus_to_resource(dev, res, &region);
1067 }
1068 if ((progif & 4) == 0) {
1069 region.start = 0x170;
1070 region.end = 0x177;
1071 res = &dev->resource[2];
1072 res->flags = LEGACY_IO_RESOURCE;
1073 pcibios_bus_to_resource(dev, res, &region);
1074 region.start = 0x376;
1075 region.end = 0x376;
1076 res = &dev->resource[3];
1077 res->flags = LEGACY_IO_RESOURCE;
1078 pcibios_bus_to_resource(dev, res, &region);
1079 }
1080 }
1081 break;
1082
1083 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1084 if (class != PCI_CLASS_BRIDGE_PCI)
1085 goto bad;
1086 /* The PCI-to-PCI bridge spec requires that subtractive
1087 decoding (i.e. transparent) bridge must have programming
1088 interface code of 0x01. */
1089 pci_read_irq(dev);
1090 dev->transparent = ((dev->class & 0xff) == 1);
1091 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1092 set_pcie_hotplug_bridge(dev);
1093 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1094 if (pos) {
1095 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1096 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1097 }
1098 break;
1099
1100 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1101 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1102 goto bad;
1103 pci_read_irq(dev);
1104 pci_read_bases(dev, 1, 0);
1105 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1106 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1107 break;
1108
1109 default: /* unknown header */
1110 dev_err(&dev->dev, "unknown header type %02x, "
1111 "ignoring device\n", dev->hdr_type);
1112 return -EIO;
1113
1114 bad:
1115 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1116 "type %02x)\n", dev->class, dev->hdr_type);
1117 dev->class = PCI_CLASS_NOT_DEFINED;
1118 }
1119
1120 /* We found a fine healthy device, go go go... */
1121 return 0;
1122 }
1123
1124 static void pci_release_capabilities(struct pci_dev *dev)
1125 {
1126 pci_vpd_release(dev);
1127 pci_iov_release(dev);
1128 pci_free_cap_save_buffers(dev);
1129 }
1130
1131 /**
1132 * pci_release_dev - free a pci device structure when all users of it are finished.
1133 * @dev: device that's been disconnected
1134 *
1135 * Will be called only by the device core when all users of this pci device are
1136 * done.
1137 */
1138 static void pci_release_dev(struct device *dev)
1139 {
1140 struct pci_dev *pci_dev;
1141
1142 pci_dev = to_pci_dev(dev);
1143 pci_release_capabilities(pci_dev);
1144 pci_release_of_node(pci_dev);
1145 kfree(pci_dev);
1146 }
1147
1148 /**
1149 * pci_cfg_space_size - get the configuration space size of the PCI device.
1150 * @dev: PCI device
1151 *
1152 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1153 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1154 * access it. Maybe we don't have a way to generate extended config space
1155 * accesses, or the device is behind a reverse Express bridge. So we try
1156 * reading the dword at 0x100 which must either be 0 or a valid extended
1157 * capability header.
1158 */
1159 int pci_cfg_space_size_ext(struct pci_dev *dev)
1160 {
1161 u32 status;
1162 int pos = PCI_CFG_SPACE_SIZE;
1163
1164 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1165 goto fail;
1166 if (status == 0xffffffff)
1167 goto fail;
1168
1169 return PCI_CFG_SPACE_EXP_SIZE;
1170
1171 fail:
1172 return PCI_CFG_SPACE_SIZE;
1173 }
1174
1175 int pci_cfg_space_size(struct pci_dev *dev)
1176 {
1177 int pos;
1178 u32 status;
1179 u16 class;
1180
1181 class = dev->class >> 8;
1182 if (class == PCI_CLASS_BRIDGE_HOST)
1183 return pci_cfg_space_size_ext(dev);
1184
1185 pos = pci_pcie_cap(dev);
1186 if (!pos) {
1187 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1188 if (!pos)
1189 goto fail;
1190
1191 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1192 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1193 goto fail;
1194 }
1195
1196 return pci_cfg_space_size_ext(dev);
1197
1198 fail:
1199 return PCI_CFG_SPACE_SIZE;
1200 }
1201
1202 static void pci_release_bus_bridge_dev(struct device *dev)
1203 {
1204 kfree(dev);
1205 }
1206
1207 struct pci_dev *alloc_pci_dev(void)
1208 {
1209 struct pci_dev *dev;
1210
1211 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1212 if (!dev)
1213 return NULL;
1214
1215 INIT_LIST_HEAD(&dev->bus_list);
1216
1217 return dev;
1218 }
1219 EXPORT_SYMBOL(alloc_pci_dev);
1220
1221 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1222 int crs_timeout)
1223 {
1224 int delay = 1;
1225
1226 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1227 return false;
1228
1229 /* some broken boards return 0 or ~0 if a slot is empty: */
1230 if (*l == 0xffffffff || *l == 0x00000000 ||
1231 *l == 0x0000ffff || *l == 0xffff0000)
1232 return false;
1233
1234 /* Configuration request Retry Status */
1235 while (*l == 0xffff0001) {
1236 if (!crs_timeout)
1237 return false;
1238
1239 msleep(delay);
1240 delay *= 2;
1241 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1242 return false;
1243 /* Card hasn't responded in 60 seconds? Must be stuck. */
1244 if (delay > crs_timeout) {
1245 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1246 "responding\n", pci_domain_nr(bus),
1247 bus->number, PCI_SLOT(devfn),
1248 PCI_FUNC(devfn));
1249 return false;
1250 }
1251 }
1252
1253 return true;
1254 }
1255 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1256
1257 /*
1258 * Read the config data for a PCI device, sanity-check it
1259 * and fill in the dev structure...
1260 */
1261 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1262 {
1263 struct pci_dev *dev;
1264 u32 l;
1265
1266 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1267 return NULL;
1268
1269 dev = alloc_pci_dev();
1270 if (!dev)
1271 return NULL;
1272
1273 dev->bus = bus;
1274 dev->devfn = devfn;
1275 dev->vendor = l & 0xffff;
1276 dev->device = (l >> 16) & 0xffff;
1277
1278 pci_set_of_node(dev);
1279
1280 if (pci_setup_device(dev)) {
1281 kfree(dev);
1282 return NULL;
1283 }
1284
1285 return dev;
1286 }
1287
1288 static void pci_init_capabilities(struct pci_dev *dev)
1289 {
1290 /* MSI/MSI-X list */
1291 pci_msi_init_pci_dev(dev);
1292
1293 /* Buffers for saving PCIe and PCI-X capabilities */
1294 pci_allocate_cap_save_buffers(dev);
1295
1296 /* Power Management */
1297 pci_pm_init(dev);
1298 platform_pci_wakeup_init(dev);
1299
1300 /* Vital Product Data */
1301 pci_vpd_pci22_init(dev);
1302
1303 /* Alternative Routing-ID Forwarding */
1304 pci_enable_ari(dev);
1305
1306 /* Single Root I/O Virtualization */
1307 pci_iov_init(dev);
1308
1309 /* Enable ACS P2P upstream forwarding */
1310 pci_enable_acs(dev);
1311 }
1312
1313 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1314 {
1315 device_initialize(&dev->dev);
1316 dev->dev.release = pci_release_dev;
1317 pci_dev_get(dev);
1318
1319 dev->dev.dma_mask = &dev->dma_mask;
1320 dev->dev.dma_parms = &dev->dma_parms;
1321 dev->dev.coherent_dma_mask = 0xffffffffull;
1322
1323 pci_set_dma_max_seg_size(dev, 65536);
1324 pci_set_dma_seg_boundary(dev, 0xffffffff);
1325
1326 /* Fix up broken headers */
1327 pci_fixup_device(pci_fixup_header, dev);
1328
1329 /* moved out from quirk header fixup code */
1330 pci_reassigndev_resource_alignment(dev);
1331
1332 /* Clear the state_saved flag. */
1333 dev->state_saved = false;
1334
1335 /* Initialize various capabilities */
1336 pci_init_capabilities(dev);
1337
1338 /*
1339 * Add the device to our list of discovered devices
1340 * and the bus list for fixup functions, etc.
1341 */
1342 down_write(&pci_bus_sem);
1343 list_add_tail(&dev->bus_list, &bus->devices);
1344 up_write(&pci_bus_sem);
1345 }
1346
1347 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1348 {
1349 struct pci_dev *dev;
1350
1351 dev = pci_get_slot(bus, devfn);
1352 if (dev) {
1353 pci_dev_put(dev);
1354 return dev;
1355 }
1356
1357 dev = pci_scan_device(bus, devfn);
1358 if (!dev)
1359 return NULL;
1360
1361 pci_device_add(dev, bus);
1362
1363 return dev;
1364 }
1365 EXPORT_SYMBOL(pci_scan_single_device);
1366
1367 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1368 {
1369 u16 cap;
1370 unsigned pos, next_fn;
1371
1372 if (!dev)
1373 return 0;
1374
1375 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1376 if (!pos)
1377 return 0;
1378 pci_read_config_word(dev, pos + 4, &cap);
1379 next_fn = cap >> 8;
1380 if (next_fn <= fn)
1381 return 0;
1382 return next_fn;
1383 }
1384
1385 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1386 {
1387 return (fn + 1) % 8;
1388 }
1389
1390 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1391 {
1392 return 0;
1393 }
1394
1395 static int only_one_child(struct pci_bus *bus)
1396 {
1397 struct pci_dev *parent = bus->self;
1398 if (!parent || !pci_is_pcie(parent))
1399 return 0;
1400 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1401 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1402 return 1;
1403 return 0;
1404 }
1405
1406 /**
1407 * pci_scan_slot - scan a PCI slot on a bus for devices.
1408 * @bus: PCI bus to scan
1409 * @devfn: slot number to scan (must have zero function.)
1410 *
1411 * Scan a PCI slot on the specified PCI bus for devices, adding
1412 * discovered devices to the @bus->devices list. New devices
1413 * will not have is_added set.
1414 *
1415 * Returns the number of new devices found.
1416 */
1417 int pci_scan_slot(struct pci_bus *bus, int devfn)
1418 {
1419 unsigned fn, nr = 0;
1420 struct pci_dev *dev;
1421 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1422
1423 if (only_one_child(bus) && (devfn > 0))
1424 return 0; /* Already scanned the entire slot */
1425
1426 dev = pci_scan_single_device(bus, devfn);
1427 if (!dev)
1428 return 0;
1429 if (!dev->is_added)
1430 nr++;
1431
1432 if (pci_ari_enabled(bus))
1433 next_fn = next_ari_fn;
1434 else if (dev->multifunction)
1435 next_fn = next_trad_fn;
1436
1437 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1438 dev = pci_scan_single_device(bus, devfn + fn);
1439 if (dev) {
1440 if (!dev->is_added)
1441 nr++;
1442 dev->multifunction = 1;
1443 }
1444 }
1445
1446 /* only one slot has pcie device */
1447 if (bus->self && nr)
1448 pcie_aspm_init_link_state(bus->self);
1449
1450 return nr;
1451 }
1452
1453 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1454 {
1455 u8 *smpss = data;
1456
1457 if (!pci_is_pcie(dev))
1458 return 0;
1459
1460 /* For PCIE hotplug enabled slots not connected directly to a
1461 * PCI-E root port, there can be problems when hotplugging
1462 * devices. This is due to the possibility of hotplugging a
1463 * device into the fabric with a smaller MPS that the devices
1464 * currently running have configured. Modifying the MPS on the
1465 * running devices could cause a fatal bus error due to an
1466 * incoming frame being larger than the newly configured MPS.
1467 * To work around this, the MPS for the entire fabric must be
1468 * set to the minimum size. Any devices hotplugged into this
1469 * fabric will have the minimum MPS set. If the PCI hotplug
1470 * slot is directly connected to the root port and there are not
1471 * other devices on the fabric (which seems to be the most
1472 * common case), then this is not an issue and MPS discovery
1473 * will occur as normal.
1474 */
1475 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1476 (dev->bus->self &&
1477 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1478 *smpss = 0;
1479
1480 if (*smpss > dev->pcie_mpss)
1481 *smpss = dev->pcie_mpss;
1482
1483 return 0;
1484 }
1485
1486 static void pcie_write_mps(struct pci_dev *dev, int mps)
1487 {
1488 int rc;
1489
1490 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1491 mps = 128 << dev->pcie_mpss;
1492
1493 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1494 /* For "Performance", the assumption is made that
1495 * downstream communication will never be larger than
1496 * the MRRS. So, the MPS only needs to be configured
1497 * for the upstream communication. This being the case,
1498 * walk from the top down and set the MPS of the child
1499 * to that of the parent bus.
1500 *
1501 * Configure the device MPS with the smaller of the
1502 * device MPSS or the bridge MPS (which is assumed to be
1503 * properly configured at this point to the largest
1504 * allowable MPS based on its parent bus).
1505 */
1506 mps = min(mps, pcie_get_mps(dev->bus->self));
1507 }
1508
1509 rc = pcie_set_mps(dev, mps);
1510 if (rc)
1511 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1512 }
1513
1514 static void pcie_write_mrrs(struct pci_dev *dev)
1515 {
1516 int rc, mrrs;
1517
1518 /* In the "safe" case, do not configure the MRRS. There appear to be
1519 * issues with setting MRRS to 0 on a number of devices.
1520 */
1521 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1522 return;
1523
1524 /* For Max performance, the MRRS must be set to the largest supported
1525 * value. However, it cannot be configured larger than the MPS the
1526 * device or the bus can support. This should already be properly
1527 * configured by a prior call to pcie_write_mps.
1528 */
1529 mrrs = pcie_get_mps(dev);
1530
1531 /* MRRS is a R/W register. Invalid values can be written, but a
1532 * subsequent read will verify if the value is acceptable or not.
1533 * If the MRRS value provided is not acceptable (e.g., too large),
1534 * shrink the value until it is acceptable to the HW.
1535 */
1536 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1537 rc = pcie_set_readrq(dev, mrrs);
1538 if (!rc)
1539 break;
1540
1541 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1542 mrrs /= 2;
1543 }
1544
1545 if (mrrs < 128)
1546 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1547 "safe value. If problems are experienced, try running "
1548 "with pci=pcie_bus_safe.\n");
1549 }
1550
1551 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1552 {
1553 int mps, orig_mps;
1554
1555 if (!pci_is_pcie(dev))
1556 return 0;
1557
1558 mps = 128 << *(u8 *)data;
1559 orig_mps = pcie_get_mps(dev);
1560
1561 pcie_write_mps(dev, mps);
1562 pcie_write_mrrs(dev);
1563
1564 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1565 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1566 orig_mps, pcie_get_readrq(dev));
1567
1568 return 0;
1569 }
1570
1571 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1572 * parents then children fashion. If this changes, then this code will not
1573 * work as designed.
1574 */
1575 void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1576 {
1577 u8 smpss;
1578
1579 if (!pci_is_pcie(bus->self))
1580 return;
1581
1582 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1583 return;
1584
1585 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1586 * to be aware to the MPS of the destination. To work around this,
1587 * simply force the MPS of the entire system to the smallest possible.
1588 */
1589 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1590 smpss = 0;
1591
1592 if (pcie_bus_config == PCIE_BUS_SAFE) {
1593 smpss = mpss;
1594
1595 pcie_find_smpss(bus->self, &smpss);
1596 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1597 }
1598
1599 pcie_bus_configure_set(bus->self, &smpss);
1600 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1601 }
1602 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1603
1604 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1605 {
1606 unsigned int devfn, pass, max = bus->secondary;
1607 struct pci_dev *dev;
1608
1609 dev_dbg(&bus->dev, "scanning bus\n");
1610
1611 /* Go find them, Rover! */
1612 for (devfn = 0; devfn < 0x100; devfn += 8)
1613 pci_scan_slot(bus, devfn);
1614
1615 /* Reserve buses for SR-IOV capability. */
1616 max += pci_iov_bus_range(bus);
1617
1618 /*
1619 * After performing arch-dependent fixup of the bus, look behind
1620 * all PCI-to-PCI bridges on this bus.
1621 */
1622 if (!bus->is_added) {
1623 dev_dbg(&bus->dev, "fixups for bus\n");
1624 pcibios_fixup_bus(bus);
1625 if (pci_is_root_bus(bus))
1626 bus->is_added = 1;
1627 }
1628
1629 for (pass=0; pass < 2; pass++)
1630 list_for_each_entry(dev, &bus->devices, bus_list) {
1631 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1632 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1633 max = pci_scan_bridge(bus, dev, max, pass);
1634 }
1635
1636 /*
1637 * We've scanned the bus and so we know all about what's on
1638 * the other side of any bridges that may be on this bus plus
1639 * any devices.
1640 *
1641 * Return how far we've got finding sub-buses.
1642 */
1643 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1644 return max;
1645 }
1646
1647 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1648 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1649 {
1650 int error;
1651 struct pci_host_bridge *bridge;
1652 struct pci_bus *b, *b2;
1653 struct device *dev;
1654 struct pci_host_bridge_window *window, *n;
1655 struct resource *res;
1656 resource_size_t offset;
1657 char bus_addr[64];
1658 char *fmt;
1659
1660 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
1661 if (!bridge)
1662 return NULL;
1663
1664 b = pci_alloc_bus();
1665 if (!b)
1666 goto err_bus;
1667
1668 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1669 if (!dev)
1670 goto err_dev;
1671
1672 b->sysdata = sysdata;
1673 b->ops = ops;
1674
1675 b2 = pci_find_bus(pci_domain_nr(b), bus);
1676 if (b2) {
1677 /* If we already got to this bus through a different bridge, ignore it */
1678 dev_dbg(&b2->dev, "bus already known\n");
1679 goto err_out;
1680 }
1681
1682 dev->parent = parent;
1683 dev->release = pci_release_bus_bridge_dev;
1684 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1685 error = device_register(dev);
1686 if (error)
1687 goto dev_reg_err;
1688 b->bridge = get_device(dev);
1689 device_enable_async_suspend(b->bridge);
1690 pci_set_bus_of_node(b);
1691
1692 if (!parent)
1693 set_dev_node(b->bridge, pcibus_to_node(b));
1694
1695 b->dev.class = &pcibus_class;
1696 b->dev.parent = b->bridge;
1697 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1698 error = device_register(&b->dev);
1699 if (error)
1700 goto class_dev_reg_err;
1701
1702 /* Create legacy_io and legacy_mem files for this bus */
1703 pci_create_legacy_files(b);
1704
1705 b->number = b->secondary = bus;
1706
1707 bridge->bus = b;
1708 INIT_LIST_HEAD(&bridge->windows);
1709
1710 if (parent)
1711 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1712 else
1713 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1714
1715 /* Add initial resources to the bus */
1716 list_for_each_entry_safe(window, n, resources, list) {
1717 list_move_tail(&window->list, &bridge->windows);
1718 res = window->res;
1719 offset = window->offset;
1720 pci_bus_add_resource(b, res, 0);
1721 if (offset) {
1722 if (resource_type(res) == IORESOURCE_IO)
1723 fmt = " (bus address [%#06llx-%#06llx])";
1724 else
1725 fmt = " (bus address [%#010llx-%#010llx])";
1726 snprintf(bus_addr, sizeof(bus_addr), fmt,
1727 (unsigned long long) (res->start - offset),
1728 (unsigned long long) (res->end - offset));
1729 } else
1730 bus_addr[0] = '\0';
1731 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1732 }
1733
1734 down_write(&pci_bus_sem);
1735 list_add_tail(&bridge->list, &pci_host_bridges);
1736 list_add_tail(&b->node, &pci_root_buses);
1737 up_write(&pci_bus_sem);
1738
1739 return b;
1740
1741 class_dev_reg_err:
1742 device_unregister(dev);
1743 dev_reg_err:
1744 down_write(&pci_bus_sem);
1745 list_del(&bridge->list);
1746 list_del(&b->node);
1747 up_write(&pci_bus_sem);
1748 err_out:
1749 kfree(dev);
1750 err_dev:
1751 kfree(b);
1752 err_bus:
1753 kfree(bridge);
1754 return NULL;
1755 }
1756
1757 struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1758 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1759 {
1760 struct pci_bus *b;
1761
1762 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1763 if (!b)
1764 return NULL;
1765
1766 b->subordinate = pci_scan_child_bus(b);
1767 pci_bus_add_devices(b);
1768 return b;
1769 }
1770 EXPORT_SYMBOL(pci_scan_root_bus);
1771
1772 /* Deprecated; use pci_scan_root_bus() instead */
1773 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1774 int bus, struct pci_ops *ops, void *sysdata)
1775 {
1776 LIST_HEAD(resources);
1777 struct pci_bus *b;
1778
1779 pci_add_resource(&resources, &ioport_resource);
1780 pci_add_resource(&resources, &iomem_resource);
1781 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1782 if (b)
1783 b->subordinate = pci_scan_child_bus(b);
1784 else
1785 pci_free_resource_list(&resources);
1786 return b;
1787 }
1788 EXPORT_SYMBOL(pci_scan_bus_parented);
1789
1790 struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
1791 void *sysdata)
1792 {
1793 LIST_HEAD(resources);
1794 struct pci_bus *b;
1795
1796 pci_add_resource(&resources, &ioport_resource);
1797 pci_add_resource(&resources, &iomem_resource);
1798 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1799 if (b) {
1800 b->subordinate = pci_scan_child_bus(b);
1801 pci_bus_add_devices(b);
1802 } else {
1803 pci_free_resource_list(&resources);
1804 }
1805 return b;
1806 }
1807 EXPORT_SYMBOL(pci_scan_bus);
1808
1809 #ifdef CONFIG_HOTPLUG
1810 /**
1811 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1812 * @bridge: PCI bridge for the bus to scan
1813 *
1814 * Scan a PCI bus and child buses for new devices, add them,
1815 * and enable them, resizing bridge mmio/io resource if necessary
1816 * and possible. The caller must ensure the child devices are already
1817 * removed for resizing to occur.
1818 *
1819 * Returns the max number of subordinate bus discovered.
1820 */
1821 unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1822 {
1823 unsigned int max;
1824 struct pci_bus *bus = bridge->subordinate;
1825
1826 max = pci_scan_child_bus(bus);
1827
1828 pci_assign_unassigned_bridge_resources(bridge);
1829
1830 pci_bus_add_devices(bus);
1831
1832 return max;
1833 }
1834
1835 EXPORT_SYMBOL(pci_add_new_bus);
1836 EXPORT_SYMBOL(pci_scan_slot);
1837 EXPORT_SYMBOL(pci_scan_bridge);
1838 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1839 #endif
1840
1841 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1842 {
1843 const struct pci_dev *a = to_pci_dev(d_a);
1844 const struct pci_dev *b = to_pci_dev(d_b);
1845
1846 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1847 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1848
1849 if (a->bus->number < b->bus->number) return -1;
1850 else if (a->bus->number > b->bus->number) return 1;
1851
1852 if (a->devfn < b->devfn) return -1;
1853 else if (a->devfn > b->devfn) return 1;
1854
1855 return 0;
1856 }
1857
1858 void __init pci_sort_breadthfirst(void)
1859 {
1860 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1861 }
(deprecated) Btrfs devel tree