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net: mv643xx_eth: update statistics timer from timer context only
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
blob44a87e4469e03440eef2d9d681e34422257f1f79
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 */
39
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42 #include <linux/init.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/in.h>
45 #include <linux/ip.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
58 #include <linux/io.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
63 #include <linux/of.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
67
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
70
71
72 /*
73 * Registers shared between all ports.
74 */
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
81
82 /*
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 */
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
151
152 /*
153 * Misc per-port registers.
154 */
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
159
160
161 /*
162 * SDMA configuration register default value.
163 */
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
171 BLM_RX_NO_SWAP | \
172 BLM_TX_NO_SWAP | \
173 TX_BURST_SIZE_4_64BIT)
174 #else
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #endif
177
178
179 /*
180 * Misc definitions.
181 */
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 256
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
185
186
187 /*
188 * RX/TX descriptors.
189 */
190 #if defined(__BIG_ENDIAN)
191 struct rx_desc {
192 u16 byte_cnt; /* Descriptor buffer byte count */
193 u16 buf_size; /* Buffer size */
194 u32 cmd_sts; /* Descriptor command status */
195 u32 next_desc_ptr; /* Next descriptor pointer */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 };
198
199 struct tx_desc {
200 u16 byte_cnt; /* buffer byte count */
201 u16 l4i_chk; /* CPU provided TCP checksum */
202 u32 cmd_sts; /* Command/status field */
203 u32 next_desc_ptr; /* Pointer to next descriptor */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 };
206 #elif defined(__LITTLE_ENDIAN)
207 struct rx_desc {
208 u32 cmd_sts; /* Descriptor command status */
209 u16 buf_size; /* Buffer size */
210 u16 byte_cnt; /* Descriptor buffer byte count */
211 u32 buf_ptr; /* Descriptor buffer pointer */
212 u32 next_desc_ptr; /* Next descriptor pointer */
213 };
214
215 struct tx_desc {
216 u32 cmd_sts; /* Command/status field */
217 u16 l4i_chk; /* CPU provided TCP checksum */
218 u16 byte_cnt; /* buffer byte count */
219 u32 buf_ptr; /* pointer to buffer for this descriptor*/
220 u32 next_desc_ptr; /* Pointer to next descriptor */
221 };
222 #else
223 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
224 #endif
225
226 /* RX & TX descriptor command */
227 #define BUFFER_OWNED_BY_DMA 0x80000000
228
229 /* RX & TX descriptor status */
230 #define ERROR_SUMMARY 0x00000001
231
232 /* RX descriptor status */
233 #define LAYER_4_CHECKSUM_OK 0x40000000
234 #define RX_ENABLE_INTERRUPT 0x20000000
235 #define RX_FIRST_DESC 0x08000000
236 #define RX_LAST_DESC 0x04000000
237 #define RX_IP_HDR_OK 0x02000000
238 #define RX_PKT_IS_IPV4 0x01000000
239 #define RX_PKT_IS_ETHERNETV2 0x00800000
240 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
241 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
242 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
243
244 /* TX descriptor command */
245 #define TX_ENABLE_INTERRUPT 0x00800000
246 #define GEN_CRC 0x00400000
247 #define TX_FIRST_DESC 0x00200000
248 #define TX_LAST_DESC 0x00100000
249 #define ZERO_PADDING 0x00080000
250 #define GEN_IP_V4_CHECKSUM 0x00040000
251 #define GEN_TCP_UDP_CHECKSUM 0x00020000
252 #define UDP_FRAME 0x00010000
253 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
255
256 #define TX_IHL_SHIFT 11
257
258
259 /* global *******************************************************************/
260 struct mv643xx_eth_shared_private {
261 /*
262 * Ethernet controller base address.
263 */
264 void __iomem *base;
265
266 /*
267 * Per-port MBUS window access register value.
268 */
269 u32 win_protect;
270
271 /*
272 * Hardware-specific parameters.
273 */
274 int extended_rx_coal_limit;
275 int tx_bw_control;
276 int tx_csum_limit;
277 struct clk *clk;
278 };
279
280 #define TX_BW_CONTROL_ABSENT 0
281 #define TX_BW_CONTROL_OLD_LAYOUT 1
282 #define TX_BW_CONTROL_NEW_LAYOUT 2
283
284 static int mv643xx_eth_open(struct net_device *dev);
285 static int mv643xx_eth_stop(struct net_device *dev);
286
287
288 /* per-port *****************************************************************/
289 struct mib_counters {
290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
309 u32 fc_sent;
310 u32 good_fc_received;
311 u32 bad_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
315 u32 jabber_received;
316 u32 mac_receive_error;
317 u32 bad_crc_event;
318 u32 collision;
319 u32 late_collision;
320 /* Non MIB hardware counters */
321 u32 rx_discard;
322 u32 rx_overrun;
323 };
324
325 struct rx_queue {
326 int index;
327
328 int rx_ring_size;
329
330 int rx_desc_count;
331 int rx_curr_desc;
332 int rx_used_desc;
333
334 struct rx_desc *rx_desc_area;
335 dma_addr_t rx_desc_dma;
336 int rx_desc_area_size;
337 struct sk_buff **rx_skb;
338 };
339
340 struct tx_queue {
341 int index;
342
343 int tx_ring_size;
344
345 int tx_desc_count;
346 int tx_curr_desc;
347 int tx_used_desc;
348
349 struct tx_desc *tx_desc_area;
350 dma_addr_t tx_desc_dma;
351 int tx_desc_area_size;
352
353 struct sk_buff_head tx_skb;
354
355 unsigned long tx_packets;
356 unsigned long tx_bytes;
357 unsigned long tx_dropped;
358 };
359
360 struct mv643xx_eth_private {
361 struct mv643xx_eth_shared_private *shared;
362 void __iomem *base;
363 int port_num;
364
365 struct net_device *dev;
366
367 struct phy_device *phy;
368
369 struct timer_list mib_counters_timer;
370 spinlock_t mib_counters_lock;
371 struct mib_counters mib_counters;
372
373 struct work_struct tx_timeout_task;
374
375 struct napi_struct napi;
376 u32 int_mask;
377 u8 oom;
378 u8 work_link;
379 u8 work_tx;
380 u8 work_tx_end;
381 u8 work_rx;
382 u8 work_rx_refill;
383
384 int skb_size;
385
386 /*
387 * RX state.
388 */
389 int rx_ring_size;
390 unsigned long rx_desc_sram_addr;
391 int rx_desc_sram_size;
392 int rxq_count;
393 struct timer_list rx_oom;
394 struct rx_queue rxq[8];
395
396 /*
397 * TX state.
398 */
399 int tx_ring_size;
400 unsigned long tx_desc_sram_addr;
401 int tx_desc_sram_size;
402 int txq_count;
403 struct tx_queue txq[8];
404
405 /*
406 * Hardware-specific parameters.
407 */
408 struct clk *clk;
409 unsigned int t_clk;
410 };
411
412
413 /* port register accessors **************************************************/
414 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
415 {
416 return readl(mp->shared->base + offset);
417 }
418
419 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
420 {
421 return readl(mp->base + offset);
422 }
423
424 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
425 {
426 writel(data, mp->shared->base + offset);
427 }
428
429 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
430 {
431 writel(data, mp->base + offset);
432 }
433
434
435 /* rxq/txq helper functions *************************************************/
436 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
437 {
438 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
439 }
440
441 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
442 {
443 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
444 }
445
446 static void rxq_enable(struct rx_queue *rxq)
447 {
448 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
449 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
450 }
451
452 static void rxq_disable(struct rx_queue *rxq)
453 {
454 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
455 u8 mask = 1 << rxq->index;
456
457 wrlp(mp, RXQ_COMMAND, mask << 8);
458 while (rdlp(mp, RXQ_COMMAND) & mask)
459 udelay(10);
460 }
461
462 static void txq_reset_hw_ptr(struct tx_queue *txq)
463 {
464 struct mv643xx_eth_private *mp = txq_to_mp(txq);
465 u32 addr;
466
467 addr = (u32)txq->tx_desc_dma;
468 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
469 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
470 }
471
472 static void txq_enable(struct tx_queue *txq)
473 {
474 struct mv643xx_eth_private *mp = txq_to_mp(txq);
475 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
476 }
477
478 static void txq_disable(struct tx_queue *txq)
479 {
480 struct mv643xx_eth_private *mp = txq_to_mp(txq);
481 u8 mask = 1 << txq->index;
482
483 wrlp(mp, TXQ_COMMAND, mask << 8);
484 while (rdlp(mp, TXQ_COMMAND) & mask)
485 udelay(10);
486 }
487
488 static void txq_maybe_wake(struct tx_queue *txq)
489 {
490 struct mv643xx_eth_private *mp = txq_to_mp(txq);
491 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
492
493 if (netif_tx_queue_stopped(nq)) {
494 __netif_tx_lock(nq, smp_processor_id());
495 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
496 netif_tx_wake_queue(nq);
497 __netif_tx_unlock(nq);
498 }
499 }
500
501 static int rxq_process(struct rx_queue *rxq, int budget)
502 {
503 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
504 struct net_device_stats *stats = &mp->dev->stats;
505 int rx;
506
507 rx = 0;
508 while (rx < budget && rxq->rx_desc_count) {
509 struct rx_desc *rx_desc;
510 unsigned int cmd_sts;
511 struct sk_buff *skb;
512 u16 byte_cnt;
513
514 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
515
516 cmd_sts = rx_desc->cmd_sts;
517 if (cmd_sts & BUFFER_OWNED_BY_DMA)
518 break;
519 rmb();
520
521 skb = rxq->rx_skb[rxq->rx_curr_desc];
522 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
523
524 rxq->rx_curr_desc++;
525 if (rxq->rx_curr_desc == rxq->rx_ring_size)
526 rxq->rx_curr_desc = 0;
527
528 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
529 rx_desc->buf_size, DMA_FROM_DEVICE);
530 rxq->rx_desc_count--;
531 rx++;
532
533 mp->work_rx_refill |= 1 << rxq->index;
534
535 byte_cnt = rx_desc->byte_cnt;
536
537 /*
538 * Update statistics.
539 *
540 * Note that the descriptor byte count includes 2 dummy
541 * bytes automatically inserted by the hardware at the
542 * start of the packet (which we don't count), and a 4
543 * byte CRC at the end of the packet (which we do count).
544 */
545 stats->rx_packets++;
546 stats->rx_bytes += byte_cnt - 2;
547
548 /*
549 * In case we received a packet without first / last bits
550 * on, or the error summary bit is set, the packet needs
551 * to be dropped.
552 */
553 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
554 != (RX_FIRST_DESC | RX_LAST_DESC))
555 goto err;
556
557 /*
558 * The -4 is for the CRC in the trailer of the
559 * received packet
560 */
561 skb_put(skb, byte_cnt - 2 - 4);
562
563 if (cmd_sts & LAYER_4_CHECKSUM_OK)
564 skb->ip_summed = CHECKSUM_UNNECESSARY;
565 skb->protocol = eth_type_trans(skb, mp->dev);
566
567 napi_gro_receive(&mp->napi, skb);
568
569 continue;
570
571 err:
572 stats->rx_dropped++;
573
574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
575 (RX_FIRST_DESC | RX_LAST_DESC)) {
576 if (net_ratelimit())
577 netdev_err(mp->dev,
578 "received packet spanning multiple descriptors\n");
579 }
580
581 if (cmd_sts & ERROR_SUMMARY)
582 stats->rx_errors++;
583
584 dev_kfree_skb(skb);
585 }
586
587 if (rx < budget)
588 mp->work_rx &= ~(1 << rxq->index);
589
590 return rx;
591 }
592
593 static int rxq_refill(struct rx_queue *rxq, int budget)
594 {
595 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
596 int refilled;
597
598 refilled = 0;
599 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
600 struct sk_buff *skb;
601 int rx;
602 struct rx_desc *rx_desc;
603 int size;
604
605 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
606
607 if (skb == NULL) {
608 mp->oom = 1;
609 goto oom;
610 }
611
612 if (SKB_DMA_REALIGN)
613 skb_reserve(skb, SKB_DMA_REALIGN);
614
615 refilled++;
616 rxq->rx_desc_count++;
617
618 rx = rxq->rx_used_desc++;
619 if (rxq->rx_used_desc == rxq->rx_ring_size)
620 rxq->rx_used_desc = 0;
621
622 rx_desc = rxq->rx_desc_area + rx;
623
624 size = skb_end_pointer(skb) - skb->data;
625 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
626 skb->data, size,
627 DMA_FROM_DEVICE);
628 rx_desc->buf_size = size;
629 rxq->rx_skb[rx] = skb;
630 wmb();
631 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
632 wmb();
633
634 /*
635 * The hardware automatically prepends 2 bytes of
636 * dummy data to each received packet, so that the
637 * IP header ends up 16-byte aligned.
638 */
639 skb_reserve(skb, 2);
640 }
641
642 if (refilled < budget)
643 mp->work_rx_refill &= ~(1 << rxq->index);
644
645 oom:
646 return refilled;
647 }
648
649
650 /* tx ***********************************************************************/
651 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
652 {
653 int frag;
654
655 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
656 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
657
658 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
659 return 1;
660 }
661
662 return 0;
663 }
664
665 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
666 {
667 struct mv643xx_eth_private *mp = txq_to_mp(txq);
668 int nr_frags = skb_shinfo(skb)->nr_frags;
669 int frag;
670
671 for (frag = 0; frag < nr_frags; frag++) {
672 skb_frag_t *this_frag;
673 int tx_index;
674 struct tx_desc *desc;
675
676 this_frag = &skb_shinfo(skb)->frags[frag];
677 tx_index = txq->tx_curr_desc++;
678 if (txq->tx_curr_desc == txq->tx_ring_size)
679 txq->tx_curr_desc = 0;
680 desc = &txq->tx_desc_area[tx_index];
681
682 /*
683 * The last fragment will generate an interrupt
684 * which will free the skb on TX completion.
685 */
686 if (frag == nr_frags - 1) {
687 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
688 ZERO_PADDING | TX_LAST_DESC |
689 TX_ENABLE_INTERRUPT;
690 } else {
691 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
692 }
693
694 desc->l4i_chk = 0;
695 desc->byte_cnt = skb_frag_size(this_frag);
696 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
697 this_frag, 0,
698 skb_frag_size(this_frag),
699 DMA_TO_DEVICE);
700 }
701 }
702
703 static inline __be16 sum16_as_be(__sum16 sum)
704 {
705 return (__force __be16)sum;
706 }
707
708 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
709 {
710 struct mv643xx_eth_private *mp = txq_to_mp(txq);
711 int nr_frags = skb_shinfo(skb)->nr_frags;
712 int tx_index;
713 struct tx_desc *desc;
714 u32 cmd_sts;
715 u16 l4i_chk;
716 int length;
717
718 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
719 l4i_chk = 0;
720
721 if (skb->ip_summed == CHECKSUM_PARTIAL) {
722 int hdr_len;
723 int tag_bytes;
724
725 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
726 skb->protocol != htons(ETH_P_8021Q));
727
728 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
729 tag_bytes = hdr_len - ETH_HLEN;
730 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
731 unlikely(tag_bytes & ~12)) {
732 if (skb_checksum_help(skb) == 0)
733 goto no_csum;
734 kfree_skb(skb);
735 return 1;
736 }
737
738 if (tag_bytes & 4)
739 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
740 if (tag_bytes & 8)
741 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
742
743 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
744 GEN_IP_V4_CHECKSUM |
745 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
746
747 switch (ip_hdr(skb)->protocol) {
748 case IPPROTO_UDP:
749 cmd_sts |= UDP_FRAME;
750 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
751 break;
752 case IPPROTO_TCP:
753 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
754 break;
755 default:
756 BUG();
757 }
758 } else {
759 no_csum:
760 /* Errata BTS #50, IHL must be 5 if no HW checksum */
761 cmd_sts |= 5 << TX_IHL_SHIFT;
762 }
763
764 tx_index = txq->tx_curr_desc++;
765 if (txq->tx_curr_desc == txq->tx_ring_size)
766 txq->tx_curr_desc = 0;
767 desc = &txq->tx_desc_area[tx_index];
768
769 if (nr_frags) {
770 txq_submit_frag_skb(txq, skb);
771 length = skb_headlen(skb);
772 } else {
773 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
774 length = skb->len;
775 }
776
777 desc->l4i_chk = l4i_chk;
778 desc->byte_cnt = length;
779 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
780 length, DMA_TO_DEVICE);
781
782 __skb_queue_tail(&txq->tx_skb, skb);
783
784 skb_tx_timestamp(skb);
785
786 /* ensure all other descriptors are written before first cmd_sts */
787 wmb();
788 desc->cmd_sts = cmd_sts;
789
790 /* clear TX_END status */
791 mp->work_tx_end &= ~(1 << txq->index);
792
793 /* ensure all descriptors are written before poking hardware */
794 wmb();
795 txq_enable(txq);
796
797 txq->tx_desc_count += nr_frags + 1;
798
799 return 0;
800 }
801
802 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
803 {
804 struct mv643xx_eth_private *mp = netdev_priv(dev);
805 int length, queue;
806 struct tx_queue *txq;
807 struct netdev_queue *nq;
808
809 queue = skb_get_queue_mapping(skb);
810 txq = mp->txq + queue;
811 nq = netdev_get_tx_queue(dev, queue);
812
813 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
814 txq->tx_dropped++;
815 netdev_printk(KERN_DEBUG, dev,
816 "failed to linearize skb with tiny unaligned fragment\n");
817 return NETDEV_TX_BUSY;
818 }
819
820 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
821 if (net_ratelimit())
822 netdev_err(dev, "tx queue full?!\n");
823 kfree_skb(skb);
824 return NETDEV_TX_OK;
825 }
826
827 length = skb->len;
828
829 if (!txq_submit_skb(txq, skb)) {
830 int entries_left;
831
832 txq->tx_bytes += length;
833 txq->tx_packets++;
834
835 entries_left = txq->tx_ring_size - txq->tx_desc_count;
836 if (entries_left < MAX_SKB_FRAGS + 1)
837 netif_tx_stop_queue(nq);
838 }
839
840 return NETDEV_TX_OK;
841 }
842
843
844 /* tx napi ******************************************************************/
845 static void txq_kick(struct tx_queue *txq)
846 {
847 struct mv643xx_eth_private *mp = txq_to_mp(txq);
848 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
849 u32 hw_desc_ptr;
850 u32 expected_ptr;
851
852 __netif_tx_lock(nq, smp_processor_id());
853
854 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
855 goto out;
856
857 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
858 expected_ptr = (u32)txq->tx_desc_dma +
859 txq->tx_curr_desc * sizeof(struct tx_desc);
860
861 if (hw_desc_ptr != expected_ptr)
862 txq_enable(txq);
863
864 out:
865 __netif_tx_unlock(nq);
866
867 mp->work_tx_end &= ~(1 << txq->index);
868 }
869
870 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
871 {
872 struct mv643xx_eth_private *mp = txq_to_mp(txq);
873 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
874 int reclaimed;
875
876 __netif_tx_lock_bh(nq);
877
878 reclaimed = 0;
879 while (reclaimed < budget && txq->tx_desc_count > 0) {
880 int tx_index;
881 struct tx_desc *desc;
882 u32 cmd_sts;
883 struct sk_buff *skb;
884
885 tx_index = txq->tx_used_desc;
886 desc = &txq->tx_desc_area[tx_index];
887 cmd_sts = desc->cmd_sts;
888
889 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
890 if (!force)
891 break;
892 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
893 }
894
895 txq->tx_used_desc = tx_index + 1;
896 if (txq->tx_used_desc == txq->tx_ring_size)
897 txq->tx_used_desc = 0;
898
899 reclaimed++;
900 txq->tx_desc_count--;
901
902 skb = NULL;
903 if (cmd_sts & TX_LAST_DESC)
904 skb = __skb_dequeue(&txq->tx_skb);
905
906 if (cmd_sts & ERROR_SUMMARY) {
907 netdev_info(mp->dev, "tx error\n");
908 mp->dev->stats.tx_errors++;
909 }
910
911 if (cmd_sts & TX_FIRST_DESC) {
912 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
913 desc->byte_cnt, DMA_TO_DEVICE);
914 } else {
915 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
916 desc->byte_cnt, DMA_TO_DEVICE);
917 }
918
919 dev_kfree_skb(skb);
920 }
921
922 __netif_tx_unlock_bh(nq);
923
924 if (reclaimed < budget)
925 mp->work_tx &= ~(1 << txq->index);
926
927 return reclaimed;
928 }
929
930
931 /* tx rate control **********************************************************/
932 /*
933 * Set total maximum TX rate (shared by all TX queues for this port)
934 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
935 */
936 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
937 {
938 int token_rate;
939 int mtu;
940 int bucket_size;
941
942 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
943 if (token_rate > 1023)
944 token_rate = 1023;
945
946 mtu = (mp->dev->mtu + 255) >> 8;
947 if (mtu > 63)
948 mtu = 63;
949
950 bucket_size = (burst + 255) >> 8;
951 if (bucket_size > 65535)
952 bucket_size = 65535;
953
954 switch (mp->shared->tx_bw_control) {
955 case TX_BW_CONTROL_OLD_LAYOUT:
956 wrlp(mp, TX_BW_RATE, token_rate);
957 wrlp(mp, TX_BW_MTU, mtu);
958 wrlp(mp, TX_BW_BURST, bucket_size);
959 break;
960 case TX_BW_CONTROL_NEW_LAYOUT:
961 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
962 wrlp(mp, TX_BW_MTU_MOVED, mtu);
963 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
964 break;
965 }
966 }
967
968 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
969 {
970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
971 int token_rate;
972 int bucket_size;
973
974 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
975 if (token_rate > 1023)
976 token_rate = 1023;
977
978 bucket_size = (burst + 255) >> 8;
979 if (bucket_size > 65535)
980 bucket_size = 65535;
981
982 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
983 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
984 }
985
986 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
987 {
988 struct mv643xx_eth_private *mp = txq_to_mp(txq);
989 int off;
990 u32 val;
991
992 /*
993 * Turn on fixed priority mode.
994 */
995 off = 0;
996 switch (mp->shared->tx_bw_control) {
997 case TX_BW_CONTROL_OLD_LAYOUT:
998 off = TXQ_FIX_PRIO_CONF;
999 break;
1000 case TX_BW_CONTROL_NEW_LAYOUT:
1001 off = TXQ_FIX_PRIO_CONF_MOVED;
1002 break;
1003 }
1004
1005 if (off) {
1006 val = rdlp(mp, off);
1007 val |= 1 << txq->index;
1008 wrlp(mp, off, val);
1009 }
1010 }
1011
1012
1013 /* mii management interface *************************************************/
1014 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1015 {
1016 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1017 u32 autoneg_disable = FORCE_LINK_PASS |
1018 DISABLE_AUTO_NEG_SPEED_GMII |
1019 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1020 DISABLE_AUTO_NEG_FOR_DUPLEX;
1021
1022 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1023 /* enable auto negotiation */
1024 pscr &= ~autoneg_disable;
1025 goto out_write;
1026 }
1027
1028 pscr |= autoneg_disable;
1029
1030 if (mp->phy->speed == SPEED_1000) {
1031 /* force gigabit, half duplex not supported */
1032 pscr |= SET_GMII_SPEED_TO_1000;
1033 pscr |= SET_FULL_DUPLEX_MODE;
1034 goto out_write;
1035 }
1036
1037 pscr &= ~SET_GMII_SPEED_TO_1000;
1038
1039 if (mp->phy->speed == SPEED_100)
1040 pscr |= SET_MII_SPEED_TO_100;
1041 else
1042 pscr &= ~SET_MII_SPEED_TO_100;
1043
1044 if (mp->phy->duplex == DUPLEX_FULL)
1045 pscr |= SET_FULL_DUPLEX_MODE;
1046 else
1047 pscr &= ~SET_FULL_DUPLEX_MODE;
1048
1049 out_write:
1050 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1051 }
1052
1053 /* statistics ***************************************************************/
1054 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1055 {
1056 struct mv643xx_eth_private *mp = netdev_priv(dev);
1057 struct net_device_stats *stats = &dev->stats;
1058 unsigned long tx_packets = 0;
1059 unsigned long tx_bytes = 0;
1060 unsigned long tx_dropped = 0;
1061 int i;
1062
1063 for (i = 0; i < mp->txq_count; i++) {
1064 struct tx_queue *txq = mp->txq + i;
1065
1066 tx_packets += txq->tx_packets;
1067 tx_bytes += txq->tx_bytes;
1068 tx_dropped += txq->tx_dropped;
1069 }
1070
1071 stats->tx_packets = tx_packets;
1072 stats->tx_bytes = tx_bytes;
1073 stats->tx_dropped = tx_dropped;
1074
1075 return stats;
1076 }
1077
1078 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1079 {
1080 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1081 }
1082
1083 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1084 {
1085 int i;
1086
1087 for (i = 0; i < 0x80; i += 4)
1088 mib_read(mp, i);
1089
1090 /* Clear non MIB hw counters also */
1091 rdlp(mp, RX_DISCARD_FRAME_CNT);
1092 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1093 }
1094
1095 static void mib_counters_update(struct mv643xx_eth_private *mp)
1096 {
1097 struct mib_counters *p = &mp->mib_counters;
1098
1099 spin_lock_bh(&mp->mib_counters_lock);
1100 p->good_octets_received += mib_read(mp, 0x00);
1101 p->bad_octets_received += mib_read(mp, 0x08);
1102 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1103 p->good_frames_received += mib_read(mp, 0x10);
1104 p->bad_frames_received += mib_read(mp, 0x14);
1105 p->broadcast_frames_received += mib_read(mp, 0x18);
1106 p->multicast_frames_received += mib_read(mp, 0x1c);
1107 p->frames_64_octets += mib_read(mp, 0x20);
1108 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1109 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1110 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1111 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1112 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1113 p->good_octets_sent += mib_read(mp, 0x38);
1114 p->good_frames_sent += mib_read(mp, 0x40);
1115 p->excessive_collision += mib_read(mp, 0x44);
1116 p->multicast_frames_sent += mib_read(mp, 0x48);
1117 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1118 p->unrec_mac_control_received += mib_read(mp, 0x50);
1119 p->fc_sent += mib_read(mp, 0x54);
1120 p->good_fc_received += mib_read(mp, 0x58);
1121 p->bad_fc_received += mib_read(mp, 0x5c);
1122 p->undersize_received += mib_read(mp, 0x60);
1123 p->fragments_received += mib_read(mp, 0x64);
1124 p->oversize_received += mib_read(mp, 0x68);
1125 p->jabber_received += mib_read(mp, 0x6c);
1126 p->mac_receive_error += mib_read(mp, 0x70);
1127 p->bad_crc_event += mib_read(mp, 0x74);
1128 p->collision += mib_read(mp, 0x78);
1129 p->late_collision += mib_read(mp, 0x7c);
1130 /* Non MIB hardware counters */
1131 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1132 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1133 spin_unlock_bh(&mp->mib_counters_lock);
1134 }
1135
1136 static void mib_counters_timer_wrapper(unsigned long _mp)
1137 {
1138 struct mv643xx_eth_private *mp = (void *)_mp;
1139 mib_counters_update(mp);
1140 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1141 }
1142
1143
1144 /* interrupt coalescing *****************************************************/
1145 /*
1146 * Hardware coalescing parameters are set in units of 64 t_clk
1147 * cycles. I.e.:
1148 *
1149 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1150 *
1151 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1152 *
1153 * In the ->set*() methods, we round the computed register value
1154 * to the nearest integer.
1155 */
1156 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1157 {
1158 u32 val = rdlp(mp, SDMA_CONFIG);
1159 u64 temp;
1160
1161 if (mp->shared->extended_rx_coal_limit)
1162 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1163 else
1164 temp = (val & 0x003fff00) >> 8;
1165
1166 temp *= 64000000;
1167 do_div(temp, mp->t_clk);
1168
1169 return (unsigned int)temp;
1170 }
1171
1172 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1173 {
1174 u64 temp;
1175 u32 val;
1176
1177 temp = (u64)usec * mp->t_clk;
1178 temp += 31999999;
1179 do_div(temp, 64000000);
1180
1181 val = rdlp(mp, SDMA_CONFIG);
1182 if (mp->shared->extended_rx_coal_limit) {
1183 if (temp > 0xffff)
1184 temp = 0xffff;
1185 val &= ~0x023fff80;
1186 val |= (temp & 0x8000) << 10;
1187 val |= (temp & 0x7fff) << 7;
1188 } else {
1189 if (temp > 0x3fff)
1190 temp = 0x3fff;
1191 val &= ~0x003fff00;
1192 val |= (temp & 0x3fff) << 8;
1193 }
1194 wrlp(mp, SDMA_CONFIG, val);
1195 }
1196
1197 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1198 {
1199 u64 temp;
1200
1201 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1202 temp *= 64000000;
1203 do_div(temp, mp->t_clk);
1204
1205 return (unsigned int)temp;
1206 }
1207
1208 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1209 {
1210 u64 temp;
1211
1212 temp = (u64)usec * mp->t_clk;
1213 temp += 31999999;
1214 do_div(temp, 64000000);
1215
1216 if (temp > 0x3fff)
1217 temp = 0x3fff;
1218
1219 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1220 }
1221
1222
1223 /* ethtool ******************************************************************/
1224 struct mv643xx_eth_stats {
1225 char stat_string[ETH_GSTRING_LEN];
1226 int sizeof_stat;
1227 int netdev_off;
1228 int mp_off;
1229 };
1230
1231 #define SSTAT(m) \
1232 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1233 offsetof(struct net_device, stats.m), -1 }
1234
1235 #define MIBSTAT(m) \
1236 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1237 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1238
1239 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1240 SSTAT(rx_packets),
1241 SSTAT(tx_packets),
1242 SSTAT(rx_bytes),
1243 SSTAT(tx_bytes),
1244 SSTAT(rx_errors),
1245 SSTAT(tx_errors),
1246 SSTAT(rx_dropped),
1247 SSTAT(tx_dropped),
1248 MIBSTAT(good_octets_received),
1249 MIBSTAT(bad_octets_received),
1250 MIBSTAT(internal_mac_transmit_err),
1251 MIBSTAT(good_frames_received),
1252 MIBSTAT(bad_frames_received),
1253 MIBSTAT(broadcast_frames_received),
1254 MIBSTAT(multicast_frames_received),
1255 MIBSTAT(frames_64_octets),
1256 MIBSTAT(frames_65_to_127_octets),
1257 MIBSTAT(frames_128_to_255_octets),
1258 MIBSTAT(frames_256_to_511_octets),
1259 MIBSTAT(frames_512_to_1023_octets),
1260 MIBSTAT(frames_1024_to_max_octets),
1261 MIBSTAT(good_octets_sent),
1262 MIBSTAT(good_frames_sent),
1263 MIBSTAT(excessive_collision),
1264 MIBSTAT(multicast_frames_sent),
1265 MIBSTAT(broadcast_frames_sent),
1266 MIBSTAT(unrec_mac_control_received),
1267 MIBSTAT(fc_sent),
1268 MIBSTAT(good_fc_received),
1269 MIBSTAT(bad_fc_received),
1270 MIBSTAT(undersize_received),
1271 MIBSTAT(fragments_received),
1272 MIBSTAT(oversize_received),
1273 MIBSTAT(jabber_received),
1274 MIBSTAT(mac_receive_error),
1275 MIBSTAT(bad_crc_event),
1276 MIBSTAT(collision),
1277 MIBSTAT(late_collision),
1278 MIBSTAT(rx_discard),
1279 MIBSTAT(rx_overrun),
1280 };
1281
1282 static int
1283 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1284 struct ethtool_cmd *cmd)
1285 {
1286 int err;
1287
1288 err = phy_read_status(mp->phy);
1289 if (err == 0)
1290 err = phy_ethtool_gset(mp->phy, cmd);
1291
1292 /*
1293 * The MAC does not support 1000baseT_Half.
1294 */
1295 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1296 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1297
1298 return err;
1299 }
1300
1301 static int
1302 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1303 struct ethtool_cmd *cmd)
1304 {
1305 u32 port_status;
1306
1307 port_status = rdlp(mp, PORT_STATUS);
1308
1309 cmd->supported = SUPPORTED_MII;
1310 cmd->advertising = ADVERTISED_MII;
1311 switch (port_status & PORT_SPEED_MASK) {
1312 case PORT_SPEED_10:
1313 ethtool_cmd_speed_set(cmd, SPEED_10);
1314 break;
1315 case PORT_SPEED_100:
1316 ethtool_cmd_speed_set(cmd, SPEED_100);
1317 break;
1318 case PORT_SPEED_1000:
1319 ethtool_cmd_speed_set(cmd, SPEED_1000);
1320 break;
1321 default:
1322 cmd->speed = -1;
1323 break;
1324 }
1325 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1326 cmd->port = PORT_MII;
1327 cmd->phy_address = 0;
1328 cmd->transceiver = XCVR_INTERNAL;
1329 cmd->autoneg = AUTONEG_DISABLE;
1330 cmd->maxtxpkt = 1;
1331 cmd->maxrxpkt = 1;
1332
1333 return 0;
1334 }
1335
1336 static void
1337 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1338 {
1339 struct mv643xx_eth_private *mp = netdev_priv(dev);
1340 wol->supported = 0;
1341 wol->wolopts = 0;
1342 if (mp->phy)
1343 phy_ethtool_get_wol(mp->phy, wol);
1344 }
1345
1346 static int
1347 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1348 {
1349 struct mv643xx_eth_private *mp = netdev_priv(dev);
1350 int err;
1351
1352 if (mp->phy == NULL)
1353 return -EOPNOTSUPP;
1354
1355 err = phy_ethtool_set_wol(mp->phy, wol);
1356 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1357 * this debugging hint is useful to have.
1358 */
1359 if (err == -EOPNOTSUPP)
1360 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1361 return err;
1362 }
1363
1364 static int
1365 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1366 {
1367 struct mv643xx_eth_private *mp = netdev_priv(dev);
1368
1369 if (mp->phy != NULL)
1370 return mv643xx_eth_get_settings_phy(mp, cmd);
1371 else
1372 return mv643xx_eth_get_settings_phyless(mp, cmd);
1373 }
1374
1375 static int
1376 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1377 {
1378 struct mv643xx_eth_private *mp = netdev_priv(dev);
1379 int ret;
1380
1381 if (mp->phy == NULL)
1382 return -EINVAL;
1383
1384 /*
1385 * The MAC does not support 1000baseT_Half.
1386 */
1387 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1388
1389 ret = phy_ethtool_sset(mp->phy, cmd);
1390 if (!ret)
1391 mv643xx_adjust_pscr(mp);
1392 return ret;
1393 }
1394
1395 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1396 struct ethtool_drvinfo *drvinfo)
1397 {
1398 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1399 sizeof(drvinfo->driver));
1400 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1401 sizeof(drvinfo->version));
1402 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1403 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1404 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1405 }
1406
1407 static int mv643xx_eth_nway_reset(struct net_device *dev)
1408 {
1409 struct mv643xx_eth_private *mp = netdev_priv(dev);
1410
1411 if (mp->phy == NULL)
1412 return -EINVAL;
1413
1414 return genphy_restart_aneg(mp->phy);
1415 }
1416
1417 static int
1418 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1419 {
1420 struct mv643xx_eth_private *mp = netdev_priv(dev);
1421
1422 ec->rx_coalesce_usecs = get_rx_coal(mp);
1423 ec->tx_coalesce_usecs = get_tx_coal(mp);
1424
1425 return 0;
1426 }
1427
1428 static int
1429 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1430 {
1431 struct mv643xx_eth_private *mp = netdev_priv(dev);
1432
1433 set_rx_coal(mp, ec->rx_coalesce_usecs);
1434 set_tx_coal(mp, ec->tx_coalesce_usecs);
1435
1436 return 0;
1437 }
1438
1439 static void
1440 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1441 {
1442 struct mv643xx_eth_private *mp = netdev_priv(dev);
1443
1444 er->rx_max_pending = 4096;
1445 er->tx_max_pending = 4096;
1446
1447 er->rx_pending = mp->rx_ring_size;
1448 er->tx_pending = mp->tx_ring_size;
1449 }
1450
1451 static int
1452 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1453 {
1454 struct mv643xx_eth_private *mp = netdev_priv(dev);
1455
1456 if (er->rx_mini_pending || er->rx_jumbo_pending)
1457 return -EINVAL;
1458
1459 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1460 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1461
1462 if (netif_running(dev)) {
1463 mv643xx_eth_stop(dev);
1464 if (mv643xx_eth_open(dev)) {
1465 netdev_err(dev,
1466 "fatal error on re-opening device after ring param change\n");
1467 return -ENOMEM;
1468 }
1469 }
1470
1471 return 0;
1472 }
1473
1474
1475 static int
1476 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1477 {
1478 struct mv643xx_eth_private *mp = netdev_priv(dev);
1479 bool rx_csum = features & NETIF_F_RXCSUM;
1480
1481 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1482
1483 return 0;
1484 }
1485
1486 static void mv643xx_eth_get_strings(struct net_device *dev,
1487 uint32_t stringset, uint8_t *data)
1488 {
1489 int i;
1490
1491 if (stringset == ETH_SS_STATS) {
1492 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1493 memcpy(data + i * ETH_GSTRING_LEN,
1494 mv643xx_eth_stats[i].stat_string,
1495 ETH_GSTRING_LEN);
1496 }
1497 }
1498 }
1499
1500 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1501 struct ethtool_stats *stats,
1502 uint64_t *data)
1503 {
1504 struct mv643xx_eth_private *mp = netdev_priv(dev);
1505 int i;
1506
1507 mv643xx_eth_get_stats(dev);
1508 mib_counters_update(mp);
1509
1510 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1511 const struct mv643xx_eth_stats *stat;
1512 void *p;
1513
1514 stat = mv643xx_eth_stats + i;
1515
1516 if (stat->netdev_off >= 0)
1517 p = ((void *)mp->dev) + stat->netdev_off;
1518 else
1519 p = ((void *)mp) + stat->mp_off;
1520
1521 data[i] = (stat->sizeof_stat == 8) ?
1522 *(uint64_t *)p : *(uint32_t *)p;
1523 }
1524 }
1525
1526 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1527 {
1528 if (sset == ETH_SS_STATS)
1529 return ARRAY_SIZE(mv643xx_eth_stats);
1530
1531 return -EOPNOTSUPP;
1532 }
1533
1534 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1535 .get_settings = mv643xx_eth_get_settings,
1536 .set_settings = mv643xx_eth_set_settings,
1537 .get_drvinfo = mv643xx_eth_get_drvinfo,
1538 .nway_reset = mv643xx_eth_nway_reset,
1539 .get_link = ethtool_op_get_link,
1540 .get_coalesce = mv643xx_eth_get_coalesce,
1541 .set_coalesce = mv643xx_eth_set_coalesce,
1542 .get_ringparam = mv643xx_eth_get_ringparam,
1543 .set_ringparam = mv643xx_eth_set_ringparam,
1544 .get_strings = mv643xx_eth_get_strings,
1545 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1546 .get_sset_count = mv643xx_eth_get_sset_count,
1547 .get_ts_info = ethtool_op_get_ts_info,
1548 .get_wol = mv643xx_eth_get_wol,
1549 .set_wol = mv643xx_eth_set_wol,
1550 };
1551
1552
1553 /* address handling *********************************************************/
1554 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1555 {
1556 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1557 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1558
1559 addr[0] = (mac_h >> 24) & 0xff;
1560 addr[1] = (mac_h >> 16) & 0xff;
1561 addr[2] = (mac_h >> 8) & 0xff;
1562 addr[3] = mac_h & 0xff;
1563 addr[4] = (mac_l >> 8) & 0xff;
1564 addr[5] = mac_l & 0xff;
1565 }
1566
1567 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1568 {
1569 wrlp(mp, MAC_ADDR_HIGH,
1570 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1571 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1572 }
1573
1574 static u32 uc_addr_filter_mask(struct net_device *dev)
1575 {
1576 struct netdev_hw_addr *ha;
1577 u32 nibbles;
1578
1579 if (dev->flags & IFF_PROMISC)
1580 return 0;
1581
1582 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1583 netdev_for_each_uc_addr(ha, dev) {
1584 if (memcmp(dev->dev_addr, ha->addr, 5))
1585 return 0;
1586 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1587 return 0;
1588
1589 nibbles |= 1 << (ha->addr[5] & 0x0f);
1590 }
1591
1592 return nibbles;
1593 }
1594
1595 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1596 {
1597 struct mv643xx_eth_private *mp = netdev_priv(dev);
1598 u32 port_config;
1599 u32 nibbles;
1600 int i;
1601
1602 uc_addr_set(mp, dev->dev_addr);
1603
1604 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1605
1606 nibbles = uc_addr_filter_mask(dev);
1607 if (!nibbles) {
1608 port_config |= UNICAST_PROMISCUOUS_MODE;
1609 nibbles = 0xffff;
1610 }
1611
1612 for (i = 0; i < 16; i += 4) {
1613 int off = UNICAST_TABLE(mp->port_num) + i;
1614 u32 v;
1615
1616 v = 0;
1617 if (nibbles & 1)
1618 v |= 0x00000001;
1619 if (nibbles & 2)
1620 v |= 0x00000100;
1621 if (nibbles & 4)
1622 v |= 0x00010000;
1623 if (nibbles & 8)
1624 v |= 0x01000000;
1625 nibbles >>= 4;
1626
1627 wrl(mp, off, v);
1628 }
1629
1630 wrlp(mp, PORT_CONFIG, port_config);
1631 }
1632
1633 static int addr_crc(unsigned char *addr)
1634 {
1635 int crc = 0;
1636 int i;
1637
1638 for (i = 0; i < 6; i++) {
1639 int j;
1640
1641 crc = (crc ^ addr[i]) << 8;
1642 for (j = 7; j >= 0; j--) {
1643 if (crc & (0x100 << j))
1644 crc ^= 0x107 << j;
1645 }
1646 }
1647
1648 return crc;
1649 }
1650
1651 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1652 {
1653 struct mv643xx_eth_private *mp = netdev_priv(dev);
1654 u32 *mc_spec;
1655 u32 *mc_other;
1656 struct netdev_hw_addr *ha;
1657 int i;
1658
1659 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1660 int port_num;
1661 u32 accept;
1662
1663 oom:
1664 port_num = mp->port_num;
1665 accept = 0x01010101;
1666 for (i = 0; i < 0x100; i += 4) {
1667 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1668 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1669 }
1670 return;
1671 }
1672
1673 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1674 if (mc_spec == NULL)
1675 goto oom;
1676 mc_other = mc_spec + (0x100 >> 2);
1677
1678 memset(mc_spec, 0, 0x100);
1679 memset(mc_other, 0, 0x100);
1680
1681 netdev_for_each_mc_addr(ha, dev) {
1682 u8 *a = ha->addr;
1683 u32 *table;
1684 int entry;
1685
1686 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1687 table = mc_spec;
1688 entry = a[5];
1689 } else {
1690 table = mc_other;
1691 entry = addr_crc(a);
1692 }
1693
1694 table[entry >> 2] |= 1 << (8 * (entry & 3));
1695 }
1696
1697 for (i = 0; i < 0x100; i += 4) {
1698 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1699 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1700 }
1701
1702 kfree(mc_spec);
1703 }
1704
1705 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1706 {
1707 mv643xx_eth_program_unicast_filter(dev);
1708 mv643xx_eth_program_multicast_filter(dev);
1709 }
1710
1711 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1712 {
1713 struct sockaddr *sa = addr;
1714
1715 if (!is_valid_ether_addr(sa->sa_data))
1716 return -EADDRNOTAVAIL;
1717
1718 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1719
1720 netif_addr_lock_bh(dev);
1721 mv643xx_eth_program_unicast_filter(dev);
1722 netif_addr_unlock_bh(dev);
1723
1724 return 0;
1725 }
1726
1727
1728 /* rx/tx queue initialisation ***********************************************/
1729 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1730 {
1731 struct rx_queue *rxq = mp->rxq + index;
1732 struct rx_desc *rx_desc;
1733 int size;
1734 int i;
1735
1736 rxq->index = index;
1737
1738 rxq->rx_ring_size = mp->rx_ring_size;
1739
1740 rxq->rx_desc_count = 0;
1741 rxq->rx_curr_desc = 0;
1742 rxq->rx_used_desc = 0;
1743
1744 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1745
1746 if (index == 0 && size <= mp->rx_desc_sram_size) {
1747 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1748 mp->rx_desc_sram_size);
1749 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1750 } else {
1751 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1752 size, &rxq->rx_desc_dma,
1753 GFP_KERNEL);
1754 }
1755
1756 if (rxq->rx_desc_area == NULL) {
1757 netdev_err(mp->dev,
1758 "can't allocate rx ring (%d bytes)\n", size);
1759 goto out;
1760 }
1761 memset(rxq->rx_desc_area, 0, size);
1762
1763 rxq->rx_desc_area_size = size;
1764 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1765 GFP_KERNEL);
1766 if (rxq->rx_skb == NULL)
1767 goto out_free;
1768
1769 rx_desc = rxq->rx_desc_area;
1770 for (i = 0; i < rxq->rx_ring_size; i++) {
1771 int nexti;
1772
1773 nexti = i + 1;
1774 if (nexti == rxq->rx_ring_size)
1775 nexti = 0;
1776
1777 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1778 nexti * sizeof(struct rx_desc);
1779 }
1780
1781 return 0;
1782
1783
1784 out_free:
1785 if (index == 0 && size <= mp->rx_desc_sram_size)
1786 iounmap(rxq->rx_desc_area);
1787 else
1788 dma_free_coherent(mp->dev->dev.parent, size,
1789 rxq->rx_desc_area,
1790 rxq->rx_desc_dma);
1791
1792 out:
1793 return -ENOMEM;
1794 }
1795
1796 static void rxq_deinit(struct rx_queue *rxq)
1797 {
1798 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1799 int i;
1800
1801 rxq_disable(rxq);
1802
1803 for (i = 0; i < rxq->rx_ring_size; i++) {
1804 if (rxq->rx_skb[i]) {
1805 dev_kfree_skb(rxq->rx_skb[i]);
1806 rxq->rx_desc_count--;
1807 }
1808 }
1809
1810 if (rxq->rx_desc_count) {
1811 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1812 rxq->rx_desc_count);
1813 }
1814
1815 if (rxq->index == 0 &&
1816 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1817 iounmap(rxq->rx_desc_area);
1818 else
1819 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1820 rxq->rx_desc_area, rxq->rx_desc_dma);
1821
1822 kfree(rxq->rx_skb);
1823 }
1824
1825 static int txq_init(struct mv643xx_eth_private *mp, int index)
1826 {
1827 struct tx_queue *txq = mp->txq + index;
1828 struct tx_desc *tx_desc;
1829 int size;
1830 int i;
1831
1832 txq->index = index;
1833
1834 txq->tx_ring_size = mp->tx_ring_size;
1835
1836 txq->tx_desc_count = 0;
1837 txq->tx_curr_desc = 0;
1838 txq->tx_used_desc = 0;
1839
1840 size = txq->tx_ring_size * sizeof(struct tx_desc);
1841
1842 if (index == 0 && size <= mp->tx_desc_sram_size) {
1843 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1844 mp->tx_desc_sram_size);
1845 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1846 } else {
1847 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1848 size, &txq->tx_desc_dma,
1849 GFP_KERNEL);
1850 }
1851
1852 if (txq->tx_desc_area == NULL) {
1853 netdev_err(mp->dev,
1854 "can't allocate tx ring (%d bytes)\n", size);
1855 return -ENOMEM;
1856 }
1857 memset(txq->tx_desc_area, 0, size);
1858
1859 txq->tx_desc_area_size = size;
1860
1861 tx_desc = txq->tx_desc_area;
1862 for (i = 0; i < txq->tx_ring_size; i++) {
1863 struct tx_desc *txd = tx_desc + i;
1864 int nexti;
1865
1866 nexti = i + 1;
1867 if (nexti == txq->tx_ring_size)
1868 nexti = 0;
1869
1870 txd->cmd_sts = 0;
1871 txd->next_desc_ptr = txq->tx_desc_dma +
1872 nexti * sizeof(struct tx_desc);
1873 }
1874
1875 skb_queue_head_init(&txq->tx_skb);
1876
1877 return 0;
1878 }
1879
1880 static void txq_deinit(struct tx_queue *txq)
1881 {
1882 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1883
1884 txq_disable(txq);
1885 txq_reclaim(txq, txq->tx_ring_size, 1);
1886
1887 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1888
1889 if (txq->index == 0 &&
1890 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1891 iounmap(txq->tx_desc_area);
1892 else
1893 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
1894 txq->tx_desc_area, txq->tx_desc_dma);
1895 }
1896
1897
1898 /* netdev ops and related ***************************************************/
1899 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1900 {
1901 u32 int_cause;
1902 u32 int_cause_ext;
1903
1904 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1905 if (int_cause == 0)
1906 return 0;
1907
1908 int_cause_ext = 0;
1909 if (int_cause & INT_EXT) {
1910 int_cause &= ~INT_EXT;
1911 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1912 }
1913
1914 if (int_cause) {
1915 wrlp(mp, INT_CAUSE, ~int_cause);
1916 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1917 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1918 mp->work_rx |= (int_cause & INT_RX) >> 2;
1919 }
1920
1921 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1922 if (int_cause_ext) {
1923 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1924 if (int_cause_ext & INT_EXT_LINK_PHY)
1925 mp->work_link = 1;
1926 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1927 }
1928
1929 return 1;
1930 }
1931
1932 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1933 {
1934 struct net_device *dev = (struct net_device *)dev_id;
1935 struct mv643xx_eth_private *mp = netdev_priv(dev);
1936
1937 if (unlikely(!mv643xx_eth_collect_events(mp)))
1938 return IRQ_NONE;
1939
1940 wrlp(mp, INT_MASK, 0);
1941 napi_schedule(&mp->napi);
1942
1943 return IRQ_HANDLED;
1944 }
1945
1946 static void handle_link_event(struct mv643xx_eth_private *mp)
1947 {
1948 struct net_device *dev = mp->dev;
1949 u32 port_status;
1950 int speed;
1951 int duplex;
1952 int fc;
1953
1954 port_status = rdlp(mp, PORT_STATUS);
1955 if (!(port_status & LINK_UP)) {
1956 if (netif_carrier_ok(dev)) {
1957 int i;
1958
1959 netdev_info(dev, "link down\n");
1960
1961 netif_carrier_off(dev);
1962
1963 for (i = 0; i < mp->txq_count; i++) {
1964 struct tx_queue *txq = mp->txq + i;
1965
1966 txq_reclaim(txq, txq->tx_ring_size, 1);
1967 txq_reset_hw_ptr(txq);
1968 }
1969 }
1970 return;
1971 }
1972
1973 switch (port_status & PORT_SPEED_MASK) {
1974 case PORT_SPEED_10:
1975 speed = 10;
1976 break;
1977 case PORT_SPEED_100:
1978 speed = 100;
1979 break;
1980 case PORT_SPEED_1000:
1981 speed = 1000;
1982 break;
1983 default:
1984 speed = -1;
1985 break;
1986 }
1987 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1988 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1989
1990 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
1991 speed, duplex ? "full" : "half", fc ? "en" : "dis");
1992
1993 if (!netif_carrier_ok(dev))
1994 netif_carrier_on(dev);
1995 }
1996
1997 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1998 {
1999 struct mv643xx_eth_private *mp;
2000 int work_done;
2001
2002 mp = container_of(napi, struct mv643xx_eth_private, napi);
2003
2004 if (unlikely(mp->oom)) {
2005 mp->oom = 0;
2006 del_timer(&mp->rx_oom);
2007 }
2008
2009 work_done = 0;
2010 while (work_done < budget) {
2011 u8 queue_mask;
2012 int queue;
2013 int work_tbd;
2014
2015 if (mp->work_link) {
2016 mp->work_link = 0;
2017 handle_link_event(mp);
2018 work_done++;
2019 continue;
2020 }
2021
2022 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2023 if (likely(!mp->oom))
2024 queue_mask |= mp->work_rx_refill;
2025
2026 if (!queue_mask) {
2027 if (mv643xx_eth_collect_events(mp))
2028 continue;
2029 break;
2030 }
2031
2032 queue = fls(queue_mask) - 1;
2033 queue_mask = 1 << queue;
2034
2035 work_tbd = budget - work_done;
2036 if (work_tbd > 16)
2037 work_tbd = 16;
2038
2039 if (mp->work_tx_end & queue_mask) {
2040 txq_kick(mp->txq + queue);
2041 } else if (mp->work_tx & queue_mask) {
2042 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2043 txq_maybe_wake(mp->txq + queue);
2044 } else if (mp->work_rx & queue_mask) {
2045 work_done += rxq_process(mp->rxq + queue, work_tbd);
2046 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2047 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2048 } else {
2049 BUG();
2050 }
2051 }
2052
2053 if (work_done < budget) {
2054 if (mp->oom)
2055 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2056 napi_complete(napi);
2057 wrlp(mp, INT_MASK, mp->int_mask);
2058 }
2059
2060 return work_done;
2061 }
2062
2063 static inline void oom_timer_wrapper(unsigned long data)
2064 {
2065 struct mv643xx_eth_private *mp = (void *)data;
2066
2067 napi_schedule(&mp->napi);
2068 }
2069
2070 static void phy_reset(struct mv643xx_eth_private *mp)
2071 {
2072 int data;
2073
2074 data = phy_read(mp->phy, MII_BMCR);
2075 if (data < 0)
2076 return;
2077
2078 data |= BMCR_RESET;
2079 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2080 return;
2081
2082 do {
2083 data = phy_read(mp->phy, MII_BMCR);
2084 } while (data >= 0 && data & BMCR_RESET);
2085 }
2086
2087 static void port_start(struct mv643xx_eth_private *mp)
2088 {
2089 u32 pscr;
2090 int i;
2091
2092 /*
2093 * Perform PHY reset, if there is a PHY.
2094 */
2095 if (mp->phy != NULL) {
2096 struct ethtool_cmd cmd;
2097
2098 mv643xx_eth_get_settings(mp->dev, &cmd);
2099 phy_reset(mp);
2100 mv643xx_eth_set_settings(mp->dev, &cmd);
2101 }
2102
2103 /*
2104 * Configure basic link parameters.
2105 */
2106 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2107
2108 pscr |= SERIAL_PORT_ENABLE;
2109 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2110
2111 pscr |= DO_NOT_FORCE_LINK_FAIL;
2112 if (mp->phy == NULL)
2113 pscr |= FORCE_LINK_PASS;
2114 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2115
2116 /*
2117 * Configure TX path and queues.
2118 */
2119 tx_set_rate(mp, 1000000000, 16777216);
2120 for (i = 0; i < mp->txq_count; i++) {
2121 struct tx_queue *txq = mp->txq + i;
2122
2123 txq_reset_hw_ptr(txq);
2124 txq_set_rate(txq, 1000000000, 16777216);
2125 txq_set_fixed_prio_mode(txq);
2126 }
2127
2128 /*
2129 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2130 * frames to RX queue #0, and include the pseudo-header when
2131 * calculating receive checksums.
2132 */
2133 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2134
2135 /*
2136 * Treat BPDUs as normal multicasts, and disable partition mode.
2137 */
2138 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2139
2140 /*
2141 * Add configured unicast addresses to address filter table.
2142 */
2143 mv643xx_eth_program_unicast_filter(mp->dev);
2144
2145 /*
2146 * Enable the receive queues.
2147 */
2148 for (i = 0; i < mp->rxq_count; i++) {
2149 struct rx_queue *rxq = mp->rxq + i;
2150 u32 addr;
2151
2152 addr = (u32)rxq->rx_desc_dma;
2153 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2154 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2155
2156 rxq_enable(rxq);
2157 }
2158 }
2159
2160 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2161 {
2162 int skb_size;
2163
2164 /*
2165 * Reserve 2+14 bytes for an ethernet header (the hardware
2166 * automatically prepends 2 bytes of dummy data to each
2167 * received packet), 16 bytes for up to four VLAN tags, and
2168 * 4 bytes for the trailing FCS -- 36 bytes total.
2169 */
2170 skb_size = mp->dev->mtu + 36;
2171
2172 /*
2173 * Make sure that the skb size is a multiple of 8 bytes, as
2174 * the lower three bits of the receive descriptor's buffer
2175 * size field are ignored by the hardware.
2176 */
2177 mp->skb_size = (skb_size + 7) & ~7;
2178
2179 /*
2180 * If NET_SKB_PAD is smaller than a cache line,
2181 * netdev_alloc_skb() will cause skb->data to be misaligned
2182 * to a cache line boundary. If this is the case, include
2183 * some extra space to allow re-aligning the data area.
2184 */
2185 mp->skb_size += SKB_DMA_REALIGN;
2186 }
2187
2188 static int mv643xx_eth_open(struct net_device *dev)
2189 {
2190 struct mv643xx_eth_private *mp = netdev_priv(dev);
2191 int err;
2192 int i;
2193
2194 wrlp(mp, INT_CAUSE, 0);
2195 wrlp(mp, INT_CAUSE_EXT, 0);
2196 rdlp(mp, INT_CAUSE_EXT);
2197
2198 err = request_irq(dev->irq, mv643xx_eth_irq,
2199 IRQF_SHARED, dev->name, dev);
2200 if (err) {
2201 netdev_err(dev, "can't assign irq\n");
2202 return -EAGAIN;
2203 }
2204
2205 mv643xx_eth_recalc_skb_size(mp);
2206
2207 napi_enable(&mp->napi);
2208
2209 mp->int_mask = INT_EXT;
2210
2211 for (i = 0; i < mp->rxq_count; i++) {
2212 err = rxq_init(mp, i);
2213 if (err) {
2214 while (--i >= 0)
2215 rxq_deinit(mp->rxq + i);
2216 goto out;
2217 }
2218
2219 rxq_refill(mp->rxq + i, INT_MAX);
2220 mp->int_mask |= INT_RX_0 << i;
2221 }
2222
2223 if (mp->oom) {
2224 mp->rx_oom.expires = jiffies + (HZ / 10);
2225 add_timer(&mp->rx_oom);
2226 }
2227
2228 for (i = 0; i < mp->txq_count; i++) {
2229 err = txq_init(mp, i);
2230 if (err) {
2231 while (--i >= 0)
2232 txq_deinit(mp->txq + i);
2233 goto out_free;
2234 }
2235 mp->int_mask |= INT_TX_END_0 << i;
2236 }
2237
2238 port_start(mp);
2239
2240 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2241 wrlp(mp, INT_MASK, mp->int_mask);
2242
2243 return 0;
2244
2245
2246 out_free:
2247 for (i = 0; i < mp->rxq_count; i++)
2248 rxq_deinit(mp->rxq + i);
2249 out:
2250 free_irq(dev->irq, dev);
2251
2252 return err;
2253 }
2254
2255 static void port_reset(struct mv643xx_eth_private *mp)
2256 {
2257 unsigned int data;
2258 int i;
2259
2260 for (i = 0; i < mp->rxq_count; i++)
2261 rxq_disable(mp->rxq + i);
2262 for (i = 0; i < mp->txq_count; i++)
2263 txq_disable(mp->txq + i);
2264
2265 while (1) {
2266 u32 ps = rdlp(mp, PORT_STATUS);
2267
2268 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2269 break;
2270 udelay(10);
2271 }
2272
2273 /* Reset the Enable bit in the Configuration Register */
2274 data = rdlp(mp, PORT_SERIAL_CONTROL);
2275 data &= ~(SERIAL_PORT_ENABLE |
2276 DO_NOT_FORCE_LINK_FAIL |
2277 FORCE_LINK_PASS);
2278 wrlp(mp, PORT_SERIAL_CONTROL, data);
2279 }
2280
2281 static int mv643xx_eth_stop(struct net_device *dev)
2282 {
2283 struct mv643xx_eth_private *mp = netdev_priv(dev);
2284 int i;
2285
2286 wrlp(mp, INT_MASK_EXT, 0x00000000);
2287 wrlp(mp, INT_MASK, 0x00000000);
2288 rdlp(mp, INT_MASK);
2289
2290 napi_disable(&mp->napi);
2291
2292 del_timer_sync(&mp->rx_oom);
2293
2294 netif_carrier_off(dev);
2295
2296 free_irq(dev->irq, dev);
2297
2298 port_reset(mp);
2299 mv643xx_eth_get_stats(dev);
2300 mib_counters_update(mp);
2301 del_timer_sync(&mp->mib_counters_timer);
2302
2303 for (i = 0; i < mp->rxq_count; i++)
2304 rxq_deinit(mp->rxq + i);
2305 for (i = 0; i < mp->txq_count; i++)
2306 txq_deinit(mp->txq + i);
2307
2308 return 0;
2309 }
2310
2311 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2312 {
2313 struct mv643xx_eth_private *mp = netdev_priv(dev);
2314 int ret;
2315
2316 if (mp->phy == NULL)
2317 return -ENOTSUPP;
2318
2319 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2320 if (!ret)
2321 mv643xx_adjust_pscr(mp);
2322 return ret;
2323 }
2324
2325 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2326 {
2327 struct mv643xx_eth_private *mp = netdev_priv(dev);
2328
2329 if (new_mtu < 64 || new_mtu > 9500)
2330 return -EINVAL;
2331
2332 dev->mtu = new_mtu;
2333 mv643xx_eth_recalc_skb_size(mp);
2334 tx_set_rate(mp, 1000000000, 16777216);
2335
2336 if (!netif_running(dev))
2337 return 0;
2338
2339 /*
2340 * Stop and then re-open the interface. This will allocate RX
2341 * skbs of the new MTU.
2342 * There is a possible danger that the open will not succeed,
2343 * due to memory being full.
2344 */
2345 mv643xx_eth_stop(dev);
2346 if (mv643xx_eth_open(dev)) {
2347 netdev_err(dev,
2348 "fatal error on re-opening device after MTU change\n");
2349 }
2350
2351 return 0;
2352 }
2353
2354 static void tx_timeout_task(struct work_struct *ugly)
2355 {
2356 struct mv643xx_eth_private *mp;
2357
2358 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2359 if (netif_running(mp->dev)) {
2360 netif_tx_stop_all_queues(mp->dev);
2361 port_reset(mp);
2362 port_start(mp);
2363 netif_tx_wake_all_queues(mp->dev);
2364 }
2365 }
2366
2367 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2368 {
2369 struct mv643xx_eth_private *mp = netdev_priv(dev);
2370
2371 netdev_info(dev, "tx timeout\n");
2372
2373 schedule_work(&mp->tx_timeout_task);
2374 }
2375
2376 #ifdef CONFIG_NET_POLL_CONTROLLER
2377 static void mv643xx_eth_netpoll(struct net_device *dev)
2378 {
2379 struct mv643xx_eth_private *mp = netdev_priv(dev);
2380
2381 wrlp(mp, INT_MASK, 0x00000000);
2382 rdlp(mp, INT_MASK);
2383
2384 mv643xx_eth_irq(dev->irq, dev);
2385
2386 wrlp(mp, INT_MASK, mp->int_mask);
2387 }
2388 #endif
2389
2390
2391 /* platform glue ************************************************************/
2392 static void
2393 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2394 const struct mbus_dram_target_info *dram)
2395 {
2396 void __iomem *base = msp->base;
2397 u32 win_enable;
2398 u32 win_protect;
2399 int i;
2400
2401 for (i = 0; i < 6; i++) {
2402 writel(0, base + WINDOW_BASE(i));
2403 writel(0, base + WINDOW_SIZE(i));
2404 if (i < 4)
2405 writel(0, base + WINDOW_REMAP_HIGH(i));
2406 }
2407
2408 win_enable = 0x3f;
2409 win_protect = 0;
2410
2411 for (i = 0; i < dram->num_cs; i++) {
2412 const struct mbus_dram_window *cs = dram->cs + i;
2413
2414 writel((cs->base & 0xffff0000) |
2415 (cs->mbus_attr << 8) |
2416 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2417 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2418
2419 win_enable &= ~(1 << i);
2420 win_protect |= 3 << (2 * i);
2421 }
2422
2423 writel(win_enable, base + WINDOW_BAR_ENABLE);
2424 msp->win_protect = win_protect;
2425 }
2426
2427 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2428 {
2429 /*
2430 * Check whether we have a 14-bit coal limit field in bits
2431 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2432 * SDMA config register.
2433 */
2434 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2435 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2436 msp->extended_rx_coal_limit = 1;
2437 else
2438 msp->extended_rx_coal_limit = 0;
2439
2440 /*
2441 * Check whether the MAC supports TX rate control, and if
2442 * yes, whether its associated registers are in the old or
2443 * the new place.
2444 */
2445 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2446 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2447 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2448 } else {
2449 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2450 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2451 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2452 else
2453 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2454 }
2455 }
2456
2457 #if defined(CONFIG_OF)
2458 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2459 { .compatible = "marvell,orion-eth", },
2460 { .compatible = "marvell,kirkwood-eth", },
2461 { }
2462 };
2463 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2464 #endif
2465
2466 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2467 #define mv643xx_eth_property(_np, _name, _v) \
2468 do { \
2469 u32 tmp; \
2470 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2471 _v = tmp; \
2472 } while (0)
2473
2474 static struct platform_device *port_platdev[3];
2475
2476 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2477 struct device_node *pnp)
2478 {
2479 struct platform_device *ppdev;
2480 struct mv643xx_eth_platform_data ppd;
2481 struct resource res;
2482 const char *mac_addr;
2483 int ret;
2484 int dev_num = 0;
2485
2486 memset(&ppd, 0, sizeof(ppd));
2487 ppd.shared = pdev;
2488
2489 memset(&res, 0, sizeof(res));
2490 if (!of_irq_to_resource(pnp, 0, &res)) {
2491 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2492 return -EINVAL;
2493 }
2494
2495 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2496 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2497 return -EINVAL;
2498 }
2499
2500 if (ppd.port_number >= 3) {
2501 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2502 return -EINVAL;
2503 }
2504
2505 while (dev_num < 3 && port_platdev[dev_num])
2506 dev_num++;
2507
2508 if (dev_num == 3) {
2509 dev_err(&pdev->dev, "too many ports registered\n");
2510 return -EINVAL;
2511 }
2512
2513 mac_addr = of_get_mac_address(pnp);
2514 if (mac_addr)
2515 memcpy(ppd.mac_addr, mac_addr, 6);
2516
2517 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2518 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2519 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2520 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2521 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2522 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2523
2524 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2525 if (!ppd.phy_node) {
2526 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2527 of_property_read_u32(pnp, "speed", &ppd.speed);
2528 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2529 }
2530
2531 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2532 if (!ppdev)
2533 return -ENOMEM;
2534 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2535
2536 ret = platform_device_add_resources(ppdev, &res, 1);
2537 if (ret)
2538 goto port_err;
2539
2540 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2541 if (ret)
2542 goto port_err;
2543
2544 ret = platform_device_add(ppdev);
2545 if (ret)
2546 goto port_err;
2547
2548 port_platdev[dev_num] = ppdev;
2549
2550 return 0;
2551
2552 port_err:
2553 platform_device_put(ppdev);
2554 return ret;
2555 }
2556
2557 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2558 {
2559 struct mv643xx_eth_shared_platform_data *pd;
2560 struct device_node *pnp, *np = pdev->dev.of_node;
2561 int ret;
2562
2563 /* bail out if not registered from DT */
2564 if (!np)
2565 return 0;
2566
2567 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2568 if (!pd)
2569 return -ENOMEM;
2570 pdev->dev.platform_data = pd;
2571
2572 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2573
2574 for_each_available_child_of_node(np, pnp) {
2575 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2576 if (ret)
2577 return ret;
2578 }
2579 return 0;
2580 }
2581
2582 static void mv643xx_eth_shared_of_remove(void)
2583 {
2584 int n;
2585
2586 for (n = 0; n < 3; n++) {
2587 platform_device_del(port_platdev[n]);
2588 port_platdev[n] = NULL;
2589 }
2590 }
2591 #else
2592 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2593 {
2594 return 0;
2595 }
2596
2597 static inline void mv643xx_eth_shared_of_remove(void)
2598 {
2599 }
2600 #endif
2601
2602 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2603 {
2604 static int mv643xx_eth_version_printed;
2605 struct mv643xx_eth_shared_platform_data *pd;
2606 struct mv643xx_eth_shared_private *msp;
2607 const struct mbus_dram_target_info *dram;
2608 struct resource *res;
2609 int ret;
2610
2611 if (!mv643xx_eth_version_printed++)
2612 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2613 mv643xx_eth_driver_version);
2614
2615 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2616 if (res == NULL)
2617 return -EINVAL;
2618
2619 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2620 if (msp == NULL)
2621 return -ENOMEM;
2622 platform_set_drvdata(pdev, msp);
2623
2624 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2625 if (msp->base == NULL)
2626 return -ENOMEM;
2627
2628 msp->clk = devm_clk_get(&pdev->dev, NULL);
2629 if (!IS_ERR(msp->clk))
2630 clk_prepare_enable(msp->clk);
2631
2632 /*
2633 * (Re-)program MBUS remapping windows if we are asked to.
2634 */
2635 dram = mv_mbus_dram_info();
2636 if (dram)
2637 mv643xx_eth_conf_mbus_windows(msp, dram);
2638
2639 ret = mv643xx_eth_shared_of_probe(pdev);
2640 if (ret)
2641 return ret;
2642 pd = dev_get_platdata(&pdev->dev);
2643
2644 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2645 pd->tx_csum_limit : 9 * 1024;
2646 infer_hw_params(msp);
2647
2648 return 0;
2649 }
2650
2651 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2652 {
2653 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2654
2655 mv643xx_eth_shared_of_remove();
2656 if (!IS_ERR(msp->clk))
2657 clk_disable_unprepare(msp->clk);
2658 return 0;
2659 }
2660
2661 static struct platform_driver mv643xx_eth_shared_driver = {
2662 .probe = mv643xx_eth_shared_probe,
2663 .remove = mv643xx_eth_shared_remove,
2664 .driver = {
2665 .name = MV643XX_ETH_SHARED_NAME,
2666 .owner = THIS_MODULE,
2667 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2668 },
2669 };
2670
2671 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2672 {
2673 int addr_shift = 5 * mp->port_num;
2674 u32 data;
2675
2676 data = rdl(mp, PHY_ADDR);
2677 data &= ~(0x1f << addr_shift);
2678 data |= (phy_addr & 0x1f) << addr_shift;
2679 wrl(mp, PHY_ADDR, data);
2680 }
2681
2682 static int phy_addr_get(struct mv643xx_eth_private *mp)
2683 {
2684 unsigned int data;
2685
2686 data = rdl(mp, PHY_ADDR);
2687
2688 return (data >> (5 * mp->port_num)) & 0x1f;
2689 }
2690
2691 static void set_params(struct mv643xx_eth_private *mp,
2692 struct mv643xx_eth_platform_data *pd)
2693 {
2694 struct net_device *dev = mp->dev;
2695
2696 if (is_valid_ether_addr(pd->mac_addr))
2697 memcpy(dev->dev_addr, pd->mac_addr, 6);
2698 else
2699 uc_addr_get(mp, dev->dev_addr);
2700
2701 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2702 if (pd->rx_queue_size)
2703 mp->rx_ring_size = pd->rx_queue_size;
2704 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2705 mp->rx_desc_sram_size = pd->rx_sram_size;
2706
2707 mp->rxq_count = pd->rx_queue_count ? : 1;
2708
2709 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2710 if (pd->tx_queue_size)
2711 mp->tx_ring_size = pd->tx_queue_size;
2712 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2713 mp->tx_desc_sram_size = pd->tx_sram_size;
2714
2715 mp->txq_count = pd->tx_queue_count ? : 1;
2716 }
2717
2718 static void mv643xx_eth_adjust_link(struct net_device *dev)
2719 {
2720 struct mv643xx_eth_private *mp = netdev_priv(dev);
2721
2722 mv643xx_adjust_pscr(mp);
2723 }
2724
2725 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2726 int phy_addr)
2727 {
2728 struct phy_device *phydev;
2729 int start;
2730 int num;
2731 int i;
2732 char phy_id[MII_BUS_ID_SIZE + 3];
2733
2734 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2735 start = phy_addr_get(mp) & 0x1f;
2736 num = 32;
2737 } else {
2738 start = phy_addr & 0x1f;
2739 num = 1;
2740 }
2741
2742 /* Attempt to connect to the PHY using orion-mdio */
2743 phydev = ERR_PTR(-ENODEV);
2744 for (i = 0; i < num; i++) {
2745 int addr = (start + i) & 0x1f;
2746
2747 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2748 "orion-mdio-mii", addr);
2749
2750 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2751 PHY_INTERFACE_MODE_GMII);
2752 if (!IS_ERR(phydev)) {
2753 phy_addr_set(mp, addr);
2754 break;
2755 }
2756 }
2757
2758 return phydev;
2759 }
2760
2761 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2762 {
2763 struct phy_device *phy = mp->phy;
2764
2765 phy_reset(mp);
2766
2767 if (speed == 0) {
2768 phy->autoneg = AUTONEG_ENABLE;
2769 phy->speed = 0;
2770 phy->duplex = 0;
2771 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2772 } else {
2773 phy->autoneg = AUTONEG_DISABLE;
2774 phy->advertising = 0;
2775 phy->speed = speed;
2776 phy->duplex = duplex;
2777 }
2778 phy_start_aneg(phy);
2779 }
2780
2781 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2782 {
2783 u32 pscr;
2784
2785 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2786 if (pscr & SERIAL_PORT_ENABLE) {
2787 pscr &= ~SERIAL_PORT_ENABLE;
2788 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2789 }
2790
2791 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2792 if (mp->phy == NULL) {
2793 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2794 if (speed == SPEED_1000)
2795 pscr |= SET_GMII_SPEED_TO_1000;
2796 else if (speed == SPEED_100)
2797 pscr |= SET_MII_SPEED_TO_100;
2798
2799 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2800
2801 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2802 if (duplex == DUPLEX_FULL)
2803 pscr |= SET_FULL_DUPLEX_MODE;
2804 }
2805
2806 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2807 }
2808
2809 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2810 .ndo_open = mv643xx_eth_open,
2811 .ndo_stop = mv643xx_eth_stop,
2812 .ndo_start_xmit = mv643xx_eth_xmit,
2813 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2814 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2815 .ndo_validate_addr = eth_validate_addr,
2816 .ndo_do_ioctl = mv643xx_eth_ioctl,
2817 .ndo_change_mtu = mv643xx_eth_change_mtu,
2818 .ndo_set_features = mv643xx_eth_set_features,
2819 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2820 .ndo_get_stats = mv643xx_eth_get_stats,
2821 #ifdef CONFIG_NET_POLL_CONTROLLER
2822 .ndo_poll_controller = mv643xx_eth_netpoll,
2823 #endif
2824 };
2825
2826 static int mv643xx_eth_probe(struct platform_device *pdev)
2827 {
2828 struct mv643xx_eth_platform_data *pd;
2829 struct mv643xx_eth_private *mp;
2830 struct net_device *dev;
2831 struct resource *res;
2832 int err;
2833
2834 pd = dev_get_platdata(&pdev->dev);
2835 if (pd == NULL) {
2836 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2837 return -ENODEV;
2838 }
2839
2840 if (pd->shared == NULL) {
2841 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2842 return -ENODEV;
2843 }
2844
2845 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2846 if (!dev)
2847 return -ENOMEM;
2848
2849 mp = netdev_priv(dev);
2850 platform_set_drvdata(pdev, mp);
2851
2852 mp->shared = platform_get_drvdata(pd->shared);
2853 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2854 mp->port_num = pd->port_number;
2855
2856 mp->dev = dev;
2857
2858 /* Kirkwood resets some registers on gated clocks. Especially
2859 * CLK125_BYPASS_EN must be cleared but is not available on
2860 * all other SoCs/System Controllers using this driver.
2861 */
2862 if (of_device_is_compatible(pdev->dev.of_node,
2863 "marvell,kirkwood-eth-port"))
2864 wrlp(mp, PORT_SERIAL_CONTROL1,
2865 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
2866
2867 /*
2868 * Start with a default rate, and if there is a clock, allow
2869 * it to override the default.
2870 */
2871 mp->t_clk = 133000000;
2872 mp->clk = devm_clk_get(&pdev->dev, NULL);
2873 if (!IS_ERR(mp->clk)) {
2874 clk_prepare_enable(mp->clk);
2875 mp->t_clk = clk_get_rate(mp->clk);
2876 } else if (!IS_ERR(mp->shared->clk)) {
2877 mp->t_clk = clk_get_rate(mp->shared->clk);
2878 }
2879
2880 set_params(mp, pd);
2881 netif_set_real_num_tx_queues(dev, mp->txq_count);
2882 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2883
2884 err = 0;
2885 if (pd->phy_node) {
2886 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
2887 mv643xx_eth_adjust_link, 0,
2888 PHY_INTERFACE_MODE_GMII);
2889 if (!mp->phy)
2890 err = -ENODEV;
2891 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
2892 mp->phy = phy_scan(mp, pd->phy_addr);
2893
2894 if (IS_ERR(mp->phy))
2895 err = PTR_ERR(mp->phy);
2896 else
2897 phy_init(mp, pd->speed, pd->duplex);
2898 }
2899 if (err == -ENODEV) {
2900 err = -EPROBE_DEFER;
2901 goto out;
2902 }
2903 if (err)
2904 goto out;
2905
2906 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2907
2908 init_pscr(mp, pd->speed, pd->duplex);
2909
2910
2911 mib_counters_clear(mp);
2912
2913 init_timer(&mp->mib_counters_timer);
2914 mp->mib_counters_timer.data = (unsigned long)mp;
2915 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2916 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2917 add_timer(&mp->mib_counters_timer);
2918
2919 spin_lock_init(&mp->mib_counters_lock);
2920
2921 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2922
2923 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2924
2925 init_timer(&mp->rx_oom);
2926 mp->rx_oom.data = (unsigned long)mp;
2927 mp->rx_oom.function = oom_timer_wrapper;
2928
2929
2930 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2931 BUG_ON(!res);
2932 dev->irq = res->start;
2933
2934 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2935
2936 dev->watchdog_timeo = 2 * HZ;
2937 dev->base_addr = 0;
2938
2939 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2940 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2941 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2942
2943 dev->priv_flags |= IFF_UNICAST_FLT;
2944
2945 SET_NETDEV_DEV(dev, &pdev->dev);
2946
2947 if (mp->shared->win_protect)
2948 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2949
2950 netif_carrier_off(dev);
2951
2952 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2953
2954 set_rx_coal(mp, 250);
2955 set_tx_coal(mp, 0);
2956
2957 err = register_netdev(dev);
2958 if (err)
2959 goto out;
2960
2961 netdev_notice(dev, "port %d with MAC address %pM\n",
2962 mp->port_num, dev->dev_addr);
2963
2964 if (mp->tx_desc_sram_size > 0)
2965 netdev_notice(dev, "configured with sram\n");
2966
2967 return 0;
2968
2969 out:
2970 if (!IS_ERR(mp->clk))
2971 clk_disable_unprepare(mp->clk);
2972 free_netdev(dev);
2973
2974 return err;
2975 }
2976
2977 static int mv643xx_eth_remove(struct platform_device *pdev)
2978 {
2979 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2980
2981 unregister_netdev(mp->dev);
2982 if (mp->phy != NULL)
2983 phy_disconnect(mp->phy);
2984 cancel_work_sync(&mp->tx_timeout_task);
2985
2986 if (!IS_ERR(mp->clk))
2987 clk_disable_unprepare(mp->clk);
2988
2989 free_netdev(mp->dev);
2990
2991 return 0;
2992 }
2993
2994 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2995 {
2996 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2997
2998 /* Mask all interrupts on ethernet port */
2999 wrlp(mp, INT_MASK, 0);
3000 rdlp(mp, INT_MASK);
3001
3002 if (netif_running(mp->dev))
3003 port_reset(mp);
3004 }
3005
3006 static struct platform_driver mv643xx_eth_driver = {
3007 .probe = mv643xx_eth_probe,
3008 .remove = mv643xx_eth_remove,
3009 .shutdown = mv643xx_eth_shutdown,
3010 .driver = {
3011 .name = MV643XX_ETH_NAME,
3012 .owner = THIS_MODULE,
3013 },
3014 };
3015
3016 static int __init mv643xx_eth_init_module(void)
3017 {
3018 int rc;
3019
3020 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3021 if (!rc) {
3022 rc = platform_driver_register(&mv643xx_eth_driver);
3023 if (rc)
3024 platform_driver_unregister(&mv643xx_eth_shared_driver);
3025 }
3026
3027 return rc;
3028 }
3029 module_init(mv643xx_eth_init_module);
3030
3031 static void __exit mv643xx_eth_cleanup_module(void)
3032 {
3033 platform_driver_unregister(&mv643xx_eth_driver);
3034 platform_driver_unregister(&mv643xx_eth_shared_driver);
3035 }
3036 module_exit(mv643xx_eth_cleanup_module);
3037
3038 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3039 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3040 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3041 MODULE_LICENSE("GPL");
3042 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3043 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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