1 * ARM Performance Monitor Units
3 ARM cores often have a PMU for counting cpu and cache events like cache misses
4 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
5 representation in the device tree should be done as under:-
9 - compatible : should be one of
22 - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
23 interrupt (PPI) then 1 interrupt should be specified.
27 - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
33 compatible = "arm,cortex-a9-pmu";
34 interrupts = <100 101>;