arch/powerpc/platforms/85xx/mpc85xx_cds.c

   1 /*
   2  * MPC85xx setup and early boot code plus other random bits.
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2005 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/console.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/root_dev.h>
  26 #include <linux/initrd.h>
  27 #include <linux/module.h>
  28 #include <linux/fsl_devices.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/page.h>
  33 #include <asm/atomic.h>
  34 #include <asm/time.h>
  35 #include <asm/io.h>
  36 #include <asm/machdep.h>
  37 #include <asm/ipic.h>
  38 #include <asm/bootinfo.h>
  39 #include <asm/pci-bridge.h>
  40 #include <asm/mpc85xx.h>
  41 #include <asm/irq.h>
  42 #include <mm/mmu_decl.h>
  43 #include <asm/prom.h>
  44 #include <asm/udbg.h>
  45 #include <asm/mpic.h>
  46 #include <asm/i8259.h>
  47
  48 #include <sysdev/fsl_soc.h>
  49 #include "mpc85xx.h"
  50
  51 #ifndef CONFIG_PCI
  52 unsigned long isa_io_base = 0;
  53 unsigned long isa_mem_base = 0;
  54 #endif
  55
  56 static int cds_pci_slot = 2;
  57 static volatile u8 *cadmus;
  58
  59
  60 #ifdef CONFIG_PCI
  61
  62 #define ARCADIA_HOST_BRIDGE_IDSEL       17
  63 #define ARCADIA_2ND_BRIDGE_IDSEL        3
  64
  65 extern int mpc85xx_pci2_busno;
  66
  67 int
  68 mpc85xx_exclude_device(u_char bus, u_char devfn)
  69 {
  70         if (bus == 0 && PCI_SLOT(devfn) == 0)
  71                 return PCIBIOS_DEVICE_NOT_FOUND;
  72         if (mpc85xx_pci2_busno)
  73                 if (bus == (mpc85xx_pci2_busno) && PCI_SLOT(devfn) == 0)
  74                         return PCIBIOS_DEVICE_NOT_FOUND;
  75         /* We explicitly do not go past the Tundra 320 Bridge */
  76         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  77                 return PCIBIOS_DEVICE_NOT_FOUND;
  78         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  79                 return PCIBIOS_DEVICE_NOT_FOUND;
  80         else
  81                 return PCIBIOS_SUCCESSFUL;
  82 }
  83
  84 void __init
  85 mpc85xx_cds_pcibios_fixup(void)
  86 {
  87         struct pci_dev *dev;
  88         u_char          c;
  89
  90         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
  91                                         PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
  92                 /*
  93                  * U-Boot does not set the enable bits
  94                  * for the IDE device. Force them on here.
  95                  */
  96                 pci_read_config_byte(dev, 0x40, &c);
  97                 c |= 0x03; /* IDE: Chip Enable Bits */
  98                 pci_write_config_byte(dev, 0x40, c);
  99
 100                 /*
 101                  * Since only primary interface works, force the
 102                  * IDE function to standard primary IDE interrupt
 103                  * w/ 8259 offset
 104                  */
 105                 dev->irq = 14;
 106                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 107                 pci_dev_put(dev);
 108         }
 109
 110         /*
 111          * Force legacy USB interrupt routing
 112          */
 113         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
 114                                         PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
 115                 dev->irq = 10;
 116                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
 117                 pci_dev_put(dev);
 118         }
 119
 120         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
 121                                         PCI_DEVICE_ID_VIA_82C586_2, dev))) {
 122                 dev->irq = 11;
 123                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
 124                 pci_dev_put(dev);
 125         }
 126
 127         /* Now map all the PCI irqs */
 128         dev = NULL;
 129         for_each_pci_dev(dev)
 130                 pci_read_irq_line(dev);
 131 }
 132
 133 #ifdef CONFIG_PPC_I8259
 134 #warning The i8259 PIC support is currently broken
 135 static void mpc85xx_8259_cascade(unsigned int irq, struct
 136                 irq_desc *desc, struct pt_regs *regs)
 137 {
 138         unsigned int cascade_irq = i8259_irq(regs);
 139
 140         if (cascade_irq != NO_IRQ)
 141                 generic_handle_irq(cascade_irq, regs);
 142
 143         desc->chip->eoi(irq);
 144 }
 145 #endif /* PPC_I8259 */
 146 #endif /* CONFIG_PCI */
 147
 148 void __init mpc85xx_cds_pic_init(void)
 149 {
 150         struct mpic *mpic;
 151         struct resource r;
 152         struct device_node *np = NULL;
 153         struct device_node *cascade_node = NULL;
 154         int cascade_irq;
 155
 156         np = of_find_node_by_type(np, "open-pic");
 157
 158         if (np == NULL) {
 159                 printk(KERN_ERR "Could not find open-pic node\n");
 160                 return;
 161         }
 162
 163         if (of_address_to_resource(np, 0, &r)) {
 164                 printk(KERN_ERR "Failed to map mpic register space\n");
 165                 of_node_put(np);
 166                 return;
 167         }
 168
 169         mpic = mpic_alloc(np, r.start,
 170                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 171                         4, 0, " OpenPIC  ");
 172         BUG_ON(mpic == NULL);
 173
 174         /* Return the mpic node */
 175         of_node_put(np);
 176
 177         mpic_assign_isu(mpic, 0, r.start + 0x10200);
 178         mpic_assign_isu(mpic, 1, r.start + 0x10280);
 179         mpic_assign_isu(mpic, 2, r.start + 0x10300);
 180         mpic_assign_isu(mpic, 3, r.start + 0x10380);
 181         mpic_assign_isu(mpic, 4, r.start + 0x10400);
 182         mpic_assign_isu(mpic, 5, r.start + 0x10480);
 183         mpic_assign_isu(mpic, 6, r.start + 0x10500);
 184         mpic_assign_isu(mpic, 7, r.start + 0x10580);
 185
 186         /* Used only for 8548 so far, but no harm in
 187          * allocating them for everyone */
 188         mpic_assign_isu(mpic, 8, r.start + 0x10600);
 189         mpic_assign_isu(mpic, 9, r.start + 0x10680);
 190         mpic_assign_isu(mpic, 10, r.start + 0x10700);
 191         mpic_assign_isu(mpic, 11, r.start + 0x10780);
 192
 193         /* External Interrupts */
 194         mpic_assign_isu(mpic, 12, r.start + 0x10000);
 195         mpic_assign_isu(mpic, 13, r.start + 0x10080);
 196         mpic_assign_isu(mpic, 14, r.start + 0x10100);
 197
 198         mpic_init(mpic);
 199
 200 #ifdef CONFIG_PPC_I8259
 201         /* Initialize the i8259 controller */
 202         for_each_node_by_type(np, "interrupt-controller")
 203                 if (device_is_compatible(np, "chrp,iic")) {
 204                         cascade_node = np;
 205                         break;
 206                 }
 207
 208         if (cascade_node == NULL) {
 209                 printk(KERN_DEBUG "Could not find i8259 PIC\n");
 210                 return;
 211         }
 212
 213         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 214         if (cascade_irq == NO_IRQ) {
 215                 printk(KERN_ERR "Failed to map cascade interrupt\n");
 216                 return;
 217         }
 218
 219         i8259_init(cascade_node, 0);
 220         of_node_put(cascade_node);
 221
 222         set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
 223 #endif /* CONFIG_PPC_I8259 */
 224 }
 225
 226
 227 /*
 228  * Setup the architecture
 229  */
 230 static void __init
 231 mpc85xx_cds_setup_arch(void)
 232 {
 233         struct device_node *cpu;
 234 #ifdef CONFIG_PCI
 235         struct device_node *np;
 236 #endif
 237
 238         if (ppc_md.progress)
 239                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 240
 241         cpu = of_find_node_by_type(NULL, "cpu");
 242         if (cpu != 0) {
 243                 const unsigned int *fp;
 244
 245                 fp = get_property(cpu, "clock-frequency", NULL);
 246                 if (fp != 0)
 247                         loops_per_jiffy = *fp / HZ;
 248                 else
 249                         loops_per_jiffy = 500000000 / HZ;
 250                 of_node_put(cpu);
 251         }
 252
 253         cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
 254         cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
 255
 256         if (ppc_md.progress) {
 257                 char buf[40];
 258                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
 259                                 cadmus[CM_VER], cds_pci_slot);
 260                 ppc_md.progress(buf, 0);
 261         }
 262
 263 #ifdef CONFIG_PCI
 264         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 265                 add_bridge(np);
 266
 267         ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
 268         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 269 #endif
 270
 271 #ifdef  CONFIG_ROOT_NFS
 272         ROOT_DEV = Root_NFS;
 273 #else
 274         ROOT_DEV = Root_HDA1;
 275 #endif
 276 }
 277
 278
 279 void
 280 mpc85xx_cds_show_cpuinfo(struct seq_file *m)
 281 {
 282         uint pvid, svid, phid1;
 283         uint memsize = total_memory;
 284
 285         pvid = mfspr(SPRN_PVR);
 286         svid = mfspr(SPRN_SVR);
 287
 288         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 289         seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
 290         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 291         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 292
 293         /* Display cpu Pll setting */
 294         phid1 = mfspr(SPRN_HID1);
 295         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 296
 297         /* Display the amount of memory */
 298         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 299 }
 300
 301
 302 /*
 303  * Called very early, device-tree isn't unflattened
 304  */
 305 static int __init mpc85xx_cds_probe(void)
 306 {
 307         /* We always match for now, eventually we should look at
 308          * the flat dev tree to ensure this is the board we are
 309          * supposed to run on
 310          */
 311         return 1;
 312 }
 313
 314 define_machine(mpc85xx_cds) {
 315         .name           = "MPC85xx CDS",
 316         .probe          = mpc85xx_cds_probe,
 317         .setup_arch     = mpc85xx_cds_setup_arch,
 318         .init_IRQ       = mpc85xx_cds_pic_init,
 319         .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
 320         .get_irq        = mpic_get_irq,
 321         .restart        = mpc85xx_restart,
 322         .calibrate_decr = generic_calibrate_decr,
 323         .progress       = udbg_progress,
 324 };