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bnx2x: remove unnecessary FUNC_FLG_RSS flag and related
[linux-2.6/btrfs-unstable.git] / drivers / net / bnx2x / bnx2x.h
blob556cad5ed01260ebb90f54e449743998eda79ada
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 #define DRV_MODULE_VERSION "1.60.00-1"
24 #define DRV_MODULE_RELDATE "2010/10/06"
25 #define BNX2X_BC_VER 0x040200
26
27 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
28 #define BCM_VLAN 1
29 #endif
30
31 #define BNX2X_MULTI_QUEUE
32
33 #define BNX2X_NEW_NAPI
34
35
36 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
37 #define BCM_CNIC 1
38 #include "../cnic_if.h"
39 #endif
40
41 #ifdef BCM_CNIC
42 #define BNX2X_MIN_MSIX_VEC_CNT 3
43 #define BNX2X_MSIX_VEC_FP_START 2
44 #else
45 #define BNX2X_MIN_MSIX_VEC_CNT 2
46 #define BNX2X_MSIX_VEC_FP_START 1
47 #endif
48
49 #include <linux/mdio.h>
50 #include <linux/pci.h>
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_hsi.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_stats.h"
56
57 /* error/debug prints */
58
59 #define DRV_MODULE_NAME "bnx2x"
60
61 /* for messages that are currently off */
62 #define BNX2X_MSG_OFF 0
63 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
64 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
65 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
68 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
69
70 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
71
72 /* regular debug print */
73 #define DP(__mask, __fmt, __args...) \
74 do { \
75 if (bp->msg_enable & (__mask)) \
76 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
77 __func__, __LINE__, \
78 bp->dev ? (bp->dev->name) : "?", \
79 ##__args); \
80 } while (0)
81
82 /* errors debug print */
83 #define BNX2X_DBG_ERR(__fmt, __args...) \
84 do { \
85 if (netif_msg_probe(bp)) \
86 pr_err("[%s:%d(%s)]" __fmt, \
87 __func__, __LINE__, \
88 bp->dev ? (bp->dev->name) : "?", \
89 ##__args); \
90 } while (0)
91
92 /* for errors (never masked) */
93 #define BNX2X_ERR(__fmt, __args...) \
94 do { \
95 pr_err("[%s:%d(%s)]" __fmt, \
96 __func__, __LINE__, \
97 bp->dev ? (bp->dev->name) : "?", \
98 ##__args); \
99 } while (0)
100
101 #define BNX2X_ERROR(__fmt, __args...) do { \
102 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
103 } while (0)
104
105
106 /* before we have a dev->name use dev_info() */
107 #define BNX2X_DEV_INFO(__fmt, __args...) \
108 do { \
109 if (netif_msg_probe(bp)) \
110 dev_info(&bp->pdev->dev, __fmt, ##__args); \
111 } while (0)
112
113 void bnx2x_panic_dump(struct bnx2x *bp);
114
115 #ifdef BNX2X_STOP_ON_ERROR
116 #define bnx2x_panic() do { \
117 bp->panic = 1; \
118 BNX2X_ERR("driver assert\n"); \
119 bnx2x_int_disable(bp); \
120 bnx2x_panic_dump(bp); \
121 } while (0)
122 #else
123 #define bnx2x_panic() do { \
124 bp->panic = 1; \
125 BNX2X_ERR("driver assert\n"); \
126 bnx2x_panic_dump(bp); \
127 } while (0)
128 #endif
129
130 #define bnx2x_mc_addr(ha) ((ha)->addr)
131
132 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
133 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
134 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
135
136
137 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
138
139 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
140 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
141 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
142
143 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
144 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
145 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
146
147 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
148 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
149
150 #define REG_RD_DMAE(bp, offset, valp, len32) \
151 do { \
152 bnx2x_read_dmae(bp, offset, len32);\
153 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
154 } while (0)
155
156 #define REG_WR_DMAE(bp, offset, valp, len32) \
157 do { \
158 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
159 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
160 offset, len32); \
161 } while (0)
162
163 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
164 REG_WR_DMAE(bp, offset, valp, len32)
165
166 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
167 do { \
168 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
169 bnx2x_write_big_buf_wb(bp, addr, len32); \
170 } while (0)
171
172 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
173 offsetof(struct shmem_region, field))
174 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
175 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
176
177 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
178 offsetof(struct shmem2_region, field))
179 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
180 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
181 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
182 offsetof(struct mf_cfg, field))
183 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
184 offsetof(struct mf2_cfg, field))
185
186 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
187 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
188 MF_CFG_ADDR(bp, field), (val))
189 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
190
191 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
192 (SHMEM2_RD((bp), size) > \
193 offsetof(struct shmem2_region, field)))
194
195 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
196 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
197
198 /* SP SB indices */
199
200 /* General SP events - stats query, cfc delete, etc */
201 #define HC_SP_INDEX_ETH_DEF_CONS 3
202
203 /* EQ completions */
204 #define HC_SP_INDEX_EQ_CONS 7
205
206 /* iSCSI L2 */
207 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
208 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
209
210 /**
211 * CIDs and CLIDs:
212 * CLIDs below is a CLID for func 0, then the CLID for other
213 * functions will be calculated by the formula:
214 *
215 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
216 *
217 */
218 /* iSCSI L2 */
219 #define BNX2X_ISCSI_ETH_CL_ID 17
220 #define BNX2X_ISCSI_ETH_CID 17
221
222 /** Additional rings budgeting */
223 #ifdef BCM_CNIC
224 #define CNIC_CONTEXT_USE 1
225 #else
226 #define CNIC_CONTEXT_USE 0
227 #endif /* BCM_CNIC */
228
229 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
230 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
231
232 #define SM_RX_ID 0
233 #define SM_TX_ID 1
234
235 /* fast path */
236
237 struct sw_rx_bd {
238 struct sk_buff *skb;
239 DEFINE_DMA_UNMAP_ADDR(mapping);
240 };
241
242 struct sw_tx_bd {
243 struct sk_buff *skb;
244 u16 first_bd;
245 u8 flags;
246 /* Set on the first BD descriptor when there is a split BD */
247 #define BNX2X_TSO_SPLIT_BD (1<<0)
248 };
249
250 struct sw_rx_page {
251 struct page *page;
252 DEFINE_DMA_UNMAP_ADDR(mapping);
253 };
254
255 union db_prod {
256 struct doorbell_set_prod data;
257 u32 raw;
258 };
259
260
261 /* MC hsi */
262 #define BCM_PAGE_SHIFT 12
263 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
264 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
265 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
266
267 #define PAGES_PER_SGE_SHIFT 0
268 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
269 #define SGE_PAGE_SIZE PAGE_SIZE
270 #define SGE_PAGE_SHIFT PAGE_SHIFT
271 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
272
273 /* SGE ring related macros */
274 #define NUM_RX_SGE_PAGES 2
275 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
276 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
277 /* RX_SGE_CNT is promised to be a power of 2 */
278 #define RX_SGE_MASK (RX_SGE_CNT - 1)
279 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
280 #define MAX_RX_SGE (NUM_RX_SGE - 1)
281 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
282 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
283 #define RX_SGE(x) ((x) & MAX_RX_SGE)
284
285 /* SGE producer mask related macros */
286 /* Number of bits in one sge_mask array element */
287 #define RX_SGE_MASK_ELEM_SZ 64
288 #define RX_SGE_MASK_ELEM_SHIFT 6
289 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
290
291 /* Creates a bitmask of all ones in less significant bits.
292 idx - index of the most significant bit in the created mask */
293 #define RX_SGE_ONES_MASK(idx) \
294 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
295 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
296
297 /* Number of u64 elements in SGE mask array */
298 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
299 RX_SGE_MASK_ELEM_SZ)
300 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
301 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
302
303 union host_hc_status_block {
304 /* pointer to fp status block e1x */
305 struct host_hc_status_block_e1x *e1x_sb;
306 /* pointer to fp status block e2 */
307 struct host_hc_status_block_e2 *e2_sb;
308 };
309
310 struct bnx2x_fastpath {
311
312 #define BNX2X_NAPI_WEIGHT 128
313 struct napi_struct napi;
314 union host_hc_status_block status_blk;
315 /* chip independed shortcuts into sb structure */
316 __le16 *sb_index_values;
317 __le16 *sb_running_index;
318 /* chip independed shortcut into rx_prods_offset memory */
319 u32 ustorm_rx_prods_offset;
320
321 dma_addr_t status_blk_mapping;
322
323 struct sw_tx_bd *tx_buf_ring;
324
325 union eth_tx_bd_types *tx_desc_ring;
326 dma_addr_t tx_desc_mapping;
327
328 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
329 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
330
331 struct eth_rx_bd *rx_desc_ring;
332 dma_addr_t rx_desc_mapping;
333
334 union eth_rx_cqe *rx_comp_ring;
335 dma_addr_t rx_comp_mapping;
336
337 /* SGE ring */
338 struct eth_rx_sge *rx_sge_ring;
339 dma_addr_t rx_sge_mapping;
340
341 u64 sge_mask[RX_SGE_MASK_LEN];
342
343 int state;
344 #define BNX2X_FP_STATE_CLOSED 0
345 #define BNX2X_FP_STATE_IRQ 0x80000
346 #define BNX2X_FP_STATE_OPENING 0x90000
347 #define BNX2X_FP_STATE_OPEN 0xa0000
348 #define BNX2X_FP_STATE_HALTING 0xb0000
349 #define BNX2X_FP_STATE_HALTED 0xc0000
350 #define BNX2X_FP_STATE_TERMINATING 0xd0000
351 #define BNX2X_FP_STATE_TERMINATED 0xe0000
352
353 u8 index; /* number in fp array */
354 u8 cl_id; /* eth client id */
355 u8 cl_qzone_id;
356 u8 fw_sb_id; /* status block number in FW */
357 u8 igu_sb_id; /* status block number in HW */
358 u32 cid;
359
360 union db_prod tx_db;
361
362 u16 tx_pkt_prod;
363 u16 tx_pkt_cons;
364 u16 tx_bd_prod;
365 u16 tx_bd_cons;
366 __le16 *tx_cons_sb;
367
368 __le16 fp_hc_idx;
369
370 u16 rx_bd_prod;
371 u16 rx_bd_cons;
372 u16 rx_comp_prod;
373 u16 rx_comp_cons;
374 u16 rx_sge_prod;
375 /* The last maximal completed SGE */
376 u16 last_max_sge;
377 __le16 *rx_cons_sb;
378
379 unsigned long tx_pkt,
380 rx_pkt,
381 rx_calls;
382
383 /* TPA related */
384 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
385 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
386 #define BNX2X_TPA_START 1
387 #define BNX2X_TPA_STOP 2
388 u8 disable_tpa;
389 #ifdef BNX2X_STOP_ON_ERROR
390 u64 tpa_queue_used;
391 #endif
392
393 struct tstorm_per_client_stats old_tclient;
394 struct ustorm_per_client_stats old_uclient;
395 struct xstorm_per_client_stats old_xclient;
396 struct bnx2x_eth_q_stats eth_q_stats;
397
398 /* The size is calculated using the following:
399 sizeof name field from netdev structure +
400 4 ('-Xx-' string) +
401 4 (for the digits and to make it DWORD aligned) */
402 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
403 char name[FP_NAME_SIZE];
404 struct bnx2x *bp; /* parent */
405 };
406
407 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
408
409
410 /* MC hsi */
411 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
412 #define RX_COPY_THRESH 92
413
414 #define NUM_TX_RINGS 16
415 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
416 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
417 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
418 #define MAX_TX_BD (NUM_TX_BD - 1)
419 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
420 #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL
421 #define INIT_TX_RING_SIZE MAX_TX_AVAIL
422 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
423 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
424 #define TX_BD(x) ((x) & MAX_TX_BD)
425 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
426
427 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
428 #define NUM_RX_RINGS 8
429 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
430 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
431 #define RX_DESC_MASK (RX_DESC_CNT - 1)
432 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
433 #define MAX_RX_BD (NUM_RX_BD - 1)
434 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
435 #define MIN_RX_AVAIL 128
436 #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL
437 #define INIT_RX_RING_SIZE MAX_RX_AVAIL
438 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
439 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
440 #define RX_BD(x) ((x) & MAX_RX_BD)
441
442 /* As long as CQE is 4 times bigger than BD entry we have to allocate
443 4 times more pages for CQ ring in order to keep it balanced with
444 BD ring */
445 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
446 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
447 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
448 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
449 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
450 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
451 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
452 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
453 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
454
455
456 /* This is needed for determining of last_max */
457 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
458
459 #define __SGE_MASK_SET_BIT(el, bit) \
460 do { \
461 el = ((el) | ((u64)0x1 << (bit))); \
462 } while (0)
463
464 #define __SGE_MASK_CLEAR_BIT(el, bit) \
465 do { \
466 el = ((el) & (~((u64)0x1 << (bit)))); \
467 } while (0)
468
469 #define SGE_MASK_SET_BIT(fp, idx) \
470 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
471 ((idx) & RX_SGE_MASK_ELEM_MASK))
472
473 #define SGE_MASK_CLEAR_BIT(fp, idx) \
474 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
475 ((idx) & RX_SGE_MASK_ELEM_MASK))
476
477
478 /* used on a CID received from the HW */
479 #define SW_CID(x) (le32_to_cpu(x) & \
480 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
481 #define CQE_CMD(x) (le32_to_cpu(x) >> \
482 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
483
484 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
485 le32_to_cpu((bd)->addr_lo))
486 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
487
488 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
489 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
490 #define DPM_TRIGER_TYPE 0x40
491 #define DOORBELL(bp, cid, val) \
492 do { \
493 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
494 DPM_TRIGER_TYPE); \
495 } while (0)
496
497
498 /* TX CSUM helpers */
499 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
500 skb->csum_offset)
501 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
502 skb->csum_offset))
503
504 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
505
506 #define XMIT_PLAIN 0
507 #define XMIT_CSUM_V4 0x1
508 #define XMIT_CSUM_V6 0x2
509 #define XMIT_CSUM_TCP 0x4
510 #define XMIT_GSO_V4 0x8
511 #define XMIT_GSO_V6 0x10
512
513 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
514 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
515
516
517 /* stuff added to make the code fit 80Col */
518
519 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
520
521 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
522 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
523 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
524 (TPA_TYPE_START | TPA_TYPE_END))
525
526 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
527
528 #define BNX2X_IP_CSUM_ERR(cqe) \
529 (!((cqe)->fast_path_cqe.status_flags & \
530 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
531 ((cqe)->fast_path_cqe.type_error_flags & \
532 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
533
534 #define BNX2X_L4_CSUM_ERR(cqe) \
535 (!((cqe)->fast_path_cqe.status_flags & \
536 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
537 ((cqe)->fast_path_cqe.type_error_flags & \
538 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
539
540 #define BNX2X_RX_CSUM_OK(cqe) \
541 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
542
543 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
544 (((le16_to_cpu(flags) & \
545 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
546 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
547 == PRS_FLAG_OVERETH_IPV4)
548 #define BNX2X_RX_SUM_FIX(cqe) \
549 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
550
551 #define U_SB_ETH_RX_CQ_INDEX 1
552 #define U_SB_ETH_RX_BD_INDEX 2
553 #define C_SB_ETH_TX_CQ_INDEX 5
554
555 #define BNX2X_RX_SB_INDEX \
556 (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX])
557
558 #define BNX2X_TX_SB_INDEX \
559 (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
560
561 /* end of fast path */
562
563 /* common */
564
565 struct bnx2x_common {
566
567 u32 chip_id;
568 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
569 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
570
571 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
572 #define CHIP_NUM_57710 0x164e
573 #define CHIP_NUM_57711 0x164f
574 #define CHIP_NUM_57711E 0x1650
575 #define CHIP_NUM_57712 0x1662
576 #define CHIP_NUM_57712E 0x1663
577 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
578 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
579 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
580 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
581 #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E)
582 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
583 CHIP_IS_57711E(bp))
584 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
585 CHIP_IS_57712E(bp))
586 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
587 #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp))
588
589 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
590 #define CHIP_REV_Ax 0x00000000
591 /* assume maximum 5 revisions */
592 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
593 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
594 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
595 !(CHIP_REV(bp) & 0x00001000))
596 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
597 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
598 (CHIP_REV(bp) & 0x00001000))
599
600 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
601 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
602
603 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
604 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
605
606 int flash_size;
607 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
608 #define NVRAM_TIMEOUT_COUNT 30000
609 #define NVRAM_PAGE_SIZE 256
610
611 u32 shmem_base;
612 u32 shmem2_base;
613 u32 mf_cfg_base;
614 u32 mf2_cfg_base;
615
616 u32 hw_config;
617
618 u32 bc_ver;
619
620 u8 int_block;
621 #define INT_BLOCK_HC 0
622 #define INT_BLOCK_IGU 1
623 #define INT_BLOCK_MODE_NORMAL 0
624 #define INT_BLOCK_MODE_BW_COMP 2
625 #define CHIP_INT_MODE_IS_NBC(bp) \
626 (CHIP_IS_E2(bp) && \
627 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
628 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
629
630 u8 chip_port_mode;
631 #define CHIP_4_PORT_MODE 0x0
632 #define CHIP_2_PORT_MODE 0x1
633 #define CHIP_PORT_MODE_NONE 0x2
634 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
635 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
636 };
637
638 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
639 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
640 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
641
642 /* end of common */
643
644 /* port */
645
646 struct bnx2x_port {
647 u32 pmf;
648
649 u32 link_config[LINK_CONFIG_SIZE];
650
651 u32 supported[LINK_CONFIG_SIZE];
652 /* link settings - missing defines */
653 #define SUPPORTED_2500baseX_Full (1 << 15)
654
655 u32 advertising[LINK_CONFIG_SIZE];
656 /* link settings - missing defines */
657 #define ADVERTISED_2500baseX_Full (1 << 15)
658
659 u32 phy_addr;
660
661 /* used to synchronize phy accesses */
662 struct mutex phy_mutex;
663 int need_hw_lock;
664
665 u32 port_stx;
666
667 struct nig_stats old_nig_stats;
668 };
669
670 /* end of port */
671
672 /* e1h Classification CAM line allocations */
673 enum {
674 CAM_ETH_LINE = 0,
675 CAM_ISCSI_ETH_LINE,
676 CAM_MAX_PF_LINE = CAM_ISCSI_ETH_LINE
677 };
678
679 #define BNX2X_VF_ID_INVALID 0xFF
680
681 /*
682 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
683 * control by the number of fast-path status blocks supported by the
684 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
685 * status block represents an independent interrupts context that can
686 * serve a regular L2 networking queue. However special L2 queues such
687 * as the FCoE queue do not require a FP-SB and other components like
688 * the CNIC may consume FP-SB reducing the number of possible L2 queues
689 *
690 * If the maximum number of FP-SB available is X then:
691 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
692 * regular L2 queues is Y=X-1
693 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
694 * c. If the FCoE L2 queue is supported the actual number of L2 queues
695 * is Y+1
696 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
697 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
698 * FP interrupt context for the CNIC).
699 * e. The number of HW context (CID count) is always X or X+1 if FCoE
700 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
701 */
702
703 #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */
704 #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */
705
706 /*
707 * cid_cnt paramter below refers to the value returned by
708 * 'bnx2x_get_l2_cid_count()' routine
709 */
710
711 /*
712 * The number of FP context allocated by the driver == max number of regular
713 * L2 queues + 1 for the FCoE L2 queue
714 */
715 #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
716
717 union cdu_context {
718 struct eth_context eth;
719 char pad[1024];
720 };
721
722 /* CDU host DB constants */
723 #define CDU_ILT_PAGE_SZ_HW 3
724 #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
725 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
726
727 #ifdef BCM_CNIC
728 #define CNIC_ISCSI_CID_MAX 256
729 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX)
730 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
731 #endif
732
733 #define QM_ILT_PAGE_SZ_HW 3
734 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */
735 #define QM_CID_ROUND 1024
736
737 #ifdef BCM_CNIC
738 /* TM (timers) host DB constants */
739 #define TM_ILT_PAGE_SZ_HW 2
740 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */
741 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
742 #define TM_CONN_NUM 1024
743 #define TM_ILT_SZ (8 * TM_CONN_NUM)
744 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
745
746 /* SRC (Searcher) host DB constants */
747 #define SRC_ILT_PAGE_SZ_HW 3
748 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */
749 #define SRC_HASH_BITS 10
750 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
751 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
752 #define SRC_T2_SZ SRC_ILT_SZ
753 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
754 #endif
755
756 #define MAX_DMAE_C 8
757
758 /* DMA memory not used in fastpath */
759 struct bnx2x_slowpath {
760 struct eth_stats_query fw_stats;
761 struct mac_configuration_cmd mac_config;
762 struct mac_configuration_cmd mcast_config;
763 struct client_init_ramrod_data client_init_data;
764
765 /* used by dmae command executer */
766 struct dmae_command dmae[MAX_DMAE_C];
767
768 u32 stats_comp;
769 union mac_stats mac_stats;
770 struct nig_stats nig_stats;
771 struct host_port_stats port_stats;
772 struct host_func_stats func_stats;
773 struct host_func_stats func_stats_base;
774
775 u32 wb_comp;
776 u32 wb_data[4];
777 };
778
779 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
780 #define bnx2x_sp_mapping(bp, var) \
781 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
782
783
784 /* attn group wiring */
785 #define MAX_DYNAMIC_ATTN_GRPS 8
786
787 struct attn_route {
788 u32 sig[5];
789 };
790
791 struct iro {
792 u32 base;
793 u16 m1;
794 u16 m2;
795 u16 m3;
796 u16 size;
797 };
798
799 struct hw_context {
800 union cdu_context *vcxt;
801 dma_addr_t cxt_mapping;
802 size_t size;
803 };
804
805 /* forward */
806 struct bnx2x_ilt;
807
808 typedef enum {
809 BNX2X_RECOVERY_DONE,
810 BNX2X_RECOVERY_INIT,
811 BNX2X_RECOVERY_WAIT,
812 } bnx2x_recovery_state_t;
813
814 /**
815 * Event queue (EQ or event ring) MC hsi
816 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
817 */
818 #define NUM_EQ_PAGES 1
819 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
820 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
821 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
822 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
823 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
824
825 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
826 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
827 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
828
829 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
830 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
831
832 #define BNX2X_EQ_INDEX \
833 (&bp->def_status_blk->sp_sb.\
834 index_values[HC_SP_INDEX_EQ_CONS])
835
836 struct bnx2x {
837 /* Fields used in the tx and intr/napi performance paths
838 * are grouped together in the beginning of the structure
839 */
840 struct bnx2x_fastpath *fp;
841 void __iomem *regview;
842 void __iomem *doorbells;
843 u16 db_size;
844
845 struct net_device *dev;
846 struct pci_dev *pdev;
847
848 struct iro *iro_arr;
849 #define IRO (bp->iro_arr)
850
851 atomic_t intr_sem;
852
853 bnx2x_recovery_state_t recovery_state;
854 int is_leader;
855 struct msix_entry *msix_table;
856 #define INT_MODE_INTx 1
857 #define INT_MODE_MSI 2
858
859 int tx_ring_size;
860
861 #ifdef BCM_VLAN
862 struct vlan_group *vlgrp;
863 #endif
864
865 u32 rx_csum;
866 u32 rx_buf_size;
867 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
868 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
869 #define ETH_MIN_PACKET_SIZE 60
870 #define ETH_MAX_PACKET_SIZE 1500
871 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
872
873 /* Max supported alignment is 256 (8 shift) */
874 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
875 L1_CACHE_SHIFT : 8)
876 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
877 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
878
879 struct host_sp_status_block *def_status_blk;
880 #define DEF_SB_IGU_ID 16
881 #define DEF_SB_ID HC_SP_SB_ID
882 __le16 def_idx;
883 __le16 def_att_idx;
884 u32 attn_state;
885 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
886
887 /* slow path ring */
888 struct eth_spe *spq;
889 dma_addr_t spq_mapping;
890 u16 spq_prod_idx;
891 struct eth_spe *spq_prod_bd;
892 struct eth_spe *spq_last_bd;
893 __le16 *dsb_sp_prod;
894 atomic_t spq_left; /* serialize spq */
895 /* used to synchronize spq accesses */
896 spinlock_t spq_lock;
897
898 /* event queue */
899 union event_ring_elem *eq_ring;
900 dma_addr_t eq_mapping;
901 u16 eq_prod;
902 u16 eq_cons;
903 __le16 *eq_cons_sb;
904
905 /* Flags for marking that there is a STAT_QUERY or
906 SET_MAC ramrod pending */
907 int stats_pending;
908 int set_mac_pending;
909
910 /* End of fields used in the performance code paths */
911
912 int panic;
913 int msg_enable;
914
915 u32 flags;
916 #define PCIX_FLAG 1
917 #define PCI_32BIT_FLAG 2
918 #define ONE_PORT_FLAG 4
919 #define NO_WOL_FLAG 8
920 #define USING_DAC_FLAG 0x10
921 #define USING_MSIX_FLAG 0x20
922 #define USING_MSI_FLAG 0x40
923
924 #define TPA_ENABLE_FLAG 0x80
925 #define NO_MCP_FLAG 0x100
926 #define DISABLE_MSI_FLAG 0x200
927 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
928 #define HW_VLAN_TX_FLAG 0x400
929 #define HW_VLAN_RX_FLAG 0x800
930 #define MF_FUNC_DIS 0x1000
931
932 int pf_num; /* absolute PF number */
933 int pfid; /* per-path PF number */
934 int base_fw_ndsb;
935 #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \
936 0 : (bp->pf_num & 1))
937 #define BP_PORT(bp) (bp->pfid & 1)
938 #define BP_FUNC(bp) (bp->pfid)
939 #define BP_ABS_FUNC(bp) (bp->pf_num)
940 #define BP_E1HVN(bp) (bp->pfid >> 1)
941 #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \
942 0 : BP_E1HVN(bp))
943 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
944 #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
945 BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1))
946
947 #ifdef BCM_CNIC
948 #define BCM_CNIC_CID_START 16
949 #define BCM_ISCSI_ETH_CL_ID 17
950 #endif
951
952 int pm_cap;
953 int pcie_cap;
954 int mrrs;
955
956 struct delayed_work sp_task;
957 struct delayed_work reset_task;
958 struct timer_list timer;
959 int current_interval;
960
961 u16 fw_seq;
962 u16 fw_drv_pulse_wr_seq;
963 u32 func_stx;
964
965 struct link_params link_params;
966 struct link_vars link_vars;
967 struct mdio_if_info mdio;
968
969 struct bnx2x_common common;
970 struct bnx2x_port port;
971
972 struct cmng_struct_per_port cmng;
973 u32 vn_weight_sum;
974
975 u32 mf_config[E1HVN_MAX];
976 u32 mf2_config[E2_FUNC_MAX];
977 u16 mf_ov;
978 u8 mf_mode;
979 #define IS_MF(bp) (bp->mf_mode != 0)
980
981 u8 wol;
982
983 int rx_ring_size;
984
985 u16 tx_quick_cons_trip_int;
986 u16 tx_quick_cons_trip;
987 u16 tx_ticks_int;
988 u16 tx_ticks;
989
990 u16 rx_quick_cons_trip_int;
991 u16 rx_quick_cons_trip;
992 u16 rx_ticks_int;
993 u16 rx_ticks;
994 /* Maximal coalescing timeout in us */
995 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
996
997 u32 lin_cnt;
998
999 int state;
1000 #define BNX2X_STATE_CLOSED 0
1001 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1002 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1003 #define BNX2X_STATE_OPEN 0x3000
1004 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1005 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1006 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
1007 #define BNX2X_STATE_FUNC_STARTED 0x7000
1008 #define BNX2X_STATE_DIAG 0xe000
1009 #define BNX2X_STATE_ERROR 0xf000
1010
1011 int multi_mode;
1012 int num_queues;
1013 int disable_tpa;
1014 int int_mode;
1015
1016 struct tstorm_eth_mac_filter_config mac_filters;
1017 #define BNX2X_ACCEPT_NONE 0x0000
1018 #define BNX2X_ACCEPT_UNICAST 0x0001
1019 #define BNX2X_ACCEPT_MULTICAST 0x0002
1020 #define BNX2X_ACCEPT_ALL_UNICAST 0x0004
1021 #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008
1022 #define BNX2X_ACCEPT_BROADCAST 0x0010
1023 #define BNX2X_PROMISCUOUS_MODE 0x10000
1024
1025 u32 rx_mode;
1026 #define BNX2X_RX_MODE_NONE 0
1027 #define BNX2X_RX_MODE_NORMAL 1
1028 #define BNX2X_RX_MODE_ALLMULTI 2
1029 #define BNX2X_RX_MODE_PROMISC 3
1030 #define BNX2X_MAX_MULTICAST 64
1031 #define BNX2X_MAX_EMUL_MULTI 16
1032
1033 u8 igu_dsb_id;
1034 u8 igu_base_sb;
1035 u8 igu_sb_cnt;
1036 dma_addr_t def_status_blk_mapping;
1037
1038 struct bnx2x_slowpath *slowpath;
1039 dma_addr_t slowpath_mapping;
1040 struct hw_context context;
1041
1042 struct bnx2x_ilt *ilt;
1043 #define BP_ILT(bp) ((bp)->ilt)
1044 #define ILT_MAX_LINES 128
1045
1046 int l2_cid_count;
1047 #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
1048 ILT_PAGE_CIDS))
1049 #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
1050
1051 int qm_cid_count;
1052
1053 int dropless_fc;
1054
1055 #ifdef BCM_CNIC
1056 u32 cnic_flags;
1057 #define BNX2X_CNIC_FLAG_MAC_SET 1
1058 void *t2;
1059 dma_addr_t t2_mapping;
1060 struct cnic_ops *cnic_ops;
1061 void *cnic_data;
1062 u32 cnic_tag;
1063 struct cnic_eth_dev cnic_eth_dev;
1064 union host_hc_status_block cnic_sb;
1065 dma_addr_t cnic_sb_mapping;
1066 #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp))
1067 #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb)
1068 struct eth_spe *cnic_kwq;
1069 struct eth_spe *cnic_kwq_prod;
1070 struct eth_spe *cnic_kwq_cons;
1071 struct eth_spe *cnic_kwq_last;
1072 u16 cnic_kwq_pending;
1073 u16 cnic_spq_pending;
1074 struct mutex cnic_mutex;
1075 u8 iscsi_mac[6];
1076 #endif
1077
1078 int dmae_ready;
1079 /* used to synchronize dmae accesses */
1080 struct mutex dmae_mutex;
1081
1082 /* used to protect the FW mail box */
1083 struct mutex fw_mb_mutex;
1084
1085 /* used to synchronize stats collecting */
1086 int stats_state;
1087
1088 /* used for synchronization of concurrent threads statistics handling */
1089 spinlock_t stats_lock;
1090
1091 /* used by dmae command loader */
1092 struct dmae_command stats_dmae;
1093 int executer_idx;
1094
1095 u16 stats_counter;
1096 struct bnx2x_eth_stats eth_stats;
1097
1098 struct z_stream_s *strm;
1099 void *gunzip_buf;
1100 dma_addr_t gunzip_mapping;
1101 int gunzip_outlen;
1102 #define FW_BUF_SIZE 0x8000
1103 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1104 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1105 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1106
1107 struct raw_op *init_ops;
1108 /* Init blocks offsets inside init_ops */
1109 u16 *init_ops_offsets;
1110 /* Data blob - has 32 bit granularity */
1111 u32 *init_data;
1112 /* Zipped PRAM blobs - raw data */
1113 const u8 *tsem_int_table_data;
1114 const u8 *tsem_pram_data;
1115 const u8 *usem_int_table_data;
1116 const u8 *usem_pram_data;
1117 const u8 *xsem_int_table_data;
1118 const u8 *xsem_pram_data;
1119 const u8 *csem_int_table_data;
1120 const u8 *csem_pram_data;
1121 #define INIT_OPS(bp) (bp->init_ops)
1122 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1123 #define INIT_DATA(bp) (bp->init_data)
1124 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1125 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1126 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1127 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1128 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1129 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1130 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1131 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1132
1133 char fw_ver[32];
1134 const struct firmware *firmware;
1135 };
1136
1137 /**
1138 * Init queue/func interface
1139 */
1140 /* queue init flags */
1141 #define QUEUE_FLG_TPA 0x0001
1142 #define QUEUE_FLG_CACHE_ALIGN 0x0002
1143 #define QUEUE_FLG_STATS 0x0004
1144 #define QUEUE_FLG_OV 0x0008
1145 #define QUEUE_FLG_VLAN 0x0010
1146 #define QUEUE_FLG_COS 0x0020
1147 #define QUEUE_FLG_HC 0x0040
1148 #define QUEUE_FLG_DHC 0x0080
1149 #define QUEUE_FLG_OOO 0x0100
1150
1151 #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR
1152 #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR
1153 #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0
1154 #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR
1155
1156
1157
1158 /* rss capabilities */
1159 #define RSS_IPV4_CAP 0x0001
1160 #define RSS_IPV4_TCP_CAP 0x0002
1161 #define RSS_IPV6_CAP 0x0004
1162 #define RSS_IPV6_TCP_CAP 0x0008
1163
1164 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1165 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1166
1167 #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
1168 #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1)
1169
1170 #define RSS_IPV4_CAP_MASK \
1171 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1172
1173 #define RSS_IPV4_TCP_CAP_MASK \
1174 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1175
1176 #define RSS_IPV6_CAP_MASK \
1177 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1178
1179 #define RSS_IPV6_TCP_CAP_MASK \
1180 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1181
1182 /* func init flags */
1183 #define FUNC_FLG_STATS 0x0001
1184 #define FUNC_FLG_TPA 0x0002
1185 #define FUNC_FLG_SPQ 0x0004
1186 #define FUNC_FLG_LEADING 0x0008 /* PF only */
1187
1188 struct rxq_pause_params {
1189 u16 bd_th_lo;
1190 u16 bd_th_hi;
1191 u16 rcq_th_lo;
1192 u16 rcq_th_hi;
1193 u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */
1194 u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */
1195 u16 pri_map;
1196 };
1197
1198 struct bnx2x_rxq_init_params {
1199 /* cxt*/
1200 struct eth_context *cxt;
1201
1202 /* dma */
1203 dma_addr_t dscr_map;
1204 dma_addr_t sge_map;
1205 dma_addr_t rcq_map;
1206 dma_addr_t rcq_np_map;
1207
1208 u16 flags;
1209 u16 drop_flags;
1210 u16 mtu;
1211 u16 buf_sz;
1212 u16 fw_sb_id;
1213 u16 cl_id;
1214 u16 spcl_id;
1215 u16 cl_qzone_id;
1216
1217 /* valid iff QUEUE_FLG_STATS */
1218 u16 stat_id;
1219
1220 /* valid iff QUEUE_FLG_TPA */
1221 u16 tpa_agg_sz;
1222 u16 sge_buf_sz;
1223 u16 max_sges_pkt;
1224
1225 /* valid iff QUEUE_FLG_CACHE_ALIGN */
1226 u8 cache_line_log;
1227
1228 u8 sb_cq_index;
1229 u32 cid;
1230
1231 /* desired interrupts per sec. valid iff QUEUE_FLG_HC */
1232 u32 hc_rate;
1233 };
1234
1235 struct bnx2x_txq_init_params {
1236 /* cxt*/
1237 struct eth_context *cxt;
1238
1239 /* dma */
1240 dma_addr_t dscr_map;
1241
1242 u16 flags;
1243 u16 fw_sb_id;
1244 u8 sb_cq_index;
1245 u8 cos; /* valid iff QUEUE_FLG_COS */
1246 u16 stat_id; /* valid iff QUEUE_FLG_STATS */
1247 u16 traffic_type;
1248 u32 cid;
1249 u16 hc_rate; /* desired interrupts per sec.*/
1250 /* valid iff QUEUE_FLG_HC */
1251
1252 };
1253
1254 struct bnx2x_client_ramrod_params {
1255 int *pstate;
1256 int state;
1257 u16 index;
1258 u16 cl_id;
1259 u32 cid;
1260 u8 poll;
1261 #define CLIENT_IS_LEADING_RSS 0x02
1262 u8 flags;
1263 };
1264
1265 struct bnx2x_client_init_params {
1266 struct rxq_pause_params pause;
1267 struct bnx2x_rxq_init_params rxq_params;
1268 struct bnx2x_txq_init_params txq_params;
1269 struct bnx2x_client_ramrod_params ramrod_params;
1270 };
1271
1272 struct bnx2x_rss_params {
1273 int mode;
1274 u16 cap;
1275 u16 result_mask;
1276 };
1277
1278 struct bnx2x_func_init_params {
1279
1280 /* rss */
1281 struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */
1282
1283 /* dma */
1284 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1285 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1286
1287 u16 func_flgs;
1288 u16 func_id; /* abs fid */
1289 u16 pf_id;
1290 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1291 };
1292
1293 #define for_each_queue(bp, var) \
1294 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1295 #define for_each_nondefault_queue(bp, var) \
1296 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1297
1298
1299 #define WAIT_RAMROD_POLL 0x01
1300 #define WAIT_RAMROD_COMMON 0x02
1301 int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
1302 int *state_p, int flags);
1303
1304 /* dmae */
1305 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1306 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1307 u32 len32);
1308 void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1309 u32 addr, u32 len);
1310 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1311 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1312 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1313 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1314 bool with_comp, u8 comp_type);
1315
1316 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1317 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1318 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1319 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
1320 void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1321
1322 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1323 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1324 u32 data_hi, u32 data_lo, int common);
1325 void bnx2x_update_coalesce(struct bnx2x *bp);
1326 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1327
1328 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1329 int wait)
1330 {
1331 u32 val;
1332
1333 do {
1334 val = REG_RD(bp, reg);
1335 if (val == expected)
1336 break;
1337 ms -= wait;
1338 msleep(wait);
1339
1340 } while (ms > 0);
1341
1342 return val;
1343 }
1344
1345 #define BNX2X_ILT_ZALLOC(x, y, size) \
1346 do { \
1347 x = pci_alloc_consistent(bp->pdev, size, y); \
1348 if (x) \
1349 memset(x, 0, size); \
1350 } while (0)
1351
1352 #define BNX2X_ILT_FREE(x, y, size) \
1353 do { \
1354 if (x) { \
1355 pci_free_consistent(bp->pdev, size, x, y); \
1356 x = NULL; \
1357 y = 0; \
1358 } \
1359 } while (0)
1360
1361 #define ILOG2(x) (ilog2((x)))
1362
1363 #define ILT_NUM_PAGE_ENTRIES (3072)
1364 /* In 57710/11 we use whole table since we have 8 func
1365 * In 57712 we have only 4 func, but use same size per func, then only half of
1366 * the table in use
1367 */
1368 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1369
1370 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1371 /*
1372 * the phys address is shifted right 12 bits and has an added
1373 * 1=valid bit added to the 53rd bit
1374 * then since this is a wide register(TM)
1375 * we split it into two 32 bit writes
1376 */
1377 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1378 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1379
1380 /* load/unload mode */
1381 #define LOAD_NORMAL 0
1382 #define LOAD_OPEN 1
1383 #define LOAD_DIAG 2
1384 #define UNLOAD_NORMAL 0
1385 #define UNLOAD_CLOSE 1
1386 #define UNLOAD_RECOVERY 2
1387
1388
1389 /* DMAE command defines */
1390 #define DMAE_TIMEOUT -1
1391 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1392 #define DMAE_NOT_RDY -3
1393 #define DMAE_PCI_ERR_FLAG 0x80000000
1394
1395 #define DMAE_SRC_PCI 0
1396 #define DMAE_SRC_GRC 1
1397
1398 #define DMAE_DST_NONE 0
1399 #define DMAE_DST_PCI 1
1400 #define DMAE_DST_GRC 2
1401
1402 #define DMAE_COMP_PCI 0
1403 #define DMAE_COMP_GRC 1
1404
1405 /* E2 and onward - PCI error handling in the completion */
1406
1407 #define DMAE_COMP_REGULAR 0
1408 #define DMAE_COM_SET_ERR 1
1409
1410 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1411 DMAE_COMMAND_SRC_SHIFT)
1412 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1413 DMAE_COMMAND_SRC_SHIFT)
1414
1415 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1416 DMAE_COMMAND_DST_SHIFT)
1417 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1418 DMAE_COMMAND_DST_SHIFT)
1419
1420 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1421 DMAE_COMMAND_C_DST_SHIFT)
1422 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1423 DMAE_COMMAND_C_DST_SHIFT)
1424
1425 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1426
1427 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1428 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1429 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1430 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1431
1432 #define DMAE_CMD_PORT_0 0
1433 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1434
1435 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1436 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1437 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1438
1439 #define DMAE_SRC_PF 0
1440 #define DMAE_SRC_VF 1
1441
1442 #define DMAE_DST_PF 0
1443 #define DMAE_DST_VF 1
1444
1445 #define DMAE_C_SRC 0
1446 #define DMAE_C_DST 1
1447
1448 #define DMAE_LEN32_RD_MAX 0x80
1449 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1450
1451 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1452 indicates eror */
1453
1454 #define MAX_DMAE_C_PER_PORT 8
1455 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1456 BP_E1HVN(bp))
1457 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1458 E1HVN_MAX)
1459
1460 /* PCIE link and speed */
1461 #define PCICFG_LINK_WIDTH 0x1f00000
1462 #define PCICFG_LINK_WIDTH_SHIFT 20
1463 #define PCICFG_LINK_SPEED 0xf0000
1464 #define PCICFG_LINK_SPEED_SHIFT 16
1465
1466
1467 #define BNX2X_NUM_TESTS 7
1468
1469 #define BNX2X_PHY_LOOPBACK 0
1470 #define BNX2X_MAC_LOOPBACK 1
1471 #define BNX2X_PHY_LOOPBACK_FAILED 1
1472 #define BNX2X_MAC_LOOPBACK_FAILED 2
1473 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1474 BNX2X_PHY_LOOPBACK_FAILED)
1475
1476
1477 #define STROM_ASSERT_ARRAY_SIZE 50
1478
1479
1480 /* must be used on a CID before placing it on a HW ring */
1481 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1482 (BP_E1HVN(bp) << 17) | (x))
1483
1484 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1485 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1486
1487
1488 #define BNX2X_BTR 4
1489 #define MAX_SPQ_PENDING 8
1490
1491
1492 /* CMNG constants
1493 derived from lab experiments, and not from system spec calculations !!! */
1494 #define DEF_MIN_RATE 100
1495 /* resolution of the rate shaping timer - 100 usec */
1496 #define RS_PERIODIC_TIMEOUT_USEC 100
1497 /* resolution of fairness algorithm in usecs -
1498 coefficient for calculating the actual t fair */
1499 #define T_FAIR_COEF 10000000
1500 /* number of bytes in single QM arbitration cycle -
1501 coefficient for calculating the fairness timer */
1502 #define QM_ARB_BYTES 40000
1503 #define FAIR_MEM 2
1504
1505
1506 #define ATTN_NIG_FOR_FUNC (1L << 8)
1507 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1508 #define GPIO_2_FUNC (1L << 10)
1509 #define GPIO_3_FUNC (1L << 11)
1510 #define GPIO_4_FUNC (1L << 12)
1511 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1512 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1513 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1514 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1515 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1516 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1517
1518 #define ATTN_HARD_WIRED_MASK 0xff00
1519 #define ATTENTION_ID 4
1520
1521
1522 /* stuff added to make the code fit 80Col */
1523
1524 #define BNX2X_PMF_LINK_ASSERT \
1525 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1526
1527 #define BNX2X_MC_ASSERT_BITS \
1528 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1529 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1530 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1531 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1532
1533 #define BNX2X_MCP_ASSERT \
1534 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1535
1536 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1537 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1538 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1539 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1540 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1541 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1542 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1543
1544 #define HW_INTERRUT_ASSERT_SET_0 \
1545 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1546 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1547 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1548 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1549 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1550 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1551 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1552 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1553 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1554 #define HW_INTERRUT_ASSERT_SET_1 \
1555 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1556 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1557 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1558 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1559 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1560 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1561 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1562 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1563 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1564 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1565 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1566 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1567 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1568 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1569 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1570 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1571 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1572 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1573 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1574 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1575 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1576 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1577 #define HW_INTERRUT_ASSERT_SET_2 \
1578 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1579 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1580 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1581 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1582 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1583 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1584 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1585 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1586 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1587 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1588 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1589 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1590
1591 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1592 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1593 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1594 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1595
1596 #define RSS_FLAGS(bp) \
1597 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1598 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1599 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1600 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1601 (bp->multi_mode << \
1602 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1603 #define MULTI_MASK 0x7f
1604
1605 #define BNX2X_SP_DSB_INDEX \
1606 (&bp->def_status_blk->sp_sb.\
1607 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1608
1609 #define SET_FLAG(value, mask, flag) \
1610 do {\
1611 (value) &= ~(mask);\
1612 (value) |= ((flag) << (mask##_SHIFT));\
1613 } while (0)
1614
1615 #define GET_FLAG(value, mask) \
1616 (((value) &= (mask)) >> (mask##_SHIFT))
1617
1618 #define GET_FIELD(value, fname) \
1619 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
1620
1621 #define CAM_IS_INVALID(x) \
1622 (GET_FLAG(x.flags, \
1623 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1624 (T_ETH_MAC_COMMAND_INVALIDATE))
1625
1626 #define CAM_INVALIDATE(x) \
1627 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1628
1629
1630 /* Number of u32 elements in MC hash array */
1631 #define MC_HASH_SIZE 8
1632 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1633 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1634
1635
1636 #ifndef PXP2_REG_PXP2_INT_STS
1637 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1638 #endif
1639
1640 #ifndef ETH_MAX_RX_CLIENTS_E2
1641 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
1642 #endif
1643
1644 #define BNX2X_VPD_LEN 128
1645 #define VENDOR_ID_LEN 4
1646
1647 /* Congestion management fairness mode */
1648 #define CMNG_FNS_NONE 0
1649 #define CMNG_FNS_MINMAX 1
1650
1651 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1652 #define HC_SEG_ACCESS_ATTN 4
1653 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1654
1655 #ifdef BNX2X_MAIN
1656 #define BNX2X_EXTERN
1657 #else
1658 #define BNX2X_EXTERN extern
1659 #endif
1660
1661 BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */
1662
1663 extern void bnx2x_set_ethtool_ops(struct net_device *netdev);
1664
1665 #endif /* bnx2x.h */
(deprecated) Btrfs devel tree