?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
blob2aef5cd3acf578197c1530454c37a345e1efee3f
1 /*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include "drmP.h"
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
30
31 #include <linux/io-mapping.h>
32
33 /* these defines are made up */
34 #define NV_CIO_CRE_44_HEADA 0x0
35 #define NV_CIO_CRE_44_HEADB 0x3
36 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37 #define LEGACY_I2C_CRT 0x80
38 #define LEGACY_I2C_PANEL 0x81
39 #define LEGACY_I2C_TV 0x82
40
41 #define EDID1_LEN 128
42
43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44 #define LOG_OLD_VALUE(x)
45
46 struct init_exec {
47 bool execute;
48 bool repeat;
49 };
50
51 static bool nv_cksum(const uint8_t *data, unsigned int length)
52 {
53 /*
54 * There's a few checksums in the BIOS, so here's a generic checking
55 * function.
56 */
57 int i;
58 uint8_t sum = 0;
59
60 for (i = 0; i < length; i++)
61 sum += data[i];
62
63 if (sum)
64 return true;
65
66 return false;
67 }
68
69 static int
70 score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
71 {
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
74 return 0;
75 }
76
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
81 } else
82 NV_TRACE(dev, "... appears to be valid\n");
83
84 return 3;
85 }
86
87 static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
88 {
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
91 int pcir_ptr;
92 int i;
93
94 if (dev_priv->card_type >= NV_50)
95 pci_nv_20 = 0x88050;
96 else
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
98
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
103
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
107 goto out;
108
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
116 goto out;
117
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
121 */
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
124
125 out:
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
129 }
130
131 static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
132 {
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
135 int i;
136
137 if (dev_priv->card_type >= NV_50) {
138 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
139
140 if (!vbios_vram)
141 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
142
143 old_bar0_pramin = nv_rd32(dev, 0x1700);
144 nv_wr32(dev, 0x1700, vbios_vram >> 16);
145 }
146
147 /* bail if no rom signature */
148 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
149 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
150 goto out;
151
152 for (i = 0; i < NV_PROM_SIZE; i++)
153 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
154
155 out:
156 if (dev_priv->card_type >= NV_50)
157 nv_wr32(dev, 0x1700, old_bar0_pramin);
158 }
159
160 static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
161 {
162 void __iomem *rom = NULL;
163 size_t rom_len;
164 int ret;
165
166 ret = pci_enable_rom(dev->pdev);
167 if (ret)
168 return;
169
170 rom = pci_map_rom(dev->pdev, &rom_len);
171 if (!rom)
172 goto out;
173 memcpy_fromio(data, rom, rom_len);
174 pci_unmap_rom(dev->pdev, rom);
175
176 out:
177 pci_disable_rom(dev->pdev);
178 }
179
180 static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
181 {
182 int i;
183 int ret;
184 int size = 64 * 1024;
185
186 if (!nouveau_acpi_rom_supported(dev->pdev))
187 return;
188
189 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
190 ret = nouveau_acpi_get_bios_chunk(data,
191 (i * ROM_BIOS_PAGE),
192 ROM_BIOS_PAGE);
193 if (ret <= 0)
194 break;
195 }
196 return;
197 }
198
199 struct methods {
200 const char desc[8];
201 void (*loadbios)(struct drm_device *, uint8_t *);
202 const bool rw;
203 };
204
205 static struct methods shadow_methods[] = {
206 { "PRAMIN", load_vbios_pramin, true },
207 { "PROM", load_vbios_prom, false },
208 { "PCIROM", load_vbios_pci, true },
209 { "ACPI", load_vbios_acpi, true },
210 };
211 #define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
212
213 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
214 {
215 struct methods *methods = shadow_methods;
216 int testscore = 3;
217 int scores[NUM_SHADOW_METHODS], i;
218
219 if (nouveau_vbios) {
220 for (i = 0; i < NUM_SHADOW_METHODS; i++)
221 if (!strcasecmp(nouveau_vbios, methods[i].desc))
222 break;
223
224 if (i < NUM_SHADOW_METHODS) {
225 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
226 methods[i].desc);
227
228 methods[i].loadbios(dev, data);
229 if (score_vbios(dev, data, methods[i].rw))
230 return true;
231 }
232
233 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
234 }
235
236 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
237 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
238 methods[i].desc);
239 data[0] = data[1] = 0; /* avoid reuse of previous image */
240 methods[i].loadbios(dev, data);
241 scores[i] = score_vbios(dev, data, methods[i].rw);
242 if (scores[i] == testscore)
243 return true;
244 }
245
246 while (--testscore > 0) {
247 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
248 if (scores[i] == testscore) {
249 NV_TRACE(dev, "Using BIOS image from %s\n",
250 methods[i].desc);
251 methods[i].loadbios(dev, data);
252 return true;
253 }
254 }
255 }
256
257 NV_ERROR(dev, "No valid BIOS image found\n");
258 return false;
259 }
260
261 struct init_tbl_entry {
262 char *name;
263 uint8_t id;
264 /* Return:
265 * > 0: success, length of opcode
266 * 0: success, but abort further parsing of table (INIT_DONE etc)
267 * < 0: failure, table parsing will be aborted
268 */
269 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
270 };
271
272 static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
273
274 #define MACRO_INDEX_SIZE 2
275 #define MACRO_SIZE 8
276 #define CONDITION_SIZE 12
277 #define IO_FLAG_CONDITION_SIZE 9
278 #define IO_CONDITION_SIZE 5
279 #define MEM_INIT_SIZE 66
280
281 static void still_alive(void)
282 {
283 #if 0
284 sync();
285 msleep(2);
286 #endif
287 }
288
289 static uint32_t
290 munge_reg(struct nvbios *bios, uint32_t reg)
291 {
292 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
293 struct dcb_entry *dcbent = bios->display.output;
294
295 if (dev_priv->card_type < NV_50)
296 return reg;
297
298 if (reg & 0x40000000) {
299 BUG_ON(!dcbent);
300
301 reg += (ffs(dcbent->or) - 1) * 0x800;
302 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
303 reg += 0x00000080;
304 }
305
306 reg &= ~0x60000000;
307 return reg;
308 }
309
310 static int
311 valid_reg(struct nvbios *bios, uint32_t reg)
312 {
313 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
314 struct drm_device *dev = bios->dev;
315
316 /* C51 has misaligned regs on purpose. Marvellous */
317 if (reg & 0x2 ||
318 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
319 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
320
321 /* warn on C51 regs that haven't been verified accessible in tracing */
322 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
323 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
324 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
325 reg);
326
327 if (reg >= (8*1024*1024)) {
328 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
329 return 0;
330 }
331
332 return 1;
333 }
334
335 static bool
336 valid_idx_port(struct nvbios *bios, uint16_t port)
337 {
338 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
339 struct drm_device *dev = bios->dev;
340
341 /*
342 * If adding more ports here, the read/write functions below will need
343 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
344 * used for the port in question
345 */
346 if (dev_priv->card_type < NV_50) {
347 if (port == NV_CIO_CRX__COLOR)
348 return true;
349 if (port == NV_VIO_SRX)
350 return true;
351 } else {
352 if (port == NV_CIO_CRX__COLOR)
353 return true;
354 }
355
356 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
357 port);
358
359 return false;
360 }
361
362 static bool
363 valid_port(struct nvbios *bios, uint16_t port)
364 {
365 struct drm_device *dev = bios->dev;
366
367 /*
368 * If adding more ports here, the read/write functions below will need
369 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
370 * used for the port in question
371 */
372 if (port == NV_VIO_VSE2)
373 return true;
374
375 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
376
377 return false;
378 }
379
380 static uint32_t
381 bios_rd32(struct nvbios *bios, uint32_t reg)
382 {
383 uint32_t data;
384
385 reg = munge_reg(bios, reg);
386 if (!valid_reg(bios, reg))
387 return 0;
388
389 /*
390 * C51 sometimes uses regs with bit0 set in the address. For these
391 * cases there should exist a translation in a BIOS table to an IO
392 * port address which the BIOS uses for accessing the reg
393 *
394 * These only seem to appear for the power control regs to a flat panel,
395 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
396 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
397 * suspend-resume mmio trace from a C51 will be required to see if this
398 * is true for the power microcode in 0x14.., or whether the direct IO
399 * port access method is needed
400 */
401 if (reg & 0x1)
402 reg &= ~0x1;
403
404 data = nv_rd32(bios->dev, reg);
405
406 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
407
408 return data;
409 }
410
411 static void
412 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
413 {
414 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
415
416 reg = munge_reg(bios, reg);
417 if (!valid_reg(bios, reg))
418 return;
419
420 /* see note in bios_rd32 */
421 if (reg & 0x1)
422 reg &= 0xfffffffe;
423
424 LOG_OLD_VALUE(bios_rd32(bios, reg));
425 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
426
427 if (dev_priv->vbios.execute) {
428 still_alive();
429 nv_wr32(bios->dev, reg, data);
430 }
431 }
432
433 static uint8_t
434 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
435 {
436 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
437 struct drm_device *dev = bios->dev;
438 uint8_t data;
439
440 if (!valid_idx_port(bios, port))
441 return 0;
442
443 if (dev_priv->card_type < NV_50) {
444 if (port == NV_VIO_SRX)
445 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
446 else /* assume NV_CIO_CRX__COLOR */
447 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
448 } else {
449 uint32_t data32;
450
451 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
452 data = (data32 >> ((index & 3) << 3)) & 0xff;
453 }
454
455 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
456 "Head: 0x%02X, Data: 0x%02X\n",
457 port, index, bios->state.crtchead, data);
458 return data;
459 }
460
461 static void
462 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
463 {
464 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
465 struct drm_device *dev = bios->dev;
466
467 if (!valid_idx_port(bios, port))
468 return;
469
470 /*
471 * The current head is maintained in the nvbios member state.crtchead.
472 * We trap changes to CR44 and update the head variable and hence the
473 * register set written.
474 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
475 * of the write, and to head1 after the write
476 */
477 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
478 data != NV_CIO_CRE_44_HEADB)
479 bios->state.crtchead = 0;
480
481 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
482 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
483 "Head: 0x%02X, Data: 0x%02X\n",
484 port, index, bios->state.crtchead, data);
485
486 if (bios->execute && dev_priv->card_type < NV_50) {
487 still_alive();
488 if (port == NV_VIO_SRX)
489 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
490 else /* assume NV_CIO_CRX__COLOR */
491 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
492 } else
493 if (bios->execute) {
494 uint32_t data32, shift = (index & 3) << 3;
495
496 still_alive();
497
498 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
499 data32 &= ~(0xff << shift);
500 data32 |= (data << shift);
501 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
502 }
503
504 if (port == NV_CIO_CRX__COLOR &&
505 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
506 bios->state.crtchead = 1;
507 }
508
509 static uint8_t
510 bios_port_rd(struct nvbios *bios, uint16_t port)
511 {
512 uint8_t data, head = bios->state.crtchead;
513
514 if (!valid_port(bios, port))
515 return 0;
516
517 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
518
519 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
520 port, head, data);
521
522 return data;
523 }
524
525 static void
526 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
527 {
528 int head = bios->state.crtchead;
529
530 if (!valid_port(bios, port))
531 return;
532
533 LOG_OLD_VALUE(bios_port_rd(bios, port));
534 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
535 port, head, data);
536
537 if (!bios->execute)
538 return;
539
540 still_alive();
541 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
542 }
543
544 static bool
545 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
546 {
547 /*
548 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
549 * for the CRTC index; 1 byte for the mask to apply to the value
550 * retrieved from the CRTC; 1 byte for the shift right to apply to the
551 * masked CRTC value; 2 bytes for the offset to the flag array, to
552 * which the shifted value is added; 1 byte for the mask applied to the
553 * value read from the flag array; and 1 byte for the value to compare
554 * against the masked byte from the flag table.
555 */
556
557 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
558 uint16_t crtcport = ROM16(bios->data[condptr]);
559 uint8_t crtcindex = bios->data[condptr + 2];
560 uint8_t mask = bios->data[condptr + 3];
561 uint8_t shift = bios->data[condptr + 4];
562 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
563 uint8_t flagarraymask = bios->data[condptr + 7];
564 uint8_t cmpval = bios->data[condptr + 8];
565 uint8_t data;
566
567 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
568 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
569 "Cmpval: 0x%02X\n",
570 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
571
572 data = bios_idxprt_rd(bios, crtcport, crtcindex);
573
574 data = bios->data[flagarray + ((data & mask) >> shift)];
575 data &= flagarraymask;
576
577 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
578 offset, data, cmpval);
579
580 return (data == cmpval);
581 }
582
583 static bool
584 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
585 {
586 /*
587 * The condition table entry has 4 bytes for the address of the
588 * register to check, 4 bytes for a mask to apply to the register and
589 * 4 for a test comparison value
590 */
591
592 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
593 uint32_t reg = ROM32(bios->data[condptr]);
594 uint32_t mask = ROM32(bios->data[condptr + 4]);
595 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
596 uint32_t data;
597
598 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
599 offset, cond, reg, mask);
600
601 data = bios_rd32(bios, reg) & mask;
602
603 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
604 offset, data, cmpval);
605
606 return (data == cmpval);
607 }
608
609 static bool
610 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
611 {
612 /*
613 * The IO condition entry has 2 bytes for the IO port address; 1 byte
614 * for the index to write to io_port; 1 byte for the mask to apply to
615 * the byte read from io_port+1; and 1 byte for the value to compare
616 * against the masked byte.
617 */
618
619 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
620 uint16_t io_port = ROM16(bios->data[condptr]);
621 uint8_t port_index = bios->data[condptr + 2];
622 uint8_t mask = bios->data[condptr + 3];
623 uint8_t cmpval = bios->data[condptr + 4];
624
625 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
626
627 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
628 offset, data, cmpval);
629
630 return (data == cmpval);
631 }
632
633 static int
634 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
635 {
636 struct drm_nouveau_private *dev_priv = dev->dev_private;
637 uint32_t reg0 = nv_rd32(dev, reg + 0);
638 uint32_t reg1 = nv_rd32(dev, reg + 4);
639 struct nouveau_pll_vals pll;
640 struct pll_lims pll_limits;
641 int ret;
642
643 ret = get_pll_limits(dev, reg, &pll_limits);
644 if (ret)
645 return ret;
646
647 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
648 if (!clk)
649 return -ERANGE;
650
651 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
652 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
653
654 if (dev_priv->vbios.execute) {
655 still_alive();
656 nv_wr32(dev, reg + 4, reg1);
657 nv_wr32(dev, reg + 0, reg0);
658 }
659
660 return 0;
661 }
662
663 static int
664 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
665 {
666 struct drm_device *dev = bios->dev;
667 struct drm_nouveau_private *dev_priv = dev->dev_private;
668 /* clk in kHz */
669 struct pll_lims pll_lim;
670 struct nouveau_pll_vals pllvals;
671 int ret;
672
673 if (dev_priv->card_type >= NV_50)
674 return nv50_pll_set(dev, reg, clk);
675
676 /* high regs (such as in the mac g5 table) are not -= 4 */
677 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
678 if (ret)
679 return ret;
680
681 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
682 if (!clk)
683 return -ERANGE;
684
685 if (bios->execute) {
686 still_alive();
687 nouveau_hw_setpll(dev, reg, &pllvals);
688 }
689
690 return 0;
691 }
692
693 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
694 {
695 struct drm_nouveau_private *dev_priv = dev->dev_private;
696 struct nvbios *bios = &dev_priv->vbios;
697
698 /*
699 * For the results of this function to be correct, CR44 must have been
700 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
701 * and the DCB table parsed, before the script calling the function is
702 * run. run_digital_op_script is example of how to do such setup
703 */
704
705 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
706
707 if (dcb_entry > bios->dcb.entries) {
708 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
709 "(%02X)\n", dcb_entry);
710 dcb_entry = 0x7f; /* unused / invalid marker */
711 }
712
713 return dcb_entry;
714 }
715
716 static int
717 read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
718 {
719 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
720 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
721 int recordoffset = 0, rdofs = 1, wrofs = 0;
722 uint8_t port_type = 0;
723
724 if (!i2ctable)
725 return -EINVAL;
726
727 if (dcb_version >= 0x30) {
728 if (i2ctable[0] != dcb_version) /* necessary? */
729 NV_WARN(dev,
730 "DCB I2C table version mismatch (%02X vs %02X)\n",
731 i2ctable[0], dcb_version);
732 dcb_i2c_ver = i2ctable[0];
733 headerlen = i2ctable[1];
734 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
735 i2c_entries = i2ctable[2];
736 else
737 NV_WARN(dev,
738 "DCB I2C table has more entries than indexable "
739 "(%d entries, max %d)\n", i2ctable[2],
740 DCB_MAX_NUM_I2C_ENTRIES);
741 entry_len = i2ctable[3];
742 /* [4] is i2c_default_indices, read in parse_dcb_table() */
743 }
744 /*
745 * It's your own fault if you call this function on a DCB 1.1 BIOS --
746 * the test below is for DCB 1.2
747 */
748 if (dcb_version < 0x14) {
749 recordoffset = 2;
750 rdofs = 0;
751 wrofs = 1;
752 }
753
754 if (index == 0xf)
755 return 0;
756 if (index >= i2c_entries) {
757 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
758 index, i2ctable[2]);
759 return -ENOENT;
760 }
761 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
762 NV_ERROR(dev, "DCB I2C entry invalid\n");
763 return -EINVAL;
764 }
765
766 if (dcb_i2c_ver >= 0x30) {
767 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
768
769 /*
770 * Fixup for chips using same address offset for read and
771 * write.
772 */
773 if (port_type == 4) /* seen on C51 */
774 rdofs = wrofs = 1;
775 if (port_type >= 5) /* G80+ */
776 rdofs = wrofs = 0;
777 }
778
779 if (dcb_i2c_ver >= 0x40) {
780 if (port_type != 5 && port_type != 6)
781 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
782
783 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
784 }
785
786 i2c->port_type = port_type;
787 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
788 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
789
790 return 0;
791 }
792
793 static struct nouveau_i2c_chan *
794 init_i2c_device_find(struct drm_device *dev, int i2c_index)
795 {
796 struct drm_nouveau_private *dev_priv = dev->dev_private;
797 struct dcb_table *dcb = &dev_priv->vbios.dcb;
798
799 if (i2c_index == 0xff) {
800 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
801 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
802 int default_indices = dcb->i2c_default_indices;
803
804 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
805 shift = 4;
806
807 i2c_index = (default_indices >> shift) & 0xf;
808 }
809 if (i2c_index == 0x80) /* g80+ */
810 i2c_index = dcb->i2c_default_indices & 0xf;
811 else
812 if (i2c_index == 0x81)
813 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
814
815 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
816 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
817 return NULL;
818 }
819
820 /* Make sure i2c table entry has been parsed, it may not
821 * have been if this is a bus not referenced by a DCB encoder
822 */
823 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
824 i2c_index, &dcb->i2c[i2c_index]);
825
826 return nouveau_i2c_find(dev, i2c_index);
827 }
828
829 static uint32_t
830 get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
831 {
832 /*
833 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
834 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
835 * CR58 for CR57 = 0 to index a table of offsets to the basic
836 * 0x6808b0 address.
837 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
838 * CR58 for CR57 = 0 to index a table of offsets to the basic
839 * 0x6808b0 address, and then flip the offset by 8.
840 */
841
842 struct drm_nouveau_private *dev_priv = dev->dev_private;
843 struct nvbios *bios = &dev_priv->vbios;
844 const int pramdac_offset[13] = {
845 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
846 const uint32_t pramdac_table[4] = {
847 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
848
849 if (mlv >= 0x80) {
850 int dcb_entry, dacoffset;
851
852 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
853 dcb_entry = dcb_entry_idx_from_crtchead(dev);
854 if (dcb_entry == 0x7f)
855 return 0;
856 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
857 if (mlv == 0x81)
858 dacoffset ^= 8;
859 return 0x6808b0 + dacoffset;
860 } else {
861 if (mlv >= ARRAY_SIZE(pramdac_table)) {
862 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
863 mlv);
864 return 0;
865 }
866 return pramdac_table[mlv];
867 }
868 }
869
870 static int
871 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
872 struct init_exec *iexec)
873 {
874 /*
875 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
876 *
877 * offset (8 bit): opcode
878 * offset + 1 (16 bit): CRTC port
879 * offset + 3 (8 bit): CRTC index
880 * offset + 4 (8 bit): mask
881 * offset + 5 (8 bit): shift
882 * offset + 6 (8 bit): count
883 * offset + 7 (32 bit): register
884 * offset + 11 (32 bit): configuration 1
885 * ...
886 *
887 * Starting at offset + 11 there are "count" 32 bit values.
888 * To find out which value to use read index "CRTC index" on "CRTC
889 * port", AND this value with "mask" and then bit shift right "shift"
890 * bits. Read the appropriate value using this index and write to
891 * "register"
892 */
893
894 uint16_t crtcport = ROM16(bios->data[offset + 1]);
895 uint8_t crtcindex = bios->data[offset + 3];
896 uint8_t mask = bios->data[offset + 4];
897 uint8_t shift = bios->data[offset + 5];
898 uint8_t count = bios->data[offset + 6];
899 uint32_t reg = ROM32(bios->data[offset + 7]);
900 uint8_t config;
901 uint32_t configval;
902 int len = 11 + count * 4;
903
904 if (!iexec->execute)
905 return len;
906
907 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
908 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
909 offset, crtcport, crtcindex, mask, shift, count, reg);
910
911 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
912 if (config > count) {
913 NV_ERROR(bios->dev,
914 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
915 offset, config, count);
916 return len;
917 }
918
919 configval = ROM32(bios->data[offset + 11 + config * 4]);
920
921 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
922
923 bios_wr32(bios, reg, configval);
924
925 return len;
926 }
927
928 static int
929 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
930 {
931 /*
932 * INIT_REPEAT opcode: 0x33 ('3')
933 *
934 * offset (8 bit): opcode
935 * offset + 1 (8 bit): count
936 *
937 * Execute script following this opcode up to INIT_REPEAT_END
938 * "count" times
939 */
940
941 uint8_t count = bios->data[offset + 1];
942 uint8_t i;
943
944 /* no iexec->execute check by design */
945
946 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
947 offset, count);
948
949 iexec->repeat = true;
950
951 /*
952 * count - 1, as the script block will execute once when we leave this
953 * opcode -- this is compatible with bios behaviour as:
954 * a) the block is always executed at least once, even if count == 0
955 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
956 * while we don't
957 */
958 for (i = 0; i < count - 1; i++)
959 parse_init_table(bios, offset + 2, iexec);
960
961 iexec->repeat = false;
962
963 return 2;
964 }
965
966 static int
967 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
968 struct init_exec *iexec)
969 {
970 /*
971 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
972 *
973 * offset (8 bit): opcode
974 * offset + 1 (16 bit): CRTC port
975 * offset + 3 (8 bit): CRTC index
976 * offset + 4 (8 bit): mask
977 * offset + 5 (8 bit): shift
978 * offset + 6 (8 bit): IO flag condition index
979 * offset + 7 (8 bit): count
980 * offset + 8 (32 bit): register
981 * offset + 12 (16 bit): frequency 1
982 * ...
983 *
984 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
985 * Set PLL register "register" to coefficients for frequency n,
986 * selected by reading index "CRTC index" of "CRTC port" ANDed with
987 * "mask" and shifted right by "shift".
988 *
989 * If "IO flag condition index" > 0, and condition met, double
990 * frequency before setting it.
991 */
992
993 uint16_t crtcport = ROM16(bios->data[offset + 1]);
994 uint8_t crtcindex = bios->data[offset + 3];
995 uint8_t mask = bios->data[offset + 4];
996 uint8_t shift = bios->data[offset + 5];
997 int8_t io_flag_condition_idx = bios->data[offset + 6];
998 uint8_t count = bios->data[offset + 7];
999 uint32_t reg = ROM32(bios->data[offset + 8]);
1000 uint8_t config;
1001 uint16_t freq;
1002 int len = 12 + count * 2;
1003
1004 if (!iexec->execute)
1005 return len;
1006
1007 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1008 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1009 "Count: 0x%02X, Reg: 0x%08X\n",
1010 offset, crtcport, crtcindex, mask, shift,
1011 io_flag_condition_idx, count, reg);
1012
1013 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1014 if (config > count) {
1015 NV_ERROR(bios->dev,
1016 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1017 offset, config, count);
1018 return len;
1019 }
1020
1021 freq = ROM16(bios->data[offset + 12 + config * 2]);
1022
1023 if (io_flag_condition_idx > 0) {
1024 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1025 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1026 "frequency doubled\n", offset);
1027 freq *= 2;
1028 } else
1029 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1030 "frequency unchanged\n", offset);
1031 }
1032
1033 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1034 offset, reg, config, freq);
1035
1036 setPLL(bios, reg, freq * 10);
1037
1038 return len;
1039 }
1040
1041 static int
1042 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1043 {
1044 /*
1045 * INIT_END_REPEAT opcode: 0x36 ('6')
1046 *
1047 * offset (8 bit): opcode
1048 *
1049 * Marks the end of the block for INIT_REPEAT to repeat
1050 */
1051
1052 /* no iexec->execute check by design */
1053
1054 /*
1055 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1056 * we're not in repeat mode
1057 */
1058 if (iexec->repeat)
1059 return 0;
1060
1061 return 1;
1062 }
1063
1064 static int
1065 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1066 {
1067 /*
1068 * INIT_COPY opcode: 0x37 ('7')
1069 *
1070 * offset (8 bit): opcode
1071 * offset + 1 (32 bit): register
1072 * offset + 5 (8 bit): shift
1073 * offset + 6 (8 bit): srcmask
1074 * offset + 7 (16 bit): CRTC port
1075 * offset + 9 (8 bit): CRTC index
1076 * offset + 10 (8 bit): mask
1077 *
1078 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1079 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1080 * port
1081 */
1082
1083 uint32_t reg = ROM32(bios->data[offset + 1]);
1084 uint8_t shift = bios->data[offset + 5];
1085 uint8_t srcmask = bios->data[offset + 6];
1086 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1087 uint8_t crtcindex = bios->data[offset + 9];
1088 uint8_t mask = bios->data[offset + 10];
1089 uint32_t data;
1090 uint8_t crtcdata;
1091
1092 if (!iexec->execute)
1093 return 11;
1094
1095 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1096 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1097 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1098
1099 data = bios_rd32(bios, reg);
1100
1101 if (shift < 0x80)
1102 data >>= shift;
1103 else
1104 data <<= (0x100 - shift);
1105
1106 data &= srcmask;
1107
1108 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1109 crtcdata |= (uint8_t)data;
1110 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1111
1112 return 11;
1113 }
1114
1115 static int
1116 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1117 {
1118 /*
1119 * INIT_NOT opcode: 0x38 ('8')
1120 *
1121 * offset (8 bit): opcode
1122 *
1123 * Invert the current execute / no-execute condition (i.e. "else")
1124 */
1125 if (iexec->execute)
1126 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1127 else
1128 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1129
1130 iexec->execute = !iexec->execute;
1131 return 1;
1132 }
1133
1134 static int
1135 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1136 struct init_exec *iexec)
1137 {
1138 /*
1139 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1140 *
1141 * offset (8 bit): opcode
1142 * offset + 1 (8 bit): condition number
1143 *
1144 * Check condition "condition number" in the IO flag condition table.
1145 * If condition not met skip subsequent opcodes until condition is
1146 * inverted (INIT_NOT), or we hit INIT_RESUME
1147 */
1148
1149 uint8_t cond = bios->data[offset + 1];
1150
1151 if (!iexec->execute)
1152 return 2;
1153
1154 if (io_flag_condition_met(bios, offset, cond))
1155 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1156 else {
1157 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1158 iexec->execute = false;
1159 }
1160
1161 return 2;
1162 }
1163
1164 static int
1165 init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1166 {
1167 /*
1168 * INIT_DP_CONDITION opcode: 0x3A ('')
1169 *
1170 * offset (8 bit): opcode
1171 * offset + 1 (8 bit): "sub" opcode
1172 * offset + 2 (8 bit): unknown
1173 *
1174 */
1175
1176 struct bit_displayport_encoder_table *dpe = NULL;
1177 struct dcb_entry *dcb = bios->display.output;
1178 struct drm_device *dev = bios->dev;
1179 uint8_t cond = bios->data[offset + 1];
1180 int dummy;
1181
1182 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1183
1184 if (!iexec->execute)
1185 return 3;
1186
1187 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1188 if (!dpe) {
1189 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
1190 return 3;
1191 }
1192
1193 switch (cond) {
1194 case 0:
1195 {
1196 struct dcb_connector_table_entry *ent =
1197 &bios->dcb.connector.entry[dcb->connector];
1198
1199 if (ent->type != DCB_CONNECTOR_eDP)
1200 iexec->execute = false;
1201 }
1202 break;
1203 case 1:
1204 case 2:
1205 if (!(dpe->unknown & cond))
1206 iexec->execute = false;
1207 break;
1208 case 5:
1209 {
1210 struct nouveau_i2c_chan *auxch;
1211 int ret;
1212
1213 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1214 if (!auxch) {
1215 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1216 return 3;
1217 }
1218
1219 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1220 if (ret) {
1221 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1222 return 3;
1223 }
1224
1225 if (!(cond & 1))
1226 iexec->execute = false;
1227 }
1228 break;
1229 default:
1230 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1231 break;
1232 }
1233
1234 if (iexec->execute)
1235 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1236 else
1237 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1238
1239 return 3;
1240 }
1241
1242 static int
1243 init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1244 {
1245 /*
1246 * INIT_3B opcode: 0x3B ('')
1247 *
1248 * offset (8 bit): opcode
1249 * offset + 1 (8 bit): crtc index
1250 *
1251 */
1252
1253 uint8_t or = ffs(bios->display.output->or) - 1;
1254 uint8_t index = bios->data[offset + 1];
1255 uint8_t data;
1256
1257 if (!iexec->execute)
1258 return 2;
1259
1260 data = bios_idxprt_rd(bios, 0x3d4, index);
1261 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1262 return 2;
1263 }
1264
1265 static int
1266 init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1267 {
1268 /*
1269 * INIT_3C opcode: 0x3C ('')
1270 *
1271 * offset (8 bit): opcode
1272 * offset + 1 (8 bit): crtc index
1273 *
1274 */
1275
1276 uint8_t or = ffs(bios->display.output->or) - 1;
1277 uint8_t index = bios->data[offset + 1];
1278 uint8_t data;
1279
1280 if (!iexec->execute)
1281 return 2;
1282
1283 data = bios_idxprt_rd(bios, 0x3d4, index);
1284 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1285 return 2;
1286 }
1287
1288 static int
1289 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1290 struct init_exec *iexec)
1291 {
1292 /*
1293 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1294 *
1295 * offset (8 bit): opcode
1296 * offset + 1 (32 bit): control register
1297 * offset + 5 (32 bit): data register
1298 * offset + 9 (32 bit): mask
1299 * offset + 13 (32 bit): data
1300 * offset + 17 (8 bit): count
1301 * offset + 18 (8 bit): address 1
1302 * offset + 19 (8 bit): data 1
1303 * ...
1304 *
1305 * For each of "count" address and data pairs, write "data n" to
1306 * "data register", read the current value of "control register",
1307 * and write it back once ANDed with "mask", ORed with "data",
1308 * and ORed with "address n"
1309 */
1310
1311 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1312 uint32_t datareg = ROM32(bios->data[offset + 5]);
1313 uint32_t mask = ROM32(bios->data[offset + 9]);
1314 uint32_t data = ROM32(bios->data[offset + 13]);
1315 uint8_t count = bios->data[offset + 17];
1316 int len = 18 + count * 2;
1317 uint32_t value;
1318 int i;
1319
1320 if (!iexec->execute)
1321 return len;
1322
1323 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1324 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1325 offset, controlreg, datareg, mask, data, count);
1326
1327 for (i = 0; i < count; i++) {
1328 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1329 uint8_t instdata = bios->data[offset + 19 + i * 2];
1330
1331 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1332 offset, instaddress, instdata);
1333
1334 bios_wr32(bios, datareg, instdata);
1335 value = bios_rd32(bios, controlreg) & mask;
1336 value |= data;
1337 value |= instaddress;
1338 bios_wr32(bios, controlreg, value);
1339 }
1340
1341 return len;
1342 }
1343
1344 static int
1345 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1346 struct init_exec *iexec)
1347 {
1348 /*
1349 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1350 *
1351 * offset (8 bit): opcode
1352 * offset + 1 (16 bit): CRTC port
1353 * offset + 3 (8 bit): CRTC index
1354 * offset + 4 (8 bit): mask
1355 * offset + 5 (8 bit): shift
1356 * offset + 6 (8 bit): count
1357 * offset + 7 (32 bit): register
1358 * offset + 11 (32 bit): frequency 1
1359 * ...
1360 *
1361 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1362 * Set PLL register "register" to coefficients for frequency n,
1363 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1364 * "mask" and shifted right by "shift".
1365 */
1366
1367 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1368 uint8_t crtcindex = bios->data[offset + 3];
1369 uint8_t mask = bios->data[offset + 4];
1370 uint8_t shift = bios->data[offset + 5];
1371 uint8_t count = bios->data[offset + 6];
1372 uint32_t reg = ROM32(bios->data[offset + 7]);
1373 int len = 11 + count * 4;
1374 uint8_t config;
1375 uint32_t freq;
1376
1377 if (!iexec->execute)
1378 return len;
1379
1380 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1381 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1382 offset, crtcport, crtcindex, mask, shift, count, reg);
1383
1384 if (!reg)
1385 return len;
1386
1387 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1388 if (config > count) {
1389 NV_ERROR(bios->dev,
1390 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1391 offset, config, count);
1392 return len;
1393 }
1394
1395 freq = ROM32(bios->data[offset + 11 + config * 4]);
1396
1397 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1398 offset, reg, config, freq);
1399
1400 setPLL(bios, reg, freq);
1401
1402 return len;
1403 }
1404
1405 static int
1406 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1407 {
1408 /*
1409 * INIT_PLL2 opcode: 0x4B ('K')
1410 *
1411 * offset (8 bit): opcode
1412 * offset + 1 (32 bit): register
1413 * offset + 5 (32 bit): freq
1414 *
1415 * Set PLL register "register" to coefficients for frequency "freq"
1416 */
1417
1418 uint32_t reg = ROM32(bios->data[offset + 1]);
1419 uint32_t freq = ROM32(bios->data[offset + 5]);
1420
1421 if (!iexec->execute)
1422 return 9;
1423
1424 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1425 offset, reg, freq);
1426
1427 setPLL(bios, reg, freq);
1428 return 9;
1429 }
1430
1431 static int
1432 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1433 {
1434 /*
1435 * INIT_I2C_BYTE opcode: 0x4C ('L')
1436 *
1437 * offset (8 bit): opcode
1438 * offset + 1 (8 bit): DCB I2C table entry index
1439 * offset + 2 (8 bit): I2C slave address
1440 * offset + 3 (8 bit): count
1441 * offset + 4 (8 bit): I2C register 1
1442 * offset + 5 (8 bit): mask 1
1443 * offset + 6 (8 bit): data 1
1444 * ...
1445 *
1446 * For each of "count" registers given by "I2C register n" on the device
1447 * addressed by "I2C slave address" on the I2C bus given by
1448 * "DCB I2C table entry index", read the register, AND the result with
1449 * "mask n" and OR it with "data n" before writing it back to the device
1450 */
1451
1452 struct drm_device *dev = bios->dev;
1453 uint8_t i2c_index = bios->data[offset + 1];
1454 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1455 uint8_t count = bios->data[offset + 3];
1456 struct nouveau_i2c_chan *chan;
1457 int len = 4 + count * 3;
1458 int ret, i;
1459
1460 if (!iexec->execute)
1461 return len;
1462
1463 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1464 "Count: 0x%02X\n",
1465 offset, i2c_index, i2c_address, count);
1466
1467 chan = init_i2c_device_find(dev, i2c_index);
1468 if (!chan) {
1469 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1470 return len;
1471 }
1472
1473 for (i = 0; i < count; i++) {
1474 uint8_t reg = bios->data[offset + 4 + i * 3];
1475 uint8_t mask = bios->data[offset + 5 + i * 3];
1476 uint8_t data = bios->data[offset + 6 + i * 3];
1477 union i2c_smbus_data val;
1478
1479 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1480 I2C_SMBUS_READ, reg,
1481 I2C_SMBUS_BYTE_DATA, &val);
1482 if (ret < 0) {
1483 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1484 return len;
1485 }
1486
1487 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1488 "Mask: 0x%02X, Data: 0x%02X\n",
1489 offset, reg, val.byte, mask, data);
1490
1491 if (!bios->execute)
1492 continue;
1493
1494 val.byte &= mask;
1495 val.byte |= data;
1496 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1497 I2C_SMBUS_WRITE, reg,
1498 I2C_SMBUS_BYTE_DATA, &val);
1499 if (ret < 0) {
1500 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1501 return len;
1502 }
1503 }
1504
1505 return len;
1506 }
1507
1508 static int
1509 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1510 {
1511 /*
1512 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1513 *
1514 * offset (8 bit): opcode
1515 * offset + 1 (8 bit): DCB I2C table entry index
1516 * offset + 2 (8 bit): I2C slave address
1517 * offset + 3 (8 bit): count
1518 * offset + 4 (8 bit): I2C register 1
1519 * offset + 5 (8 bit): data 1
1520 * ...
1521 *
1522 * For each of "count" registers given by "I2C register n" on the device
1523 * addressed by "I2C slave address" on the I2C bus given by
1524 * "DCB I2C table entry index", set the register to "data n"
1525 */
1526
1527 struct drm_device *dev = bios->dev;
1528 uint8_t i2c_index = bios->data[offset + 1];
1529 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1530 uint8_t count = bios->data[offset + 3];
1531 struct nouveau_i2c_chan *chan;
1532 int len = 4 + count * 2;
1533 int ret, i;
1534
1535 if (!iexec->execute)
1536 return len;
1537
1538 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1539 "Count: 0x%02X\n",
1540 offset, i2c_index, i2c_address, count);
1541
1542 chan = init_i2c_device_find(dev, i2c_index);
1543 if (!chan) {
1544 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1545 return len;
1546 }
1547
1548 for (i = 0; i < count; i++) {
1549 uint8_t reg = bios->data[offset + 4 + i * 2];
1550 union i2c_smbus_data val;
1551
1552 val.byte = bios->data[offset + 5 + i * 2];
1553
1554 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1555 offset, reg, val.byte);
1556
1557 if (!bios->execute)
1558 continue;
1559
1560 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1561 I2C_SMBUS_WRITE, reg,
1562 I2C_SMBUS_BYTE_DATA, &val);
1563 if (ret < 0) {
1564 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1565 return len;
1566 }
1567 }
1568
1569 return len;
1570 }
1571
1572 static int
1573 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1574 {
1575 /*
1576 * INIT_ZM_I2C opcode: 0x4E ('N')
1577 *
1578 * offset (8 bit): opcode
1579 * offset + 1 (8 bit): DCB I2C table entry index
1580 * offset + 2 (8 bit): I2C slave address
1581 * offset + 3 (8 bit): count
1582 * offset + 4 (8 bit): data 1
1583 * ...
1584 *
1585 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1586 * address" on the I2C bus given by "DCB I2C table entry index"
1587 */
1588
1589 struct drm_device *dev = bios->dev;
1590 uint8_t i2c_index = bios->data[offset + 1];
1591 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1592 uint8_t count = bios->data[offset + 3];
1593 int len = 4 + count;
1594 struct nouveau_i2c_chan *chan;
1595 struct i2c_msg msg;
1596 uint8_t data[256];
1597 int ret, i;
1598
1599 if (!iexec->execute)
1600 return len;
1601
1602 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1603 "Count: 0x%02X\n",
1604 offset, i2c_index, i2c_address, count);
1605
1606 chan = init_i2c_device_find(dev, i2c_index);
1607 if (!chan) {
1608 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1609 return len;
1610 }
1611
1612 for (i = 0; i < count; i++) {
1613 data[i] = bios->data[offset + 4 + i];
1614
1615 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1616 }
1617
1618 if (bios->execute) {
1619 msg.addr = i2c_address;
1620 msg.flags = 0;
1621 msg.len = count;
1622 msg.buf = data;
1623 ret = i2c_transfer(&chan->adapter, &msg, 1);
1624 if (ret != 1) {
1625 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1626 return len;
1627 }
1628 }
1629
1630 return len;
1631 }
1632
1633 static int
1634 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1635 {
1636 /*
1637 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1638 *
1639 * offset (8 bit): opcode
1640 * offset + 1 (8 bit): magic lookup value
1641 * offset + 2 (8 bit): TMDS address
1642 * offset + 3 (8 bit): mask
1643 * offset + 4 (8 bit): data
1644 *
1645 * Read the data reg for TMDS address "TMDS address", AND it with mask
1646 * and OR it with data, then write it back
1647 * "magic lookup value" determines which TMDS base address register is
1648 * used -- see get_tmds_index_reg()
1649 */
1650
1651 struct drm_device *dev = bios->dev;
1652 uint8_t mlv = bios->data[offset + 1];
1653 uint32_t tmdsaddr = bios->data[offset + 2];
1654 uint8_t mask = bios->data[offset + 3];
1655 uint8_t data = bios->data[offset + 4];
1656 uint32_t reg, value;
1657
1658 if (!iexec->execute)
1659 return 5;
1660
1661 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1662 "Mask: 0x%02X, Data: 0x%02X\n",
1663 offset, mlv, tmdsaddr, mask, data);
1664
1665 reg = get_tmds_index_reg(bios->dev, mlv);
1666 if (!reg) {
1667 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1668 return 5;
1669 }
1670
1671 bios_wr32(bios, reg,
1672 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1673 value = (bios_rd32(bios, reg + 4) & mask) | data;
1674 bios_wr32(bios, reg + 4, value);
1675 bios_wr32(bios, reg, tmdsaddr);
1676
1677 return 5;
1678 }
1679
1680 static int
1681 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1682 struct init_exec *iexec)
1683 {
1684 /*
1685 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1686 *
1687 * offset (8 bit): opcode
1688 * offset + 1 (8 bit): magic lookup value
1689 * offset + 2 (8 bit): count
1690 * offset + 3 (8 bit): addr 1
1691 * offset + 4 (8 bit): data 1
1692 * ...
1693 *
1694 * For each of "count" TMDS address and data pairs write "data n" to
1695 * "addr n". "magic lookup value" determines which TMDS base address
1696 * register is used -- see get_tmds_index_reg()
1697 */
1698
1699 struct drm_device *dev = bios->dev;
1700 uint8_t mlv = bios->data[offset + 1];
1701 uint8_t count = bios->data[offset + 2];
1702 int len = 3 + count * 2;
1703 uint32_t reg;
1704 int i;
1705
1706 if (!iexec->execute)
1707 return len;
1708
1709 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1710 offset, mlv, count);
1711
1712 reg = get_tmds_index_reg(bios->dev, mlv);
1713 if (!reg) {
1714 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1715 return len;
1716 }
1717
1718 for (i = 0; i < count; i++) {
1719 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1720 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1721
1722 bios_wr32(bios, reg + 4, tmdsdata);
1723 bios_wr32(bios, reg, tmdsaddr);
1724 }
1725
1726 return len;
1727 }
1728
1729 static int
1730 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1731 struct init_exec *iexec)
1732 {
1733 /*
1734 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1735 *
1736 * offset (8 bit): opcode
1737 * offset + 1 (8 bit): CRTC index1
1738 * offset + 2 (8 bit): CRTC index2
1739 * offset + 3 (8 bit): baseaddr
1740 * offset + 4 (8 bit): count
1741 * offset + 5 (8 bit): data 1
1742 * ...
1743 *
1744 * For each of "count" address and data pairs, write "baseaddr + n" to
1745 * "CRTC index1" and "data n" to "CRTC index2"
1746 * Once complete, restore initial value read from "CRTC index1"
1747 */
1748 uint8_t crtcindex1 = bios->data[offset + 1];
1749 uint8_t crtcindex2 = bios->data[offset + 2];
1750 uint8_t baseaddr = bios->data[offset + 3];
1751 uint8_t count = bios->data[offset + 4];
1752 int len = 5 + count;
1753 uint8_t oldaddr, data;
1754 int i;
1755
1756 if (!iexec->execute)
1757 return len;
1758
1759 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1760 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1761 offset, crtcindex1, crtcindex2, baseaddr, count);
1762
1763 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1764
1765 for (i = 0; i < count; i++) {
1766 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1767 baseaddr + i);
1768 data = bios->data[offset + 5 + i];
1769 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1770 }
1771
1772 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1773
1774 return len;
1775 }
1776
1777 static int
1778 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1779 {
1780 /*
1781 * INIT_CR opcode: 0x52 ('R')
1782 *
1783 * offset (8 bit): opcode
1784 * offset + 1 (8 bit): CRTC index
1785 * offset + 2 (8 bit): mask
1786 * offset + 3 (8 bit): data
1787 *
1788 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1789 * data back to "CRTC index"
1790 */
1791
1792 uint8_t crtcindex = bios->data[offset + 1];
1793 uint8_t mask = bios->data[offset + 2];
1794 uint8_t data = bios->data[offset + 3];
1795 uint8_t value;
1796
1797 if (!iexec->execute)
1798 return 4;
1799
1800 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1801 offset, crtcindex, mask, data);
1802
1803 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1804 value |= data;
1805 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1806
1807 return 4;
1808 }
1809
1810 static int
1811 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1812 {
1813 /*
1814 * INIT_ZM_CR opcode: 0x53 ('S')
1815 *
1816 * offset (8 bit): opcode
1817 * offset + 1 (8 bit): CRTC index
1818 * offset + 2 (8 bit): value
1819 *
1820 * Assign "value" to CRTC register with index "CRTC index".
1821 */
1822
1823 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1824 uint8_t data = bios->data[offset + 2];
1825
1826 if (!iexec->execute)
1827 return 3;
1828
1829 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1830
1831 return 3;
1832 }
1833
1834 static int
1835 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1836 {
1837 /*
1838 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1839 *
1840 * offset (8 bit): opcode
1841 * offset + 1 (8 bit): count
1842 * offset + 2 (8 bit): CRTC index 1
1843 * offset + 3 (8 bit): value 1
1844 * ...
1845 *
1846 * For "count", assign "value n" to CRTC register with index
1847 * "CRTC index n".
1848 */
1849
1850 uint8_t count = bios->data[offset + 1];
1851 int len = 2 + count * 2;
1852 int i;
1853
1854 if (!iexec->execute)
1855 return len;
1856
1857 for (i = 0; i < count; i++)
1858 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1859
1860 return len;
1861 }
1862
1863 static int
1864 init_condition_time(struct nvbios *bios, uint16_t offset,
1865 struct init_exec *iexec)
1866 {
1867 /*
1868 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1869 *
1870 * offset (8 bit): opcode
1871 * offset + 1 (8 bit): condition number
1872 * offset + 2 (8 bit): retries / 50
1873 *
1874 * Check condition "condition number" in the condition table.
1875 * Bios code then sleeps for 2ms if the condition is not met, and
1876 * repeats up to "retries" times, but on one C51 this has proved
1877 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1878 * this, and bail after "retries" times, or 2s, whichever is less.
1879 * If still not met after retries, clear execution flag for this table.
1880 */
1881
1882 uint8_t cond = bios->data[offset + 1];
1883 uint16_t retries = bios->data[offset + 2] * 50;
1884 unsigned cnt;
1885
1886 if (!iexec->execute)
1887 return 3;
1888
1889 if (retries > 100)
1890 retries = 100;
1891
1892 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1893 offset, cond, retries);
1894
1895 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1896 retries = 1;
1897
1898 for (cnt = 0; cnt < retries; cnt++) {
1899 if (bios_condition_met(bios, offset, cond)) {
1900 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1901 offset);
1902 break;
1903 } else {
1904 BIOSLOG(bios, "0x%04X: "
1905 "Condition not met, sleeping for 20ms\n",
1906 offset);
1907 msleep(20);
1908 }
1909 }
1910
1911 if (!bios_condition_met(bios, offset, cond)) {
1912 NV_WARN(bios->dev,
1913 "0x%04X: Condition still not met after %dms, "
1914 "skipping following opcodes\n", offset, 20 * retries);
1915 iexec->execute = false;
1916 }
1917
1918 return 3;
1919 }
1920
1921 static int
1922 init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1923 {
1924 /*
1925 * INIT_LTIME opcode: 0x57 ('V')
1926 *
1927 * offset (8 bit): opcode
1928 * offset + 1 (16 bit): time
1929 *
1930 * Sleep for "time" milliseconds.
1931 */
1932
1933 unsigned time = ROM16(bios->data[offset + 1]);
1934
1935 if (!iexec->execute)
1936 return 3;
1937
1938 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1939 offset, time);
1940
1941 msleep(time);
1942
1943 return 3;
1944 }
1945
1946 static int
1947 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1948 struct init_exec *iexec)
1949 {
1950 /*
1951 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1952 *
1953 * offset (8 bit): opcode
1954 * offset + 1 (32 bit): base register
1955 * offset + 5 (8 bit): count
1956 * offset + 6 (32 bit): value 1
1957 * ...
1958 *
1959 * Starting at offset + 6 there are "count" 32 bit values.
1960 * For "count" iterations set "base register" + 4 * current_iteration
1961 * to "value current_iteration"
1962 */
1963
1964 uint32_t basereg = ROM32(bios->data[offset + 1]);
1965 uint32_t count = bios->data[offset + 5];
1966 int len = 6 + count * 4;
1967 int i;
1968
1969 if (!iexec->execute)
1970 return len;
1971
1972 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1973 offset, basereg, count);
1974
1975 for (i = 0; i < count; i++) {
1976 uint32_t reg = basereg + i * 4;
1977 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1978
1979 bios_wr32(bios, reg, data);
1980 }
1981
1982 return len;
1983 }
1984
1985 static int
1986 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1987 {
1988 /*
1989 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1990 *
1991 * offset (8 bit): opcode
1992 * offset + 1 (16 bit): subroutine offset (in bios)
1993 *
1994 * Calls a subroutine that will execute commands until INIT_DONE
1995 * is found.
1996 */
1997
1998 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1999
2000 if (!iexec->execute)
2001 return 3;
2002
2003 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
2004 offset, sub_offset);
2005
2006 parse_init_table(bios, sub_offset, iexec);
2007
2008 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
2009
2010 return 3;
2011 }
2012
2013 static int
2014 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2015 {
2016 /*
2017 * INIT_I2C_IF opcode: 0x5E ('^')
2018 *
2019 * offset (8 bit): opcode
2020 * offset + 1 (8 bit): DCB I2C table entry index
2021 * offset + 2 (8 bit): I2C slave address
2022 * offset + 3 (8 bit): I2C register
2023 * offset + 4 (8 bit): mask
2024 * offset + 5 (8 bit): data
2025 *
2026 * Read the register given by "I2C register" on the device addressed
2027 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2028 * entry index". Compare the result AND "mask" to "data".
2029 * If they're not equal, skip subsequent opcodes until condition is
2030 * inverted (INIT_NOT), or we hit INIT_RESUME
2031 */
2032
2033 uint8_t i2c_index = bios->data[offset + 1];
2034 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2035 uint8_t reg = bios->data[offset + 3];
2036 uint8_t mask = bios->data[offset + 4];
2037 uint8_t data = bios->data[offset + 5];
2038 struct nouveau_i2c_chan *chan;
2039 union i2c_smbus_data val;
2040 int ret;
2041
2042 /* no execute check by design */
2043
2044 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2045 offset, i2c_index, i2c_address);
2046
2047 chan = init_i2c_device_find(bios->dev, i2c_index);
2048 if (!chan)
2049 return -ENODEV;
2050
2051 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2052 I2C_SMBUS_READ, reg,
2053 I2C_SMBUS_BYTE_DATA, &val);
2054 if (ret < 0) {
2055 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2056 "Mask: 0x%02X, Data: 0x%02X\n",
2057 offset, reg, mask, data);
2058 iexec->execute = 0;
2059 return 6;
2060 }
2061
2062 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2063 "Mask: 0x%02X, Data: 0x%02X\n",
2064 offset, reg, val.byte, mask, data);
2065
2066 iexec->execute = ((val.byte & mask) == data);
2067
2068 return 6;
2069 }
2070
2071 static int
2072 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2073 {
2074 /*
2075 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2076 *
2077 * offset (8 bit): opcode
2078 * offset + 1 (32 bit): src reg
2079 * offset + 5 (8 bit): shift
2080 * offset + 6 (32 bit): src mask
2081 * offset + 10 (32 bit): xor
2082 * offset + 14 (32 bit): dst reg
2083 * offset + 18 (32 bit): dst mask
2084 *
2085 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2086 * "src mask", then XOR with "xor". Write this OR'd with
2087 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2088 */
2089
2090 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2091 uint8_t shift = bios->data[offset + 5];
2092 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2093 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2094 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2095 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2096 uint32_t srcvalue, dstvalue;
2097
2098 if (!iexec->execute)
2099 return 22;
2100
2101 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2102 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2103 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2104
2105 srcvalue = bios_rd32(bios, srcreg);
2106
2107 if (shift < 0x80)
2108 srcvalue >>= shift;
2109 else
2110 srcvalue <<= (0x100 - shift);
2111
2112 srcvalue = (srcvalue & srcmask) ^ xor;
2113
2114 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2115
2116 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2117
2118 return 22;
2119 }
2120
2121 static int
2122 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2123 {
2124 /*
2125 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2126 *
2127 * offset (8 bit): opcode
2128 * offset + 1 (16 bit): CRTC port
2129 * offset + 3 (8 bit): CRTC index
2130 * offset + 4 (8 bit): data
2131 *
2132 * Write "data" to index "CRTC index" of "CRTC port"
2133 */
2134 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2135 uint8_t crtcindex = bios->data[offset + 3];
2136 uint8_t data = bios->data[offset + 4];
2137
2138 if (!iexec->execute)
2139 return 5;
2140
2141 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2142
2143 return 5;
2144 }
2145
2146 static inline void
2147 bios_md32(struct nvbios *bios, uint32_t reg,
2148 uint32_t mask, uint32_t val)
2149 {
2150 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2151 }
2152
2153 static uint32_t
2154 peek_fb(struct drm_device *dev, struct io_mapping *fb,
2155 uint32_t off)
2156 {
2157 uint32_t val = 0;
2158
2159 if (off < pci_resource_len(dev->pdev, 1)) {
2160 uint8_t __iomem *p =
2161 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2162
2163 val = ioread32(p + (off & ~PAGE_MASK));
2164
2165 io_mapping_unmap_atomic(p);
2166 }
2167
2168 return val;
2169 }
2170
2171 static void
2172 poke_fb(struct drm_device *dev, struct io_mapping *fb,
2173 uint32_t off, uint32_t val)
2174 {
2175 if (off < pci_resource_len(dev->pdev, 1)) {
2176 uint8_t __iomem *p =
2177 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2178
2179 iowrite32(val, p + (off & ~PAGE_MASK));
2180 wmb();
2181
2182 io_mapping_unmap_atomic(p);
2183 }
2184 }
2185
2186 static inline bool
2187 read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2188 uint32_t off, uint32_t val)
2189 {
2190 poke_fb(dev, fb, off, val);
2191 return val == peek_fb(dev, fb, off);
2192 }
2193
2194 static int
2195 nv04_init_compute_mem(struct nvbios *bios)
2196 {
2197 struct drm_device *dev = bios->dev;
2198 uint32_t patt = 0xdeadbeef;
2199 struct io_mapping *fb;
2200 int i;
2201
2202 /* Map the framebuffer aperture */
2203 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2204 pci_resource_len(dev->pdev, 1));
2205 if (!fb)
2206 return -ENOMEM;
2207
2208 /* Sequencer and refresh off */
2209 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2210 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2211
2212 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2213 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2214 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2215 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2216
2217 for (i = 0; i < 4; i++)
2218 poke_fb(dev, fb, 4 * i, patt);
2219
2220 poke_fb(dev, fb, 0x400000, patt + 1);
2221
2222 if (peek_fb(dev, fb, 0) == patt + 1) {
2223 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2224 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2225 bios_md32(bios, NV04_PFB_DEBUG_0,
2226 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2227
2228 for (i = 0; i < 4; i++)
2229 poke_fb(dev, fb, 4 * i, patt);
2230
2231 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2232 bios_md32(bios, NV04_PFB_BOOT_0,
2233 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2234 NV04_PFB_BOOT_0_RAM_AMOUNT,
2235 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2236
2237 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2238 (patt & 0xffff0000)) {
2239 bios_md32(bios, NV04_PFB_BOOT_0,
2240 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2241 NV04_PFB_BOOT_0_RAM_AMOUNT,
2242 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2243
2244 } else if (peek_fb(dev, fb, 0) != patt) {
2245 if (read_back_fb(dev, fb, 0x800000, patt))
2246 bios_md32(bios, NV04_PFB_BOOT_0,
2247 NV04_PFB_BOOT_0_RAM_AMOUNT,
2248 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2249 else
2250 bios_md32(bios, NV04_PFB_BOOT_0,
2251 NV04_PFB_BOOT_0_RAM_AMOUNT,
2252 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2253
2254 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2255 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2256
2257 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2258 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2259 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2260
2261 }
2262
2263 /* Refresh on, sequencer on */
2264 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2265 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2266
2267 io_mapping_free(fb);
2268 return 0;
2269 }
2270
2271 static const uint8_t *
2272 nv05_memory_config(struct nvbios *bios)
2273 {
2274 /* Defaults for BIOSes lacking a memory config table */
2275 static const uint8_t default_config_tab[][2] = {
2276 { 0x24, 0x00 },
2277 { 0x28, 0x00 },
2278 { 0x24, 0x01 },
2279 { 0x1f, 0x00 },
2280 { 0x0f, 0x00 },
2281 { 0x17, 0x00 },
2282 { 0x06, 0x00 },
2283 { 0x00, 0x00 }
2284 };
2285 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2286 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2287
2288 if (bios->legacy.mem_init_tbl_ptr)
2289 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2290 else
2291 return default_config_tab[i];
2292 }
2293
2294 static int
2295 nv05_init_compute_mem(struct nvbios *bios)
2296 {
2297 struct drm_device *dev = bios->dev;
2298 const uint8_t *ramcfg = nv05_memory_config(bios);
2299 uint32_t patt = 0xdeadbeef;
2300 struct io_mapping *fb;
2301 int i, v;
2302
2303 /* Map the framebuffer aperture */
2304 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2305 pci_resource_len(dev->pdev, 1));
2306 if (!fb)
2307 return -ENOMEM;
2308
2309 /* Sequencer off */
2310 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2311
2312 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2313 goto out;
2314
2315 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2316
2317 /* If present load the hardcoded scrambling table */
2318 if (bios->legacy.mem_init_tbl_ptr) {
2319 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2320 bios->legacy.mem_init_tbl_ptr + 0x10];
2321
2322 for (i = 0; i < 8; i++)
2323 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2324 ROM32(scramble_tab[i]));
2325 }
2326
2327 /* Set memory type/width/length defaults depending on the straps */
2328 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2329
2330 if (ramcfg[1] & 0x80)
2331 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2332
2333 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2334 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2335
2336 /* Probe memory bus width */
2337 for (i = 0; i < 4; i++)
2338 poke_fb(dev, fb, 4 * i, patt);
2339
2340 if (peek_fb(dev, fb, 0xc) != patt)
2341 bios_md32(bios, NV04_PFB_BOOT_0,
2342 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2343
2344 /* Probe memory length */
2345 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2346
2347 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2348 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2349 !read_back_fb(dev, fb, 0, ++patt)))
2350 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2351 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2352
2353 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2354 !read_back_fb(dev, fb, 0x800000, ++patt))
2355 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2356 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2357
2358 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2359 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2360 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2361
2362 out:
2363 /* Sequencer on */
2364 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2365
2366 io_mapping_free(fb);
2367 return 0;
2368 }
2369
2370 static int
2371 nv10_init_compute_mem(struct nvbios *bios)
2372 {
2373 struct drm_device *dev = bios->dev;
2374 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2375 const int mem_width[] = { 0x10, 0x00, 0x20 };
2376 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2377 uint32_t patt = 0xdeadbeef;
2378 struct io_mapping *fb;
2379 int i, j, k;
2380
2381 /* Map the framebuffer aperture */
2382 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2383 pci_resource_len(dev->pdev, 1));
2384 if (!fb)
2385 return -ENOMEM;
2386
2387 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2388
2389 /* Probe memory bus width */
2390 for (i = 0; i < mem_width_count; i++) {
2391 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2392
2393 for (j = 0; j < 4; j++) {
2394 for (k = 0; k < 4; k++)
2395 poke_fb(dev, fb, 0x1c, 0);
2396
2397 poke_fb(dev, fb, 0x1c, patt);
2398 poke_fb(dev, fb, 0x3c, 0);
2399
2400 if (peek_fb(dev, fb, 0x1c) == patt)
2401 goto mem_width_found;
2402 }
2403 }
2404
2405 mem_width_found:
2406 patt <<= 1;
2407
2408 /* Probe amount of installed memory */
2409 for (i = 0; i < 4; i++) {
2410 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2411
2412 poke_fb(dev, fb, off, patt);
2413 poke_fb(dev, fb, 0, 0);
2414
2415 peek_fb(dev, fb, 0);
2416 peek_fb(dev, fb, 0);
2417 peek_fb(dev, fb, 0);
2418 peek_fb(dev, fb, 0);
2419
2420 if (peek_fb(dev, fb, off) == patt)
2421 goto amount_found;
2422 }
2423
2424 /* IC missing - disable the upper half memory space. */
2425 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2426
2427 amount_found:
2428 io_mapping_free(fb);
2429 return 0;
2430 }
2431
2432 static int
2433 nv20_init_compute_mem(struct nvbios *bios)
2434 {
2435 struct drm_device *dev = bios->dev;
2436 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2437 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2438 uint32_t amount, off;
2439 struct io_mapping *fb;
2440
2441 /* Map the framebuffer aperture */
2442 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2443 pci_resource_len(dev->pdev, 1));
2444 if (!fb)
2445 return -ENOMEM;
2446
2447 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2448
2449 /* Allow full addressing */
2450 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2451
2452 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2453 for (off = amount; off > 0x2000000; off -= 0x2000000)
2454 poke_fb(dev, fb, off - 4, off);
2455
2456 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2457 if (amount != peek_fb(dev, fb, amount - 4))
2458 /* IC missing - disable the upper half memory space. */
2459 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2460
2461 io_mapping_free(fb);
2462 return 0;
2463 }
2464
2465 static int
2466 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2467 {
2468 /*
2469 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2470 *
2471 * offset (8 bit): opcode
2472 *
2473 * This opcode is meant to set the PFB memory config registers
2474 * appropriately so that we can correctly calculate how much VRAM it
2475 * has (on nv10 and better chipsets the amount of installed VRAM is
2476 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2477 *
2478 * The implementation of this opcode in general consists of several
2479 * parts:
2480 *
2481 * 1) Determination of memory type and density. Only necessary for
2482 * really old chipsets, the memory type reported by the strap bits
2483 * (0x101000) is assumed to be accurate on nv05 and newer.
2484 *
2485 * 2) Determination of the memory bus width. Usually done by a cunning
2486 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2487 * seeing whether the written values are read back correctly.
2488 *
2489 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2490 * trust the straps.
2491 *
2492 * 3) Determination of how many of the card's RAM pads have ICs
2493 * attached, usually done by a cunning combination of writes to an
2494 * offset slightly less than the maximum memory reported by
2495 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2496 *
2497 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2498 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2499 * card show nothing being done for this opcode. Why is it still listed
2500 * in the table?!
2501 */
2502
2503 /* no iexec->execute check by design */
2504
2505 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2506 int ret;
2507
2508 if (dev_priv->chipset >= 0x40 ||
2509 dev_priv->chipset == 0x1a ||
2510 dev_priv->chipset == 0x1f)
2511 ret = 0;
2512 else if (dev_priv->chipset >= 0x20 &&
2513 dev_priv->chipset != 0x34)
2514 ret = nv20_init_compute_mem(bios);
2515 else if (dev_priv->chipset >= 0x10)
2516 ret = nv10_init_compute_mem(bios);
2517 else if (dev_priv->chipset >= 0x5)
2518 ret = nv05_init_compute_mem(bios);
2519 else
2520 ret = nv04_init_compute_mem(bios);
2521
2522 if (ret)
2523 return ret;
2524
2525 return 1;
2526 }
2527
2528 static int
2529 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2530 {
2531 /*
2532 * INIT_RESET opcode: 0x65 ('e')
2533 *
2534 * offset (8 bit): opcode
2535 * offset + 1 (32 bit): register
2536 * offset + 5 (32 bit): value1
2537 * offset + 9 (32 bit): value2
2538 *
2539 * Assign "value1" to "register", then assign "value2" to "register"
2540 */
2541
2542 uint32_t reg = ROM32(bios->data[offset + 1]);
2543 uint32_t value1 = ROM32(bios->data[offset + 5]);
2544 uint32_t value2 = ROM32(bios->data[offset + 9]);
2545 uint32_t pci_nv_19, pci_nv_20;
2546
2547 /* no iexec->execute check by design */
2548
2549 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2550 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2551
2552 bios_wr32(bios, reg, value1);
2553
2554 udelay(10);
2555
2556 bios_wr32(bios, reg, value2);
2557 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2558
2559 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2560 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2561 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2562
2563 return 13;
2564 }
2565
2566 static int
2567 init_configure_mem(struct nvbios *bios, uint16_t offset,
2568 struct init_exec *iexec)
2569 {
2570 /*
2571 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2572 *
2573 * offset (8 bit): opcode
2574 *
2575 * Equivalent to INIT_DONE on bios version 3 or greater.
2576 * For early bios versions, sets up the memory registers, using values
2577 * taken from the memory init table
2578 */
2579
2580 /* no iexec->execute check by design */
2581
2582 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2583 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2584 uint32_t reg, data;
2585
2586 if (bios->major_version > 2)
2587 return 0;
2588
2589 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2590 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2591
2592 if (bios->data[meminitoffs] & 1)
2593 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2594
2595 for (reg = ROM32(bios->data[seqtbloffs]);
2596 reg != 0xffffffff;
2597 reg = ROM32(bios->data[seqtbloffs += 4])) {
2598
2599 switch (reg) {
2600 case NV04_PFB_PRE:
2601 data = NV04_PFB_PRE_CMD_PRECHARGE;
2602 break;
2603 case NV04_PFB_PAD:
2604 data = NV04_PFB_PAD_CKE_NORMAL;
2605 break;
2606 case NV04_PFB_REF:
2607 data = NV04_PFB_REF_CMD_REFRESH;
2608 break;
2609 default:
2610 data = ROM32(bios->data[meminitdata]);
2611 meminitdata += 4;
2612 if (data == 0xffffffff)
2613 continue;
2614 }
2615
2616 bios_wr32(bios, reg, data);
2617 }
2618
2619 return 1;
2620 }
2621
2622 static int
2623 init_configure_clk(struct nvbios *bios, uint16_t offset,
2624 struct init_exec *iexec)
2625 {
2626 /*
2627 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2628 *
2629 * offset (8 bit): opcode
2630 *
2631 * Equivalent to INIT_DONE on bios version 3 or greater.
2632 * For early bios versions, sets up the NVClk and MClk PLLs, using
2633 * values taken from the memory init table
2634 */
2635
2636 /* no iexec->execute check by design */
2637
2638 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2639 int clock;
2640
2641 if (bios->major_version > 2)
2642 return 0;
2643
2644 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2645 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2646
2647 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2648 if (bios->data[meminitoffs] & 1) /* DDR */
2649 clock *= 2;
2650 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2651
2652 return 1;
2653 }
2654
2655 static int
2656 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2657 struct init_exec *iexec)
2658 {
2659 /*
2660 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2661 *
2662 * offset (8 bit): opcode
2663 *
2664 * Equivalent to INIT_DONE on bios version 3 or greater.
2665 * For early bios versions, does early init, loading ram and crystal
2666 * configuration from straps into CR3C
2667 */
2668
2669 /* no iexec->execute check by design */
2670
2671 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2672 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2673
2674 if (bios->major_version > 2)
2675 return 0;
2676
2677 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2678 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2679
2680 return 1;
2681 }
2682
2683 static int
2684 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2685 {
2686 /*
2687 * INIT_IO opcode: 0x69 ('i')
2688 *
2689 * offset (8 bit): opcode
2690 * offset + 1 (16 bit): CRTC port
2691 * offset + 3 (8 bit): mask
2692 * offset + 4 (8 bit): data
2693 *
2694 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2695 */
2696
2697 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2698 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2699 uint8_t mask = bios->data[offset + 3];
2700 uint8_t data = bios->data[offset + 4];
2701
2702 if (!iexec->execute)
2703 return 5;
2704
2705 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2706 offset, crtcport, mask, data);
2707
2708 /*
2709 * I have no idea what this does, but NVIDIA do this magic sequence
2710 * in the places where this INIT_IO happens..
2711 */
2712 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2713 int i;
2714
2715 bios_wr32(bios, 0x614100, (bios_rd32(
2716 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2717
2718 bios_wr32(bios, 0x00e18c, bios_rd32(
2719 bios, 0x00e18c) | 0x00020000);
2720
2721 bios_wr32(bios, 0x614900, (bios_rd32(
2722 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2723
2724 bios_wr32(bios, 0x000200, bios_rd32(
2725 bios, 0x000200) & ~0x40000000);
2726
2727 mdelay(10);
2728
2729 bios_wr32(bios, 0x00e18c, bios_rd32(
2730 bios, 0x00e18c) & ~0x00020000);
2731
2732 bios_wr32(bios, 0x000200, bios_rd32(
2733 bios, 0x000200) | 0x40000000);
2734
2735 bios_wr32(bios, 0x614100, 0x00800018);
2736 bios_wr32(bios, 0x614900, 0x00800018);
2737
2738 mdelay(10);
2739
2740 bios_wr32(bios, 0x614100, 0x10000018);
2741 bios_wr32(bios, 0x614900, 0x10000018);
2742
2743 for (i = 0; i < 3; i++)
2744 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2745 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2746
2747 for (i = 0; i < 2; i++)
2748 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2749 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2750
2751 for (i = 0; i < 3; i++)
2752 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2753 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2754
2755 for (i = 0; i < 2; i++)
2756 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2757 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2758
2759 for (i = 0; i < 2; i++)
2760 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2761 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2762 return 5;
2763 }
2764
2765 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2766 data);
2767 return 5;
2768 }
2769
2770 static int
2771 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2772 {
2773 /*
2774 * INIT_SUB opcode: 0x6B ('k')
2775 *
2776 * offset (8 bit): opcode
2777 * offset + 1 (8 bit): script number
2778 *
2779 * Execute script number "script number", as a subroutine
2780 */
2781
2782 uint8_t sub = bios->data[offset + 1];
2783
2784 if (!iexec->execute)
2785 return 2;
2786
2787 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2788
2789 parse_init_table(bios,
2790 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2791 iexec);
2792
2793 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2794
2795 return 2;
2796 }
2797
2798 static int
2799 init_ram_condition(struct nvbios *bios, uint16_t offset,
2800 struct init_exec *iexec)
2801 {
2802 /*
2803 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2804 *
2805 * offset (8 bit): opcode
2806 * offset + 1 (8 bit): mask
2807 * offset + 2 (8 bit): cmpval
2808 *
2809 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2810 * If condition not met skip subsequent opcodes until condition is
2811 * inverted (INIT_NOT), or we hit INIT_RESUME
2812 */
2813
2814 uint8_t mask = bios->data[offset + 1];
2815 uint8_t cmpval = bios->data[offset + 2];
2816 uint8_t data;
2817
2818 if (!iexec->execute)
2819 return 3;
2820
2821 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2822
2823 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2824 offset, data, cmpval);
2825
2826 if (data == cmpval)
2827 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2828 else {
2829 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2830 iexec->execute = false;
2831 }
2832
2833 return 3;
2834 }
2835
2836 static int
2837 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2838 {
2839 /*
2840 * INIT_NV_REG opcode: 0x6E ('n')
2841 *
2842 * offset (8 bit): opcode
2843 * offset + 1 (32 bit): register
2844 * offset + 5 (32 bit): mask
2845 * offset + 9 (32 bit): data
2846 *
2847 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2848 */
2849
2850 uint32_t reg = ROM32(bios->data[offset + 1]);
2851 uint32_t mask = ROM32(bios->data[offset + 5]);
2852 uint32_t data = ROM32(bios->data[offset + 9]);
2853
2854 if (!iexec->execute)
2855 return 13;
2856
2857 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2858 offset, reg, mask, data);
2859
2860 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2861
2862 return 13;
2863 }
2864
2865 static int
2866 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2867 {
2868 /*
2869 * INIT_MACRO opcode: 0x6F ('o')
2870 *
2871 * offset (8 bit): opcode
2872 * offset + 1 (8 bit): macro number
2873 *
2874 * Look up macro index "macro number" in the macro index table.
2875 * The macro index table entry has 1 byte for the index in the macro
2876 * table, and 1 byte for the number of times to repeat the macro.
2877 * The macro table entry has 4 bytes for the register address and
2878 * 4 bytes for the value to write to that register
2879 */
2880
2881 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2882 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2883 uint8_t macro_tbl_idx = bios->data[tmp];
2884 uint8_t count = bios->data[tmp + 1];
2885 uint32_t reg, data;
2886 int i;
2887
2888 if (!iexec->execute)
2889 return 2;
2890
2891 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2892 "Count: 0x%02X\n",
2893 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2894
2895 for (i = 0; i < count; i++) {
2896 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2897
2898 reg = ROM32(bios->data[macroentryptr]);
2899 data = ROM32(bios->data[macroentryptr + 4]);
2900
2901 bios_wr32(bios, reg, data);
2902 }
2903
2904 return 2;
2905 }
2906
2907 static int
2908 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2909 {
2910 /*
2911 * INIT_DONE opcode: 0x71 ('q')
2912 *
2913 * offset (8 bit): opcode
2914 *
2915 * End the current script
2916 */
2917
2918 /* mild retval abuse to stop parsing this table */
2919 return 0;
2920 }
2921
2922 static int
2923 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2924 {
2925 /*
2926 * INIT_RESUME opcode: 0x72 ('r')
2927 *
2928 * offset (8 bit): opcode
2929 *
2930 * End the current execute / no-execute condition
2931 */
2932
2933 if (iexec->execute)
2934 return 1;
2935
2936 iexec->execute = true;
2937 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2938
2939 return 1;
2940 }
2941
2942 static int
2943 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2944 {
2945 /*
2946 * INIT_TIME opcode: 0x74 ('t')
2947 *
2948 * offset (8 bit): opcode
2949 * offset + 1 (16 bit): time
2950 *
2951 * Sleep for "time" microseconds.
2952 */
2953
2954 unsigned time = ROM16(bios->data[offset + 1]);
2955
2956 if (!iexec->execute)
2957 return 3;
2958
2959 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2960 offset, time);
2961
2962 if (time < 1000)
2963 udelay(time);
2964 else
2965 msleep((time + 900) / 1000);
2966
2967 return 3;
2968 }
2969
2970 static int
2971 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2972 {
2973 /*
2974 * INIT_CONDITION opcode: 0x75 ('u')
2975 *
2976 * offset (8 bit): opcode
2977 * offset + 1 (8 bit): condition number
2978 *
2979 * Check condition "condition number" in the condition table.
2980 * If condition not met skip subsequent opcodes until condition is
2981 * inverted (INIT_NOT), or we hit INIT_RESUME
2982 */
2983
2984 uint8_t cond = bios->data[offset + 1];
2985
2986 if (!iexec->execute)
2987 return 2;
2988
2989 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2990
2991 if (bios_condition_met(bios, offset, cond))
2992 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2993 else {
2994 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2995 iexec->execute = false;
2996 }
2997
2998 return 2;
2999 }
3000
3001 static int
3002 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3003 {
3004 /*
3005 * INIT_IO_CONDITION opcode: 0x76
3006 *
3007 * offset (8 bit): opcode
3008 * offset + 1 (8 bit): condition number
3009 *
3010 * Check condition "condition number" in the io condition table.
3011 * If condition not met skip subsequent opcodes until condition is
3012 * inverted (INIT_NOT), or we hit INIT_RESUME
3013 */
3014
3015 uint8_t cond = bios->data[offset + 1];
3016
3017 if (!iexec->execute)
3018 return 2;
3019
3020 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
3021
3022 if (io_condition_met(bios, offset, cond))
3023 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3024 else {
3025 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3026 iexec->execute = false;
3027 }
3028
3029 return 2;
3030 }
3031
3032 static int
3033 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3034 {
3035 /*
3036 * INIT_INDEX_IO opcode: 0x78 ('x')
3037 *
3038 * offset (8 bit): opcode
3039 * offset + 1 (16 bit): CRTC port
3040 * offset + 3 (8 bit): CRTC index
3041 * offset + 4 (8 bit): mask
3042 * offset + 5 (8 bit): data
3043 *
3044 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3045 * OR with "data", write-back
3046 */
3047
3048 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3049 uint8_t crtcindex = bios->data[offset + 3];
3050 uint8_t mask = bios->data[offset + 4];
3051 uint8_t data = bios->data[offset + 5];
3052 uint8_t value;
3053
3054 if (!iexec->execute)
3055 return 6;
3056
3057 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3058 "Data: 0x%02X\n",
3059 offset, crtcport, crtcindex, mask, data);
3060
3061 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3062 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3063
3064 return 6;
3065 }
3066
3067 static int
3068 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3069 {
3070 /*
3071 * INIT_PLL opcode: 0x79 ('y')
3072 *
3073 * offset (8 bit): opcode
3074 * offset + 1 (32 bit): register
3075 * offset + 5 (16 bit): freq
3076 *
3077 * Set PLL register "register" to coefficients for frequency (10kHz)
3078 * "freq"
3079 */
3080
3081 uint32_t reg = ROM32(bios->data[offset + 1]);
3082 uint16_t freq = ROM16(bios->data[offset + 5]);
3083
3084 if (!iexec->execute)
3085 return 7;
3086
3087 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3088
3089 setPLL(bios, reg, freq * 10);
3090
3091 return 7;
3092 }
3093
3094 static int
3095 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3096 {
3097 /*
3098 * INIT_ZM_REG opcode: 0x7A ('z')
3099 *
3100 * offset (8 bit): opcode
3101 * offset + 1 (32 bit): register
3102 * offset + 5 (32 bit): value
3103 *
3104 * Assign "value" to "register"
3105 */
3106
3107 uint32_t reg = ROM32(bios->data[offset + 1]);
3108 uint32_t value = ROM32(bios->data[offset + 5]);
3109
3110 if (!iexec->execute)
3111 return 9;
3112
3113 if (reg == 0x000200)
3114 value |= 1;
3115
3116 bios_wr32(bios, reg, value);
3117
3118 return 9;
3119 }
3120
3121 static int
3122 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3123 struct init_exec *iexec)
3124 {
3125 /*
3126 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3127 *
3128 * offset (8 bit): opcode
3129 * offset + 1 (8 bit): PLL type
3130 * offset + 2 (32 bit): frequency 0
3131 *
3132 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3133 * ram_restrict_table_ptr. The value read from there is used to select
3134 * a frequency from the table starting at 'frequency 0' to be
3135 * programmed into the PLL corresponding to 'type'.
3136 *
3137 * The PLL limits table on cards using this opcode has a mapping of
3138 * 'type' to the relevant registers.
3139 */
3140
3141 struct drm_device *dev = bios->dev;
3142 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3143 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3144 uint8_t type = bios->data[offset + 1];
3145 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3146 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
3147 int len = 2 + bios->ram_restrict_group_count * 4;
3148 int i;
3149
3150 if (!iexec->execute)
3151 return len;
3152
3153 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3154 NV_ERROR(dev, "PLL limits table not version 3.x\n");
3155 return len; /* deliberate, allow default clocks to remain */
3156 }
3157
3158 entry = pll_limits + pll_limits[1];
3159 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3160 if (entry[0] == type) {
3161 uint32_t reg = ROM32(entry[3]);
3162
3163 BIOSLOG(bios, "0x%04X: "
3164 "Type %02x Reg 0x%08x Freq %dKHz\n",
3165 offset, type, reg, freq);
3166
3167 setPLL(bios, reg, freq);
3168 return len;
3169 }
3170 }
3171
3172 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
3173 return len;
3174 }
3175
3176 static int
3177 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3178 {
3179 /*
3180 * INIT_8C opcode: 0x8C ('')
3181 *
3182 * NOP so far....
3183 *
3184 */
3185
3186 return 1;
3187 }
3188
3189 static int
3190 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3191 {
3192 /*
3193 * INIT_8D opcode: 0x8D ('')
3194 *
3195 * NOP so far....
3196 *
3197 */
3198
3199 return 1;
3200 }
3201
3202 static int
3203 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3204 {
3205 /*
3206 * INIT_GPIO opcode: 0x8E ('')
3207 *
3208 * offset (8 bit): opcode
3209 *
3210 * Loop over all entries in the DCB GPIO table, and initialise
3211 * each GPIO according to various values listed in each entry
3212 */
3213
3214 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
3215 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
3216 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
3217 int i;
3218
3219 if (dev_priv->card_type < NV_50) {
3220 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
3221 return 1;
3222 }
3223
3224 if (!iexec->execute)
3225 return 1;
3226
3227 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3228 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
3229 uint32_t r, s, v;
3230
3231 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
3232
3233 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3234 offset, gpio->tag, gpio->state_default);
3235 if (bios->execute)
3236 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
3237
3238 /* The NVIDIA binary driver doesn't appear to actually do
3239 * any of this, my VBIOS does however.
3240 */
3241 /* Not a clue, needs de-magicing */
3242 r = nv50_gpio_ctl[gpio->line >> 4];
3243 s = (gpio->line & 0x0f);
3244 v = bios_rd32(bios, r) & ~(0x00010001 << s);
3245 switch ((gpio->entry & 0x06000000) >> 25) {
3246 case 1:
3247 v |= (0x00000001 << s);
3248 break;
3249 case 2:
3250 v |= (0x00010000 << s);
3251 break;
3252 default:
3253 break;
3254 }
3255 bios_wr32(bios, r, v);
3256 }
3257
3258 return 1;
3259 }
3260
3261 static int
3262 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3263 struct init_exec *iexec)
3264 {
3265 /*
3266 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3267 *
3268 * offset (8 bit): opcode
3269 * offset + 1 (32 bit): reg
3270 * offset + 5 (8 bit): regincrement
3271 * offset + 6 (8 bit): count
3272 * offset + 7 (32 bit): value 1,1
3273 * ...
3274 *
3275 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3276 * ram_restrict_table_ptr. The value read from here is 'n', and
3277 * "value 1,n" gets written to "reg". This repeats "count" times and on
3278 * each iteration 'm', "reg" increases by "regincrement" and
3279 * "value m,n" is used. The extent of n is limited by a number read
3280 * from the 'M' BIT table, herein called "blocklen"
3281 */
3282
3283 uint32_t reg = ROM32(bios->data[offset + 1]);
3284 uint8_t regincrement = bios->data[offset + 5];
3285 uint8_t count = bios->data[offset + 6];
3286 uint32_t strap_ramcfg, data;
3287 /* previously set by 'M' BIT table */
3288 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3289 int len = 7 + count * blocklen;
3290 uint8_t index;
3291 int i;
3292
3293 /* critical! to know the length of the opcode */;
3294 if (!blocklen) {
3295 NV_ERROR(bios->dev,
3296 "0x%04X: Zero block length - has the M table "
3297 "been parsed?\n", offset);
3298 return -EINVAL;
3299 }
3300
3301 if (!iexec->execute)
3302 return len;
3303
3304 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3305 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3306
3307 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3308 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3309 offset, reg, regincrement, count, strap_ramcfg, index);
3310
3311 for (i = 0; i < count; i++) {
3312 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3313
3314 bios_wr32(bios, reg, data);
3315
3316 reg += regincrement;
3317 }
3318
3319 return len;
3320 }
3321
3322 static int
3323 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3324 {
3325 /*
3326 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3327 *
3328 * offset (8 bit): opcode
3329 * offset + 1 (32 bit): src reg
3330 * offset + 5 (32 bit): dst reg
3331 *
3332 * Put contents of "src reg" into "dst reg"
3333 */
3334
3335 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3336 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3337
3338 if (!iexec->execute)
3339 return 9;
3340
3341 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3342
3343 return 9;
3344 }
3345
3346 static int
3347 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3348 struct init_exec *iexec)
3349 {
3350 /*
3351 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3352 *
3353 * offset (8 bit): opcode
3354 * offset + 1 (32 bit): dst reg
3355 * offset + 5 (8 bit): count
3356 * offset + 6 (32 bit): data 1
3357 * ...
3358 *
3359 * For each of "count" values write "data n" to "dst reg"
3360 */
3361
3362 uint32_t reg = ROM32(bios->data[offset + 1]);
3363 uint8_t count = bios->data[offset + 5];
3364 int len = 6 + count * 4;
3365 int i;
3366
3367 if (!iexec->execute)
3368 return len;
3369
3370 for (i = 0; i < count; i++) {
3371 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3372 bios_wr32(bios, reg, data);
3373 }
3374
3375 return len;
3376 }
3377
3378 static int
3379 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3380 {
3381 /*
3382 * INIT_RESERVED opcode: 0x92 ('')
3383 *
3384 * offset (8 bit): opcode
3385 *
3386 * Seemingly does nothing
3387 */
3388
3389 return 1;
3390 }
3391
3392 static int
3393 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3394 {
3395 /*
3396 * INIT_96 opcode: 0x96 ('')
3397 *
3398 * offset (8 bit): opcode
3399 * offset + 1 (32 bit): sreg
3400 * offset + 5 (8 bit): sshift
3401 * offset + 6 (8 bit): smask
3402 * offset + 7 (8 bit): index
3403 * offset + 8 (32 bit): reg
3404 * offset + 12 (32 bit): mask
3405 * offset + 16 (8 bit): shift
3406 *
3407 */
3408
3409 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3410 uint32_t reg = ROM32(bios->data[offset + 8]);
3411 uint32_t mask = ROM32(bios->data[offset + 12]);
3412 uint32_t val;
3413
3414 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3415 if (bios->data[offset + 5] < 0x80)
3416 val >>= bios->data[offset + 5];
3417 else
3418 val <<= (0x100 - bios->data[offset + 5]);
3419 val &= bios->data[offset + 6];
3420
3421 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3422 val <<= bios->data[offset + 16];
3423
3424 if (!iexec->execute)
3425 return 17;
3426
3427 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3428 return 17;
3429 }
3430
3431 static int
3432 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3433 {
3434 /*
3435 * INIT_97 opcode: 0x97 ('')
3436 *
3437 * offset (8 bit): opcode
3438 * offset + 1 (32 bit): register
3439 * offset + 5 (32 bit): mask
3440 * offset + 9 (32 bit): value
3441 *
3442 * Adds "value" to "register" preserving the fields specified
3443 * by "mask"
3444 */
3445
3446 uint32_t reg = ROM32(bios->data[offset + 1]);
3447 uint32_t mask = ROM32(bios->data[offset + 5]);
3448 uint32_t add = ROM32(bios->data[offset + 9]);
3449 uint32_t val;
3450
3451 val = bios_rd32(bios, reg);
3452 val = (val & mask) | ((val + add) & ~mask);
3453
3454 if (!iexec->execute)
3455 return 13;
3456
3457 bios_wr32(bios, reg, val);
3458 return 13;
3459 }
3460
3461 static int
3462 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3463 {
3464 /*
3465 * INIT_AUXCH opcode: 0x98 ('')
3466 *
3467 * offset (8 bit): opcode
3468 * offset + 1 (32 bit): address
3469 * offset + 5 (8 bit): count
3470 * offset + 6 (8 bit): mask 0
3471 * offset + 7 (8 bit): data 0
3472 * ...
3473 *
3474 */
3475
3476 struct drm_device *dev = bios->dev;
3477 struct nouveau_i2c_chan *auxch;
3478 uint32_t addr = ROM32(bios->data[offset + 1]);
3479 uint8_t count = bios->data[offset + 5];
3480 int len = 6 + count * 2;
3481 int ret, i;
3482
3483 if (!bios->display.output) {
3484 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3485 return len;
3486 }
3487
3488 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3489 if (!auxch) {
3490 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3491 bios->display.output->i2c_index);
3492 return len;
3493 }
3494
3495 if (!iexec->execute)
3496 return len;
3497
3498 offset += 6;
3499 for (i = 0; i < count; i++, offset += 2) {
3500 uint8_t data;
3501
3502 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3503 if (ret) {
3504 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3505 return len;
3506 }
3507
3508 data &= bios->data[offset + 0];
3509 data |= bios->data[offset + 1];
3510
3511 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3512 if (ret) {
3513 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3514 return len;
3515 }
3516 }
3517
3518 return len;
3519 }
3520
3521 static int
3522 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3523 {
3524 /*
3525 * INIT_ZM_AUXCH opcode: 0x99 ('')
3526 *
3527 * offset (8 bit): opcode
3528 * offset + 1 (32 bit): address
3529 * offset + 5 (8 bit): count
3530 * offset + 6 (8 bit): data 0
3531 * ...
3532 *
3533 */
3534
3535 struct drm_device *dev = bios->dev;
3536 struct nouveau_i2c_chan *auxch;
3537 uint32_t addr = ROM32(bios->data[offset + 1]);
3538 uint8_t count = bios->data[offset + 5];
3539 int len = 6 + count;
3540 int ret, i;
3541
3542 if (!bios->display.output) {
3543 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3544 return len;
3545 }
3546
3547 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3548 if (!auxch) {
3549 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3550 bios->display.output->i2c_index);
3551 return len;
3552 }
3553
3554 if (!iexec->execute)
3555 return len;
3556
3557 offset += 6;
3558 for (i = 0; i < count; i++, offset++) {
3559 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3560 if (ret) {
3561 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3562 return len;
3563 }
3564 }
3565
3566 return len;
3567 }
3568
3569 static int
3570 init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3571 {
3572 /*
3573 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3574 *
3575 * offset (8 bit): opcode
3576 * offset + 1 (8 bit): DCB I2C table entry index
3577 * offset + 2 (8 bit): I2C slave address
3578 * offset + 3 (16 bit): I2C register
3579 * offset + 5 (8 bit): mask
3580 * offset + 6 (8 bit): data
3581 *
3582 * Read the register given by "I2C register" on the device addressed
3583 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3584 * entry index". Compare the result AND "mask" to "data".
3585 * If they're not equal, skip subsequent opcodes until condition is
3586 * inverted (INIT_NOT), or we hit INIT_RESUME
3587 */
3588
3589 uint8_t i2c_index = bios->data[offset + 1];
3590 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3591 uint8_t reglo = bios->data[offset + 3];
3592 uint8_t reghi = bios->data[offset + 4];
3593 uint8_t mask = bios->data[offset + 5];
3594 uint8_t data = bios->data[offset + 6];
3595 struct nouveau_i2c_chan *chan;
3596 uint8_t buf0[2] = { reghi, reglo };
3597 uint8_t buf1[1];
3598 struct i2c_msg msg[2] = {
3599 { i2c_address, 0, 1, buf0 },
3600 { i2c_address, I2C_M_RD, 1, buf1 },
3601 };
3602 int ret;
3603
3604 /* no execute check by design */
3605
3606 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3607 offset, i2c_index, i2c_address);
3608
3609 chan = init_i2c_device_find(bios->dev, i2c_index);
3610 if (!chan)
3611 return -ENODEV;
3612
3613
3614 ret = i2c_transfer(&chan->adapter, msg, 2);
3615 if (ret < 0) {
3616 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3617 "Mask: 0x%02X, Data: 0x%02X\n",
3618 offset, reghi, reglo, mask, data);
3619 iexec->execute = 0;
3620 return 7;
3621 }
3622
3623 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3624 "Mask: 0x%02X, Data: 0x%02X\n",
3625 offset, reghi, reglo, buf1[0], mask, data);
3626
3627 iexec->execute = ((buf1[0] & mask) == data);
3628
3629 return 7;
3630 }
3631
3632 static struct init_tbl_entry itbl_entry[] = {
3633 /* command name , id , length , offset , mult , command handler */
3634 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3635 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3636 { "INIT_REPEAT" , 0x33, init_repeat },
3637 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3638 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3639 { "INIT_COPY" , 0x37, init_copy },
3640 { "INIT_NOT" , 0x38, init_not },
3641 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3642 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3643 { "INIT_OP_3B" , 0x3B, init_op_3b },
3644 { "INIT_OP_3C" , 0x3C, init_op_3c },
3645 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3646 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3647 { "INIT_PLL2" , 0x4B, init_pll2 },
3648 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3649 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3650 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3651 { "INIT_TMDS" , 0x4F, init_tmds },
3652 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3653 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3654 { "INIT_CR" , 0x52, init_cr },
3655 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3656 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3657 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3658 { "INIT_LTIME" , 0x57, init_ltime },
3659 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3660 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3661 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3662 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3663 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3664 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3665 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3666 { "INIT_RESET" , 0x65, init_reset },
3667 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3668 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3669 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3670 { "INIT_IO" , 0x69, init_io },
3671 { "INIT_SUB" , 0x6B, init_sub },
3672 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3673 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3674 { "INIT_MACRO" , 0x6F, init_macro },
3675 { "INIT_DONE" , 0x71, init_done },
3676 { "INIT_RESUME" , 0x72, init_resume },
3677 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3678 { "INIT_TIME" , 0x74, init_time },
3679 { "INIT_CONDITION" , 0x75, init_condition },
3680 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3681 { "INIT_INDEX_IO" , 0x78, init_index_io },
3682 { "INIT_PLL" , 0x79, init_pll },
3683 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3684 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3685 { "INIT_8C" , 0x8C, init_8c },
3686 { "INIT_8D" , 0x8D, init_8d },
3687 { "INIT_GPIO" , 0x8E, init_gpio },
3688 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3689 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3690 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3691 { "INIT_RESERVED" , 0x92, init_reserved },
3692 { "INIT_96" , 0x96, init_96 },
3693 { "INIT_97" , 0x97, init_97 },
3694 { "INIT_AUXCH" , 0x98, init_auxch },
3695 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3696 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3697 { NULL , 0 , NULL }
3698 };
3699
3700 #define MAX_TABLE_OPS 1000
3701
3702 static int
3703 parse_init_table(struct nvbios *bios, unsigned int offset,
3704 struct init_exec *iexec)
3705 {
3706 /*
3707 * Parses all commands in an init table.
3708 *
3709 * We start out executing all commands found in the init table. Some
3710 * opcodes may change the status of iexec->execute to SKIP, which will
3711 * cause the following opcodes to perform no operation until the value
3712 * is changed back to EXECUTE.
3713 */
3714
3715 int count = 0, i, ret;
3716 uint8_t id;
3717
3718 /*
3719 * Loop until INIT_DONE causes us to break out of the loop
3720 * (or until offset > bios length just in case... )
3721 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3722 */
3723 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3724 id = bios->data[offset];
3725
3726 /* Find matching id in itbl_entry */
3727 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3728 ;
3729
3730 if (!itbl_entry[i].name) {
3731 NV_ERROR(bios->dev,
3732 "0x%04X: Init table command not found: "
3733 "0x%02X\n", offset, id);
3734 return -ENOENT;
3735 }
3736
3737 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3738 itbl_entry[i].id, itbl_entry[i].name);
3739
3740 /* execute eventual command handler */
3741 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3742 if (ret < 0) {
3743 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3744 "table opcode: %s %d\n", offset,
3745 itbl_entry[i].name, ret);
3746 }
3747
3748 if (ret <= 0)
3749 break;
3750
3751 /*
3752 * Add the offset of the current command including all data
3753 * of that command. The offset will then be pointing on the
3754 * next op code.
3755 */
3756 offset += ret;
3757 }
3758
3759 if (offset >= bios->length)
3760 NV_WARN(bios->dev,
3761 "Offset 0x%04X greater than known bios image length. "
3762 "Corrupt image?\n", offset);
3763 if (count >= MAX_TABLE_OPS)
3764 NV_WARN(bios->dev,
3765 "More than %d opcodes to a table is unlikely, "
3766 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3767
3768 return 0;
3769 }
3770
3771 static void
3772 parse_init_tables(struct nvbios *bios)
3773 {
3774 /* Loops and calls parse_init_table() for each present table. */
3775
3776 int i = 0;
3777 uint16_t table;
3778 struct init_exec iexec = {true, false};
3779
3780 if (bios->old_style_init) {
3781 if (bios->init_script_tbls_ptr)
3782 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3783 if (bios->extra_init_script_tbl_ptr)
3784 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3785
3786 return;
3787 }
3788
3789 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3790 NV_INFO(bios->dev,
3791 "Parsing VBIOS init table %d at offset 0x%04X\n",
3792 i / 2, table);
3793 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3794
3795 parse_init_table(bios, table, &iexec);
3796 i += 2;
3797 }
3798 }
3799
3800 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3801 {
3802 int compare_record_len, i = 0;
3803 uint16_t compareclk, scriptptr = 0;
3804
3805 if (bios->major_version < 5) /* pre BIT */
3806 compare_record_len = 3;
3807 else
3808 compare_record_len = 4;
3809
3810 do {
3811 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3812 if (pxclk >= compareclk * 10) {
3813 if (bios->major_version < 5) {
3814 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3815 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3816 } else
3817 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3818 break;
3819 }
3820 i++;
3821 } while (compareclk);
3822
3823 return scriptptr;
3824 }
3825
3826 static void
3827 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3828 struct dcb_entry *dcbent, int head, bool dl)
3829 {
3830 struct drm_nouveau_private *dev_priv = dev->dev_private;
3831 struct nvbios *bios = &dev_priv->vbios;
3832 struct init_exec iexec = {true, false};
3833
3834 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3835 scriptptr);
3836 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3837 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3838 /* note: if dcb entries have been merged, index may be misleading */
3839 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3840 parse_init_table(bios, scriptptr, &iexec);
3841
3842 nv04_dfp_bind_head(dev, dcbent, head, dl);
3843 }
3844
3845 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3846 {
3847 struct drm_nouveau_private *dev_priv = dev->dev_private;
3848 struct nvbios *bios = &dev_priv->vbios;
3849 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3850 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3851
3852 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3853 return -EINVAL;
3854
3855 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3856
3857 if (script == LVDS_PANEL_OFF) {
3858 /* off-on delay in ms */
3859 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3860 }
3861 #ifdef __powerpc__
3862 /* Powerbook specific quirks */
3863 if (script == LVDS_RESET &&
3864 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3865 dev->pci_device == 0x0329))
3866 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3867 #endif
3868
3869 return 0;
3870 }
3871
3872 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3873 {
3874 /*
3875 * The BIT LVDS table's header has the information to setup the
3876 * necessary registers. Following the standard 4 byte header are:
3877 * A bitmask byte and a dual-link transition pxclk value for use in
3878 * selecting the init script when not using straps; 4 script pointers
3879 * for panel power, selected by output and on/off; and 8 table pointers
3880 * for panel init, the needed one determined by output, and bits in the
3881 * conf byte. These tables are similar to the TMDS tables, consisting
3882 * of a list of pxclks and script pointers.
3883 */
3884 struct drm_nouveau_private *dev_priv = dev->dev_private;
3885 struct nvbios *bios = &dev_priv->vbios;
3886 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3887 uint16_t scriptptr = 0, clktable;
3888
3889 /*
3890 * For now we assume version 3.0 table - g80 support will need some
3891 * changes
3892 */
3893
3894 switch (script) {
3895 case LVDS_INIT:
3896 return -ENOSYS;
3897 case LVDS_BACKLIGHT_ON:
3898 case LVDS_PANEL_ON:
3899 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3900 break;
3901 case LVDS_BACKLIGHT_OFF:
3902 case LVDS_PANEL_OFF:
3903 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3904 break;
3905 case LVDS_RESET:
3906 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3907 if (dcbent->or == 4)
3908 clktable += 8;
3909
3910 if (dcbent->lvdsconf.use_straps_for_mode) {
3911 if (bios->fp.dual_link)
3912 clktable += 4;
3913 if (bios->fp.if_is_24bit)
3914 clktable += 2;
3915 } else {
3916 /* using EDID */
3917 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3918
3919 if (bios->fp.dual_link) {
3920 clktable += 4;
3921 cmpval_24bit <<= 1;
3922 }
3923
3924 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3925 clktable += 2;
3926 }
3927
3928 clktable = ROM16(bios->data[clktable]);
3929 if (!clktable) {
3930 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3931 return -ENOENT;
3932 }
3933 scriptptr = clkcmptable(bios, clktable, pxclk);
3934 }
3935
3936 if (!scriptptr) {
3937 NV_ERROR(dev, "LVDS output init script not found\n");
3938 return -ENOENT;
3939 }
3940 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3941
3942 return 0;
3943 }
3944
3945 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3946 {
3947 /*
3948 * LVDS operations are multiplexed in an effort to present a single API
3949 * which works with two vastly differing underlying structures.
3950 * This acts as the demux
3951 */
3952
3953 struct drm_nouveau_private *dev_priv = dev->dev_private;
3954 struct nvbios *bios = &dev_priv->vbios;
3955 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3956 uint32_t sel_clk_binding, sel_clk;
3957 int ret;
3958
3959 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3960 (lvds_ver >= 0x30 && script == LVDS_INIT))
3961 return 0;
3962
3963 if (!bios->fp.lvds_init_run) {
3964 bios->fp.lvds_init_run = true;
3965 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3966 }
3967
3968 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3969 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3970 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3971 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3972
3973 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3974
3975 /* don't let script change pll->head binding */
3976 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3977
3978 if (lvds_ver < 0x30)
3979 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3980 else
3981 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3982
3983 bios->fp.last_script_invoc = (script << 1 | head);
3984
3985 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3986 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3987 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3988 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3989
3990 return ret;
3991 }
3992
3993 struct lvdstableheader {
3994 uint8_t lvds_ver, headerlen, recordlen;
3995 };
3996
3997 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3998 {
3999 /*
4000 * BMP version (0xa) LVDS table has a simple header of version and
4001 * record length. The BIT LVDS table has the typical BIT table header:
4002 * version byte, header length byte, record length byte, and a byte for
4003 * the maximum number of records that can be held in the table.
4004 */
4005
4006 uint8_t lvds_ver, headerlen, recordlen;
4007
4008 memset(lth, 0, sizeof(struct lvdstableheader));
4009
4010 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
4011 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
4012 return -EINVAL;
4013 }
4014
4015 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4016
4017 switch (lvds_ver) {
4018 case 0x0a: /* pre NV40 */
4019 headerlen = 2;
4020 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4021 break;
4022 case 0x30: /* NV4x */
4023 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4024 if (headerlen < 0x1f) {
4025 NV_ERROR(dev, "LVDS table header not understood\n");
4026 return -EINVAL;
4027 }
4028 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4029 break;
4030 case 0x40: /* G80/G90 */
4031 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4032 if (headerlen < 0x7) {
4033 NV_ERROR(dev, "LVDS table header not understood\n");
4034 return -EINVAL;
4035 }
4036 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4037 break;
4038 default:
4039 NV_ERROR(dev,
4040 "LVDS table revision %d.%d not currently supported\n",
4041 lvds_ver >> 4, lvds_ver & 0xf);
4042 return -ENOSYS;
4043 }
4044
4045 lth->lvds_ver = lvds_ver;
4046 lth->headerlen = headerlen;
4047 lth->recordlen = recordlen;
4048
4049 return 0;
4050 }
4051
4052 static int
4053 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
4054 {
4055 struct drm_nouveau_private *dev_priv = dev->dev_private;
4056
4057 /*
4058 * The fp strap is normally dictated by the "User Strap" in
4059 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4060 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4061 * by the PCI subsystem ID during POST, but not before the previous user
4062 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4063 * read and used instead
4064 */
4065
4066 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4067 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4068
4069 if (dev_priv->card_type >= NV_50)
4070 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4071 else
4072 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4073 }
4074
4075 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4076 {
4077 uint8_t *fptable;
4078 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4079 int ret, ofs, fpstrapping;
4080 struct lvdstableheader lth;
4081
4082 if (bios->fp.fptablepointer == 0x0) {
4083 /* Apple cards don't have the fp table; the laptops use DDC */
4084 /* The table is also missing on some x86 IGPs */
4085 #ifndef __powerpc__
4086 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4087 #endif
4088 bios->digital_min_front_porch = 0x4b;
4089 return 0;
4090 }
4091
4092 fptable = &bios->data[bios->fp.fptablepointer];
4093 fptable_ver = fptable[0];
4094
4095 switch (fptable_ver) {
4096 /*
4097 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4098 * version field, and miss one of the spread spectrum/PWM bytes.
4099 * This could affect early GF2Go parts (not seen any appropriate ROMs
4100 * though). Here we assume that a version of 0x05 matches this case
4101 * (combining with a BMP version check would be better), as the
4102 * common case for the panel type field is 0x0005, and that is in
4103 * fact what we are reading the first byte of.
4104 */
4105 case 0x05: /* some NV10, 11, 15, 16 */
4106 recordlen = 42;
4107 ofs = -1;
4108 break;
4109 case 0x10: /* some NV15/16, and NV11+ */
4110 recordlen = 44;
4111 ofs = 0;
4112 break;
4113 case 0x20: /* NV40+ */
4114 headerlen = fptable[1];
4115 recordlen = fptable[2];
4116 fpentries = fptable[3];
4117 /*
4118 * fptable[4] is the minimum
4119 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4120 */
4121 bios->digital_min_front_porch = fptable[4];
4122 ofs = -7;
4123 break;
4124 default:
4125 NV_ERROR(dev,
4126 "FP table revision %d.%d not currently supported\n",
4127 fptable_ver >> 4, fptable_ver & 0xf);
4128 return -ENOSYS;
4129 }
4130
4131 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4132 return 0;
4133
4134 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4135 if (ret)
4136 return ret;
4137
4138 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4139 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4140 lth.headerlen + 1;
4141 bios->fp.xlatwidth = lth.recordlen;
4142 }
4143 if (bios->fp.fpxlatetableptr == 0x0) {
4144 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4145 return -EINVAL;
4146 }
4147
4148 fpstrapping = get_fp_strap(dev, bios);
4149
4150 fpindex = bios->data[bios->fp.fpxlatetableptr +
4151 fpstrapping * bios->fp.xlatwidth];
4152
4153 if (fpindex > fpentries) {
4154 NV_ERROR(dev, "Bad flat panel table index\n");
4155 return -ENOENT;
4156 }
4157
4158 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4159 if (lth.lvds_ver > 0x10)
4160 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
4161
4162 /*
4163 * If either the strap or xlated fpindex value are 0xf there is no
4164 * panel using a strap-derived bios mode present. this condition
4165 * includes, but is different from, the DDC panel indicator above
4166 */
4167 if (fpstrapping == 0xf || fpindex == 0xf)
4168 return 0;
4169
4170 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4171 recordlen * fpindex + ofs;
4172
4173 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4174 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4175 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4176 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4177
4178 return 0;
4179 }
4180
4181 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4182 {
4183 struct drm_nouveau_private *dev_priv = dev->dev_private;
4184 struct nvbios *bios = &dev_priv->vbios;
4185 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4186
4187 if (!mode) /* just checking whether we can produce a mode */
4188 return bios->fp.mode_ptr;
4189
4190 memset(mode, 0, sizeof(struct drm_display_mode));
4191 /*
4192 * For version 1.0 (version in byte 0):
4193 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4194 * single/dual link, and type (TFT etc.)
4195 * bytes 3-6 are bits per colour in RGBX
4196 */
4197 mode->clock = ROM16(mode_entry[7]) * 10;
4198 /* bytes 9-10 is HActive */
4199 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4200 /*
4201 * bytes 13-14 is HValid Start
4202 * bytes 15-16 is HValid End
4203 */
4204 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4205 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4206 mode->htotal = ROM16(mode_entry[21]) + 1;
4207 /* bytes 23-24, 27-30 similarly, but vertical */
4208 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4209 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4210 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4211 mode->vtotal = ROM16(mode_entry[35]) + 1;
4212 mode->flags |= (mode_entry[37] & 0x10) ?
4213 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4214 mode->flags |= (mode_entry[37] & 0x1) ?
4215 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4216 /*
4217 * bytes 38-39 relate to spread spectrum settings
4218 * bytes 40-43 are something to do with PWM
4219 */
4220
4221 mode->status = MODE_OK;
4222 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4223 drm_mode_set_name(mode);
4224 return bios->fp.mode_ptr;
4225 }
4226
4227 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4228 {
4229 /*
4230 * The LVDS table header is (mostly) described in
4231 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4232 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4233 * straps are not being used for the panel, this specifies the frequency
4234 * at which modes should be set up in the dual link style.
4235 *
4236 * Following the header, the BMP (ver 0xa) table has several records,
4237 * indexed by a separate xlat table, indexed in turn by the fp strap in
4238 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4239 * numbers for use by INIT_SUB which controlled panel init and power,
4240 * and finally a dword of ms to sleep between power off and on
4241 * operations.
4242 *
4243 * In the BIT versions, the table following the header serves as an
4244 * integrated config and xlat table: the records in the table are
4245 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4246 * two bytes - the first as a config byte, the second for indexing the
4247 * fp mode table pointed to by the BIT 'D' table
4248 *
4249 * DDC is not used until after card init, so selecting the correct table
4250 * entry and setting the dual link flag for EDID equipped panels,
4251 * requiring tests against the native-mode pixel clock, cannot be done
4252 * until later, when this function should be called with non-zero pxclk
4253 */
4254 struct drm_nouveau_private *dev_priv = dev->dev_private;
4255 struct nvbios *bios = &dev_priv->vbios;
4256 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4257 struct lvdstableheader lth;
4258 uint16_t lvdsofs;
4259 int ret, chip_version = bios->chip_version;
4260
4261 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4262 if (ret)
4263 return ret;
4264
4265 switch (lth.lvds_ver) {
4266 case 0x0a: /* pre NV40 */
4267 lvdsmanufacturerindex = bios->data[
4268 bios->fp.fpxlatemanufacturertableptr +
4269 fpstrapping];
4270
4271 /* we're done if this isn't the EDID panel case */
4272 if (!pxclk)
4273 break;
4274
4275 if (chip_version < 0x25) {
4276 /* nv17 behaviour
4277 *
4278 * It seems the old style lvds script pointer is reused
4279 * to select 18/24 bit colour depth for EDID panels.
4280 */
4281 lvdsmanufacturerindex =
4282 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4283 2 : 0;
4284 if (pxclk >= bios->fp.duallink_transition_clk)
4285 lvdsmanufacturerindex++;
4286 } else if (chip_version < 0x30) {
4287 /* nv28 behaviour (off-chip encoder)
4288 *
4289 * nv28 does a complex dance of first using byte 121 of
4290 * the EDID to choose the lvdsmanufacturerindex, then
4291 * later attempting to match the EDID manufacturer and
4292 * product IDs in a table (signature 'pidt' (panel id
4293 * table?)), setting an lvdsmanufacturerindex of 0 and
4294 * an fp strap of the match index (or 0xf if none)
4295 */
4296 lvdsmanufacturerindex = 0;
4297 } else {
4298 /* nv31, nv34 behaviour */
4299 lvdsmanufacturerindex = 0;
4300 if (pxclk >= bios->fp.duallink_transition_clk)
4301 lvdsmanufacturerindex = 2;
4302 if (pxclk >= 140000)
4303 lvdsmanufacturerindex = 3;
4304 }
4305
4306 /*
4307 * nvidia set the high nibble of (cr57=f, cr58) to
4308 * lvdsmanufacturerindex in this case; we don't
4309 */
4310 break;
4311 case 0x30: /* NV4x */
4312 case 0x40: /* G80/G90 */
4313 lvdsmanufacturerindex = fpstrapping;
4314 break;
4315 default:
4316 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4317 return -ENOSYS;
4318 }
4319
4320 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4321 switch (lth.lvds_ver) {
4322 case 0x0a:
4323 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4324 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4325 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4326 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4327 *if_is_24bit = bios->data[lvdsofs] & 16;
4328 break;
4329 case 0x30:
4330 case 0x40:
4331 /*
4332 * No sign of the "power off for reset" or "reset for panel
4333 * on" bits, but it's safer to assume we should
4334 */
4335 bios->fp.power_off_for_reset = true;
4336 bios->fp.reset_after_pclk_change = true;
4337
4338 /*
4339 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4340 * over-written, and if_is_24bit isn't used
4341 */
4342 bios->fp.dual_link = bios->data[lvdsofs] & 1;
4343 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4344 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4345 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4346 break;
4347 }
4348
4349 /* Dell Latitude D620 reports a too-high value for the dual-link
4350 * transition freq, causing us to program the panel incorrectly.
4351 *
4352 * It doesn't appear the VBIOS actually uses its transition freq
4353 * (90000kHz), instead it uses the "Number of LVDS channels" field
4354 * out of the panel ID structure (http://www.spwg.org/).
4355 *
4356 * For the moment, a quirk will do :)
4357 */
4358 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
4359 bios->fp.duallink_transition_clk = 80000;
4360
4361 /* set dual_link flag for EDID case */
4362 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4363 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4364
4365 *dl = bios->fp.dual_link;
4366
4367 return 0;
4368 }
4369
4370 static uint8_t *
4371 bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
4372 uint16_t record, int record_len, int record_nr,
4373 bool match_link)
4374 {
4375 struct drm_nouveau_private *dev_priv = dev->dev_private;
4376 struct nvbios *bios = &dev_priv->vbios;
4377 uint32_t entry;
4378 uint16_t table;
4379 int i, v;
4380
4381 switch (dcbent->type) {
4382 case OUTPUT_TMDS:
4383 case OUTPUT_LVDS:
4384 case OUTPUT_DP:
4385 break;
4386 default:
4387 match_link = false;
4388 break;
4389 }
4390
4391 for (i = 0; i < record_nr; i++, record += record_len) {
4392 table = ROM16(bios->data[record]);
4393 if (!table)
4394 continue;
4395 entry = ROM32(bios->data[table]);
4396
4397 if (match_link) {
4398 v = (entry & 0x00c00000) >> 22;
4399 if (!(v & dcbent->sorconf.link))
4400 continue;
4401 }
4402
4403 v = (entry & 0x000f0000) >> 16;
4404 if (!(v & dcbent->or))
4405 continue;
4406
4407 v = (entry & 0x000000f0) >> 4;
4408 if (v != dcbent->location)
4409 continue;
4410
4411 v = (entry & 0x0000000f);
4412 if (v != dcbent->type)
4413 continue;
4414
4415 return &bios->data[table];
4416 }
4417
4418 return NULL;
4419 }
4420
4421 void *
4422 nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
4423 int *length)
4424 {
4425 struct drm_nouveau_private *dev_priv = dev->dev_private;
4426 struct nvbios *bios = &dev_priv->vbios;
4427 uint8_t *table;
4428
4429 if (!bios->display.dp_table_ptr) {
4430 NV_ERROR(dev, "No pointer to DisplayPort table\n");
4431 return NULL;
4432 }
4433 table = &bios->data[bios->display.dp_table_ptr];
4434
4435 if (table[0] != 0x20 && table[0] != 0x21) {
4436 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
4437 table[0]);
4438 return NULL;
4439 }
4440
4441 *length = table[4];
4442 return bios_output_config_match(dev, dcbent,
4443 bios->display.dp_table_ptr + table[1],
4444 table[2], table[3], table[0] >= 0x21);
4445 }
4446
4447 int
4448 nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4449 uint32_t sub, int pxclk)
4450 {
4451 /*
4452 * The display script table is located by the BIT 'U' table.
4453 *
4454 * It contains an array of pointers to various tables describing
4455 * a particular output type. The first 32-bits of the output
4456 * tables contains similar information to a DCB entry, and is
4457 * used to decide whether that particular table is suitable for
4458 * the output you want to access.
4459 *
4460 * The "record header length" field here seems to indicate the
4461 * offset of the first configuration entry in the output tables.
4462 * This is 10 on most cards I've seen, but 12 has been witnessed
4463 * on DP cards, and there's another script pointer within the
4464 * header.
4465 *
4466 * offset + 0 ( 8 bits): version
4467 * offset + 1 ( 8 bits): header length
4468 * offset + 2 ( 8 bits): record length
4469 * offset + 3 ( 8 bits): number of records
4470 * offset + 4 ( 8 bits): record header length
4471 * offset + 5 (16 bits): pointer to first output script table
4472 */
4473
4474 struct drm_nouveau_private *dev_priv = dev->dev_private;
4475 struct nvbios *bios = &dev_priv->vbios;
4476 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4477 uint8_t *otable = NULL;
4478 uint16_t script;
4479 int i = 0;
4480
4481 if (!bios->display.script_table_ptr) {
4482 NV_ERROR(dev, "No pointer to output script table\n");
4483 return 1;
4484 }
4485
4486 /*
4487 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4488 * so until they are, we really don't need to care.
4489 */
4490 if (table[0] < 0x20)
4491 return 1;
4492
4493 if (table[0] != 0x20 && table[0] != 0x21) {
4494 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4495 table[0]);
4496 return 1;
4497 }
4498
4499 /*
4500 * The output script tables describing a particular output type
4501 * look as follows:
4502 *
4503 * offset + 0 (32 bits): output this table matches (hash of DCB)
4504 * offset + 4 ( 8 bits): unknown
4505 * offset + 5 ( 8 bits): number of configurations
4506 * offset + 6 (16 bits): pointer to some script
4507 * offset + 8 (16 bits): pointer to some script
4508 *
4509 * headerlen == 10
4510 * offset + 10 : configuration 0
4511 *
4512 * headerlen == 12
4513 * offset + 10 : pointer to some script
4514 * offset + 12 : configuration 0
4515 *
4516 * Each config entry is as follows:
4517 *
4518 * offset + 0 (16 bits): unknown, assumed to be a match value
4519 * offset + 2 (16 bits): pointer to script table (clock set?)
4520 * offset + 4 (16 bits): pointer to script table (reset?)
4521 *
4522 * There doesn't appear to be a count value to say how many
4523 * entries exist in each script table, instead, a 0 value in
4524 * the first 16-bit word seems to indicate both the end of the
4525 * list and the default entry. The second 16-bit word in the
4526 * script tables is a pointer to the script to execute.
4527 */
4528
4529 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
4530 dcbent->type, dcbent->location, dcbent->or);
4531 otable = bios_output_config_match(dev, dcbent, table[1] +
4532 bios->display.script_table_ptr,
4533 table[2], table[3], table[0] >= 0x21);
4534 if (!otable) {
4535 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4536 return 1;
4537 }
4538
4539 if (pxclk < -2 || pxclk > 0) {
4540 /* Try to find matching script table entry */
4541 for (i = 0; i < otable[5]; i++) {
4542 if (ROM16(otable[table[4] + i*6]) == sub)
4543 break;
4544 }
4545
4546 if (i == otable[5]) {
4547 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4548 "using first\n",
4549 sub, dcbent->type, dcbent->or);
4550 i = 0;
4551 }
4552 }
4553
4554 if (pxclk == 0) {
4555 script = ROM16(otable[6]);
4556 if (!script) {
4557 NV_DEBUG_KMS(dev, "output script 0 not found\n");
4558 return 1;
4559 }
4560
4561 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4562 nouveau_bios_run_init_table(dev, script, dcbent);
4563 } else
4564 if (pxclk == -1) {
4565 script = ROM16(otable[8]);
4566 if (!script) {
4567 NV_DEBUG_KMS(dev, "output script 1 not found\n");
4568 return 1;
4569 }
4570
4571 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4572 nouveau_bios_run_init_table(dev, script, dcbent);
4573 } else
4574 if (pxclk == -2) {
4575 if (table[4] >= 12)
4576 script = ROM16(otable[10]);
4577 else
4578 script = 0;
4579 if (!script) {
4580 NV_DEBUG_KMS(dev, "output script 2 not found\n");
4581 return 1;
4582 }
4583
4584 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4585 nouveau_bios_run_init_table(dev, script, dcbent);
4586 } else
4587 if (pxclk > 0) {
4588 script = ROM16(otable[table[4] + i*6 + 2]);
4589 if (script)
4590 script = clkcmptable(bios, script, pxclk);
4591 if (!script) {
4592 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4593 return 1;
4594 }
4595
4596 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4597 nouveau_bios_run_init_table(dev, script, dcbent);
4598 } else
4599 if (pxclk < 0) {
4600 script = ROM16(otable[table[4] + i*6 + 4]);
4601 if (script)
4602 script = clkcmptable(bios, script, -pxclk);
4603 if (!script) {
4604 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
4605 return 1;
4606 }
4607
4608 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4609 nouveau_bios_run_init_table(dev, script, dcbent);
4610 }
4611
4612 return 0;
4613 }
4614
4615
4616 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4617 {
4618 /*
4619 * the pxclk parameter is in kHz
4620 *
4621 * This runs the TMDS regs setting code found on BIT bios cards
4622 *
4623 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4624 * ffs(or) == 3, use the second.
4625 */
4626
4627 struct drm_nouveau_private *dev_priv = dev->dev_private;
4628 struct nvbios *bios = &dev_priv->vbios;
4629 int cv = bios->chip_version;
4630 uint16_t clktable = 0, scriptptr;
4631 uint32_t sel_clk_binding, sel_clk;
4632
4633 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4634 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4635 dcbent->location != DCB_LOC_ON_CHIP)
4636 return 0;
4637
4638 switch (ffs(dcbent->or)) {
4639 case 1:
4640 clktable = bios->tmds.output0_script_ptr;
4641 break;
4642 case 2:
4643 case 3:
4644 clktable = bios->tmds.output1_script_ptr;
4645 break;
4646 }
4647
4648 if (!clktable) {
4649 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4650 return -EINVAL;
4651 }
4652
4653 scriptptr = clkcmptable(bios, clktable, pxclk);
4654
4655 if (!scriptptr) {
4656 NV_ERROR(dev, "TMDS output init script not found\n");
4657 return -ENOENT;
4658 }
4659
4660 /* don't let script change pll->head binding */
4661 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4662 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4663 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4664 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4665
4666 return 0;
4667 }
4668
4669 struct pll_mapping {
4670 u8 type;
4671 u32 reg;
4672 };
4673
4674 static struct pll_mapping nv04_pll_mapping[] = {
4675 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4676 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4677 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4678 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4679 {}
4680 };
4681
4682 static struct pll_mapping nv40_pll_mapping[] = {
4683 { PLL_CORE , 0x004000 },
4684 { PLL_MEMORY, 0x004020 },
4685 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4686 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4687 {}
4688 };
4689
4690 static struct pll_mapping nv50_pll_mapping[] = {
4691 { PLL_CORE , 0x004028 },
4692 { PLL_SHADER, 0x004020 },
4693 { PLL_UNK03 , 0x004000 },
4694 { PLL_MEMORY, 0x004008 },
4695 { PLL_UNK40 , 0x00e810 },
4696 { PLL_UNK41 , 0x00e818 },
4697 { PLL_UNK42 , 0x00e824 },
4698 { PLL_VPLL0 , 0x614100 },
4699 { PLL_VPLL1 , 0x614900 },
4700 {}
4701 };
4702
4703 static struct pll_mapping nv84_pll_mapping[] = {
4704 { PLL_CORE , 0x004028 },
4705 { PLL_SHADER, 0x004020 },
4706 { PLL_MEMORY, 0x004008 },
4707 { PLL_UNK05 , 0x004030 },
4708 { PLL_UNK41 , 0x00e818 },
4709 { PLL_VPLL0 , 0x614100 },
4710 { PLL_VPLL1 , 0x614900 },
4711 {}
4712 };
4713
4714 u32
4715 get_pll_register(struct drm_device *dev, enum pll_types type)
4716 {
4717 struct drm_nouveau_private *dev_priv = dev->dev_private;
4718 struct nvbios *bios = &dev_priv->vbios;
4719 struct pll_mapping *map;
4720 int i;
4721
4722 if (dev_priv->card_type < NV_40)
4723 map = nv04_pll_mapping;
4724 else
4725 if (dev_priv->card_type < NV_50)
4726 map = nv40_pll_mapping;
4727 else {
4728 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4729
4730 if (plim[0] >= 0x30) {
4731 u8 *entry = plim + plim[1];
4732 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4733 if (entry[0] == type)
4734 return ROM32(entry[3]);
4735 }
4736
4737 return 0;
4738 }
4739
4740 if (dev_priv->chipset == 0x50)
4741 map = nv50_pll_mapping;
4742 else
4743 map = nv84_pll_mapping;
4744 }
4745
4746 while (map->reg) {
4747 if (map->type == type)
4748 return map->reg;
4749 map++;
4750 }
4751
4752 return 0;
4753 }
4754
4755 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4756 {
4757 /*
4758 * PLL limits table
4759 *
4760 * Version 0x10: NV30, NV31
4761 * One byte header (version), one record of 24 bytes
4762 * Version 0x11: NV36 - Not implemented
4763 * Seems to have same record style as 0x10, but 3 records rather than 1
4764 * Version 0x20: Found on Geforce 6 cards
4765 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4766 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4767 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4768 * length in general, some (integrated) have an extra configuration byte
4769 * Version 0x30: Found on Geforce 8, separates the register mapping
4770 * from the limits tables.
4771 */
4772
4773 struct drm_nouveau_private *dev_priv = dev->dev_private;
4774 struct nvbios *bios = &dev_priv->vbios;
4775 int cv = bios->chip_version, pllindex = 0;
4776 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4777 uint32_t crystal_strap_mask, crystal_straps;
4778
4779 if (!bios->pll_limit_tbl_ptr) {
4780 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4781 cv >= 0x40) {
4782 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4783 return -EINVAL;
4784 }
4785 } else
4786 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4787
4788 crystal_strap_mask = 1 << 6;
4789 /* open coded dev->twoHeads test */
4790 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4791 crystal_strap_mask |= 1 << 22;
4792 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4793 crystal_strap_mask;
4794
4795 switch (pll_lim_ver) {
4796 /*
4797 * We use version 0 to indicate a pre limit table bios (single stage
4798 * pll) and load the hard coded limits instead.
4799 */
4800 case 0:
4801 break;
4802 case 0x10:
4803 case 0x11:
4804 /*
4805 * Strictly v0x11 has 3 entries, but the last two don't seem
4806 * to get used.
4807 */
4808 headerlen = 1;
4809 recordlen = 0x18;
4810 entries = 1;
4811 pllindex = 0;
4812 break;
4813 case 0x20:
4814 case 0x21:
4815 case 0x30:
4816 case 0x40:
4817 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4818 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4819 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4820 break;
4821 default:
4822 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4823 "supported\n", pll_lim_ver);
4824 return -ENOSYS;
4825 }
4826
4827 /* initialize all members to zero */
4828 memset(pll_lim, 0, sizeof(struct pll_lims));
4829
4830 /* if we were passed a type rather than a register, figure
4831 * out the register and store it
4832 */
4833 if (limit_match > PLL_MAX)
4834 pll_lim->reg = limit_match;
4835 else {
4836 pll_lim->reg = get_pll_register(dev, limit_match);
4837 if (!pll_lim->reg)
4838 return -ENOENT;
4839 }
4840
4841 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4842 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4843
4844 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4845 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4846 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4847 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4848 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4849 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4850 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4851
4852 /* these values taken from nv30/31/36 */
4853 pll_lim->vco1.min_n = 0x1;
4854 if (cv == 0x36)
4855 pll_lim->vco1.min_n = 0x5;
4856 pll_lim->vco1.max_n = 0xff;
4857 pll_lim->vco1.min_m = 0x1;
4858 pll_lim->vco1.max_m = 0xd;
4859 pll_lim->vco2.min_n = 0x4;
4860 /*
4861 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4862 * table version (apart from nv35)), N2 is compared to
4863 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4864 * save a comparison
4865 */
4866 pll_lim->vco2.max_n = 0x28;
4867 if (cv == 0x30 || cv == 0x35)
4868 /* only 5 bits available for N2 on nv30/35 */
4869 pll_lim->vco2.max_n = 0x1f;
4870 pll_lim->vco2.min_m = 0x1;
4871 pll_lim->vco2.max_m = 0x4;
4872 pll_lim->max_log2p = 0x7;
4873 pll_lim->max_usable_log2p = 0x6;
4874 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4875 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4876 uint8_t *pll_rec;
4877 int i;
4878
4879 /*
4880 * First entry is default match, if nothing better. warn if
4881 * reg field nonzero
4882 */
4883 if (ROM32(bios->data[plloffs]))
4884 NV_WARN(dev, "Default PLL limit entry has non-zero "
4885 "register field\n");
4886
4887 for (i = 1; i < entries; i++)
4888 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
4889 pllindex = i;
4890 break;
4891 }
4892
4893 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4894 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4895 "limits table", pll_lim->reg);
4896 return -ENOENT;
4897 }
4898
4899 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4900
4901 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4902 pllindex ? pll_lim->reg : 0);
4903
4904 /*
4905 * Frequencies are stored in tables in MHz, kHz are more
4906 * useful, so we convert.
4907 */
4908
4909 /* What output frequencies can each VCO generate? */
4910 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4911 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4912 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4913 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4914
4915 /* What input frequencies they accept (past the m-divider)? */
4916 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4917 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4918 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4919 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4920
4921 /* What values are accepted as multiplier and divider? */
4922 pll_lim->vco1.min_n = pll_rec[20];
4923 pll_lim->vco1.max_n = pll_rec[21];
4924 pll_lim->vco1.min_m = pll_rec[22];
4925 pll_lim->vco1.max_m = pll_rec[23];
4926 pll_lim->vco2.min_n = pll_rec[24];
4927 pll_lim->vco2.max_n = pll_rec[25];
4928 pll_lim->vco2.min_m = pll_rec[26];
4929 pll_lim->vco2.max_m = pll_rec[27];
4930
4931 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4932 if (pll_lim->max_log2p > 0x7)
4933 /* pll decoding in nv_hw.c assumes never > 7 */
4934 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4935 pll_lim->max_log2p);
4936 if (cv < 0x60)
4937 pll_lim->max_usable_log2p = 0x6;
4938 pll_lim->log2p_bias = pll_rec[30];
4939
4940 if (recordlen > 0x22)
4941 pll_lim->refclk = ROM32(pll_rec[31]);
4942
4943 if (recordlen > 0x23 && pll_rec[35])
4944 NV_WARN(dev,
4945 "Bits set in PLL configuration byte (%x)\n",
4946 pll_rec[35]);
4947
4948 /* C51 special not seen elsewhere */
4949 if (cv == 0x51 && !pll_lim->refclk) {
4950 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4951
4952 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4953 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
4954 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4955 pll_lim->refclk = 200000;
4956 else
4957 pll_lim->refclk = 25000;
4958 }
4959 }
4960 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4961 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4962 uint8_t *record = NULL;
4963 int i;
4964
4965 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4966 pll_lim->reg);
4967
4968 for (i = 0; i < entries; i++, entry += recordlen) {
4969 if (ROM32(entry[3]) == pll_lim->reg) {
4970 record = &bios->data[ROM16(entry[1])];
4971 break;
4972 }
4973 }
4974
4975 if (!record) {
4976 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4977 "limits table", pll_lim->reg);
4978 return -ENOENT;
4979 }
4980
4981 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4982 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4983 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4984 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4985 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4986 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4987 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4988 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4989 pll_lim->vco1.min_n = record[16];
4990 pll_lim->vco1.max_n = record[17];
4991 pll_lim->vco1.min_m = record[18];
4992 pll_lim->vco1.max_m = record[19];
4993 pll_lim->vco2.min_n = record[20];
4994 pll_lim->vco2.max_n = record[21];
4995 pll_lim->vco2.min_m = record[22];
4996 pll_lim->vco2.max_m = record[23];
4997 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4998 pll_lim->log2p_bias = record[27];
4999 pll_lim->refclk = ROM32(record[28]);
5000 } else if (pll_lim_ver) { /* ver 0x40 */
5001 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
5002 uint8_t *record = NULL;
5003 int i;
5004
5005 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
5006 pll_lim->reg);
5007
5008 for (i = 0; i < entries; i++, entry += recordlen) {
5009 if (ROM32(entry[3]) == pll_lim->reg) {
5010 record = &bios->data[ROM16(entry[1])];
5011 break;
5012 }
5013 }
5014
5015 if (!record) {
5016 NV_ERROR(dev, "Register 0x%08x not found in PLL "
5017 "limits table", pll_lim->reg);
5018 return -ENOENT;
5019 }
5020
5021 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
5022 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
5023 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
5024 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
5025 pll_lim->vco1.min_m = record[8];
5026 pll_lim->vco1.max_m = record[9];
5027 pll_lim->vco1.min_n = record[10];
5028 pll_lim->vco1.max_n = record[11];
5029 pll_lim->min_p = record[12];
5030 pll_lim->max_p = record[13];
5031 /* where did this go to?? */
5032 if ((entry[0] & 0xf0) == 0x80)
5033 pll_lim->refclk = 27000;
5034 else
5035 pll_lim->refclk = 100000;
5036 }
5037
5038 /*
5039 * By now any valid limit table ought to have set a max frequency for
5040 * vco1, so if it's zero it's either a pre limit table bios, or one
5041 * with an empty limit table (seen on nv18)
5042 */
5043 if (!pll_lim->vco1.maxfreq) {
5044 pll_lim->vco1.minfreq = bios->fminvco;
5045 pll_lim->vco1.maxfreq = bios->fmaxvco;
5046 pll_lim->vco1.min_inputfreq = 0;
5047 pll_lim->vco1.max_inputfreq = INT_MAX;
5048 pll_lim->vco1.min_n = 0x1;
5049 pll_lim->vco1.max_n = 0xff;
5050 pll_lim->vco1.min_m = 0x1;
5051 if (crystal_straps == 0) {
5052 /* nv05 does this, nv11 doesn't, nv10 unknown */
5053 if (cv < 0x11)
5054 pll_lim->vco1.min_m = 0x7;
5055 pll_lim->vco1.max_m = 0xd;
5056 } else {
5057 if (cv < 0x11)
5058 pll_lim->vco1.min_m = 0x8;
5059 pll_lim->vco1.max_m = 0xe;
5060 }
5061 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
5062 pll_lim->max_log2p = 4;
5063 else
5064 pll_lim->max_log2p = 5;
5065 pll_lim->max_usable_log2p = pll_lim->max_log2p;
5066 }
5067
5068 if (!pll_lim->refclk)
5069 switch (crystal_straps) {
5070 case 0:
5071 pll_lim->refclk = 13500;
5072 break;
5073 case (1 << 6):
5074 pll_lim->refclk = 14318;
5075 break;
5076 case (1 << 22):
5077 pll_lim->refclk = 27000;
5078 break;
5079 case (1 << 22 | 1 << 6):
5080 pll_lim->refclk = 25000;
5081 break;
5082 }
5083
5084 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
5085 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
5086 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
5087 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
5088 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
5089 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
5090 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
5091 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
5092 if (pll_lim->vco2.maxfreq) {
5093 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
5094 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
5095 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
5096 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
5097 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
5098 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
5099 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
5100 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
5101 }
5102 if (!pll_lim->max_p) {
5103 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
5104 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
5105 } else {
5106 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
5107 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
5108 }
5109 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
5110
5111 return 0;
5112 }
5113
5114 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
5115 {
5116 /*
5117 * offset + 0 (8 bits): Micro version
5118 * offset + 1 (8 bits): Minor version
5119 * offset + 2 (8 bits): Chip version
5120 * offset + 3 (8 bits): Major version
5121 */
5122
5123 bios->major_version = bios->data[offset + 3];
5124 bios->chip_version = bios->data[offset + 2];
5125 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5126 bios->data[offset + 3], bios->data[offset + 2],
5127 bios->data[offset + 1], bios->data[offset]);
5128 }
5129
5130 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5131 {
5132 /*
5133 * Parses the init table segment for pointers used in script execution.
5134 *
5135 * offset + 0 (16 bits): init script tables pointer
5136 * offset + 2 (16 bits): macro index table pointer
5137 * offset + 4 (16 bits): macro table pointer
5138 * offset + 6 (16 bits): condition table pointer
5139 * offset + 8 (16 bits): io condition table pointer
5140 * offset + 10 (16 bits): io flag condition table pointer
5141 * offset + 12 (16 bits): init function table pointer
5142 */
5143
5144 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5145 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5146 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5147 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5148 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5149 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5150 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5151 }
5152
5153 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5154 {
5155 /*
5156 * Parses the load detect values for g80 cards.
5157 *
5158 * offset + 0 (16 bits): loadval table pointer
5159 */
5160
5161 uint16_t load_table_ptr;
5162 uint8_t version, headerlen, entrylen, num_entries;
5163
5164 if (bitentry->length != 3) {
5165 NV_ERROR(dev, "Do not understand BIT A table\n");
5166 return -EINVAL;
5167 }
5168
5169 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5170
5171 if (load_table_ptr == 0x0) {
5172 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
5173 return -EINVAL;
5174 }
5175
5176 version = bios->data[load_table_ptr];
5177
5178 if (version != 0x10) {
5179 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5180 version >> 4, version & 0xF);
5181 return -ENOSYS;
5182 }
5183
5184 headerlen = bios->data[load_table_ptr + 1];
5185 entrylen = bios->data[load_table_ptr + 2];
5186 num_entries = bios->data[load_table_ptr + 3];
5187
5188 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5189 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5190 return -EINVAL;
5191 }
5192
5193 /* First entry is normal dac, 2nd tv-out perhaps? */
5194 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
5195
5196 return 0;
5197 }
5198
5199 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5200 {
5201 /*
5202 * offset + 8 (16 bits): PLL limits table pointer
5203 *
5204 * There's more in here, but that's unknown.
5205 */
5206
5207 if (bitentry->length < 10) {
5208 NV_ERROR(dev, "Do not understand BIT C table\n");
5209 return -EINVAL;
5210 }
5211
5212 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5213
5214 return 0;
5215 }
5216
5217 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5218 {
5219 /*
5220 * Parses the flat panel table segment that the bit entry points to.
5221 * Starting at bitentry->offset:
5222 *
5223 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5224 * records beginning with a freq.
5225 * offset + 2 (16 bits): mode table pointer
5226 */
5227
5228 if (bitentry->length != 4) {
5229 NV_ERROR(dev, "Do not understand BIT display table\n");
5230 return -EINVAL;
5231 }
5232
5233 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5234
5235 return 0;
5236 }
5237
5238 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5239 {
5240 /*
5241 * Parses the init table segment that the bit entry points to.
5242 *
5243 * See parse_script_table_pointers for layout
5244 */
5245
5246 if (bitentry->length < 14) {
5247 NV_ERROR(dev, "Do not understand init table\n");
5248 return -EINVAL;
5249 }
5250
5251 parse_script_table_pointers(bios, bitentry->offset);
5252
5253 if (bitentry->length >= 16)
5254 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5255 if (bitentry->length >= 18)
5256 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5257
5258 return 0;
5259 }
5260
5261 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5262 {
5263 /*
5264 * BIT 'i' (info?) table
5265 *
5266 * offset + 0 (32 bits): BIOS version dword (as in B table)
5267 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5268 * offset + 13 (16 bits): pointer to table containing DAC load
5269 * detection comparison values
5270 *
5271 * There's other things in the table, purpose unknown
5272 */
5273
5274 uint16_t daccmpoffset;
5275 uint8_t dacver, dacheaderlen;
5276
5277 if (bitentry->length < 6) {
5278 NV_ERROR(dev, "BIT i table too short for needed information\n");
5279 return -EINVAL;
5280 }
5281
5282 parse_bios_version(dev, bios, bitentry->offset);
5283
5284 /*
5285 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5286 * Quadro identity crisis), other bits possibly as for BMP feature byte
5287 */
5288 bios->feature_byte = bios->data[bitentry->offset + 5];
5289 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5290
5291 if (bitentry->length < 15) {
5292 NV_WARN(dev, "BIT i table not long enough for DAC load "
5293 "detection comparison table\n");
5294 return -EINVAL;
5295 }
5296
5297 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5298
5299 /* doesn't exist on g80 */
5300 if (!daccmpoffset)
5301 return 0;
5302
5303 /*
5304 * The first value in the table, following the header, is the
5305 * comparison value, the second entry is a comparison value for
5306 * TV load detection.
5307 */
5308
5309 dacver = bios->data[daccmpoffset];
5310 dacheaderlen = bios->data[daccmpoffset + 1];
5311
5312 if (dacver != 0x00 && dacver != 0x10) {
5313 NV_WARN(dev, "DAC load detection comparison table version "
5314 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5315 return -ENOSYS;
5316 }
5317
5318 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5319 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
5320
5321 return 0;
5322 }
5323
5324 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5325 {
5326 /*
5327 * Parses the LVDS table segment that the bit entry points to.
5328 * Starting at bitentry->offset:
5329 *
5330 * offset + 0 (16 bits): LVDS strap xlate table pointer
5331 */
5332
5333 if (bitentry->length != 2) {
5334 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5335 return -EINVAL;
5336 }
5337
5338 /*
5339 * No idea if it's still called the LVDS manufacturer table, but
5340 * the concept's close enough.
5341 */
5342 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5343
5344 return 0;
5345 }
5346
5347 static int
5348 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5349 struct bit_entry *bitentry)
5350 {
5351 /*
5352 * offset + 2 (8 bits): number of options in an
5353 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5354 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5355 * restrict option selection
5356 *
5357 * There's a bunch of bits in this table other than the RAM restrict
5358 * stuff that we don't use - their use currently unknown
5359 */
5360
5361 /*
5362 * Older bios versions don't have a sufficiently long table for
5363 * what we want
5364 */
5365 if (bitentry->length < 0x5)
5366 return 0;
5367
5368 if (bitentry->version < 2) {
5369 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5370 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
5371 } else {
5372 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5373 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
5374 }
5375
5376 return 0;
5377 }
5378
5379 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5380 {
5381 /*
5382 * Parses the pointer to the TMDS table
5383 *
5384 * Starting at bitentry->offset:
5385 *
5386 * offset + 0 (16 bits): TMDS table pointer
5387 *
5388 * The TMDS table is typically found just before the DCB table, with a
5389 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5390 * length?)
5391 *
5392 * At offset +7 is a pointer to a script, which I don't know how to
5393 * run yet.
5394 * At offset +9 is a pointer to another script, likewise
5395 * Offset +11 has a pointer to a table where the first word is a pxclk
5396 * frequency and the second word a pointer to a script, which should be
5397 * run if the comparison pxclk frequency is less than the pxclk desired.
5398 * This repeats for decreasing comparison frequencies
5399 * Offset +13 has a pointer to a similar table
5400 * The selection of table (and possibly +7/+9 script) is dictated by
5401 * "or" from the DCB.
5402 */
5403
5404 uint16_t tmdstableptr, script1, script2;
5405
5406 if (bitentry->length != 2) {
5407 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5408 return -EINVAL;
5409 }
5410
5411 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5412 if (!tmdstableptr) {
5413 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5414 return -EINVAL;
5415 }
5416
5417 NV_INFO(dev, "TMDS table version %d.%d\n",
5418 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5419
5420 /* nv50+ has v2.0, but we don't parse it atm */
5421 if (bios->data[tmdstableptr] != 0x11)
5422 return -ENOSYS;
5423
5424 /*
5425 * These two scripts are odd: they don't seem to get run even when
5426 * they are not stubbed.
5427 */
5428 script1 = ROM16(bios->data[tmdstableptr + 7]);
5429 script2 = ROM16(bios->data[tmdstableptr + 9]);
5430 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5431 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5432
5433 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5434 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5435
5436 return 0;
5437 }
5438
5439 static int
5440 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5441 struct bit_entry *bitentry)
5442 {
5443 /*
5444 * Parses the pointer to the G80 output script tables
5445 *
5446 * Starting at bitentry->offset:
5447 *
5448 * offset + 0 (16 bits): output script table pointer
5449 */
5450
5451 uint16_t outputscripttableptr;
5452
5453 if (bitentry->length != 3) {
5454 NV_ERROR(dev, "Do not understand BIT U table\n");
5455 return -EINVAL;
5456 }
5457
5458 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5459 bios->display.script_table_ptr = outputscripttableptr;
5460 return 0;
5461 }
5462
5463 static int
5464 parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5465 struct bit_entry *bitentry)
5466 {
5467 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
5468 return 0;
5469 }
5470
5471 struct bit_table {
5472 const char id;
5473 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5474 };
5475
5476 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5477
5478 int
5479 bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5480 {
5481 struct drm_nouveau_private *dev_priv = dev->dev_private;
5482 struct nvbios *bios = &dev_priv->vbios;
5483 u8 entries, *entry;
5484
5485 entries = bios->data[bios->offset + 10];
5486 entry = &bios->data[bios->offset + 12];
5487 while (entries--) {
5488 if (entry[0] == id) {
5489 bit->id = entry[0];
5490 bit->version = entry[1];
5491 bit->length = ROM16(entry[2]);
5492 bit->offset = ROM16(entry[4]);
5493 bit->data = ROMPTR(bios, entry[4]);
5494 return 0;
5495 }
5496
5497 entry += bios->data[bios->offset + 9];
5498 }
5499
5500 return -ENOENT;
5501 }
5502
5503 static int
5504 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5505 struct bit_table *table)
5506 {
5507 struct drm_device *dev = bios->dev;
5508 struct bit_entry bitentry;
5509
5510 if (bit_table(dev, table->id, &bitentry) == 0)
5511 return table->parse_fn(dev, bios, &bitentry);
5512
5513 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5514 return -ENOSYS;
5515 }
5516
5517 static int
5518 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5519 {
5520 int ret;
5521
5522 /*
5523 * The only restriction on parsing order currently is having 'i' first
5524 * for use of bios->*_version or bios->feature_byte while parsing;
5525 * functions shouldn't be actually *doing* anything apart from pulling
5526 * data from the image into the bios struct, thus no interdependencies
5527 */
5528 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5529 if (ret) /* info? */
5530 return ret;
5531 if (bios->major_version >= 0x60) /* g80+ */
5532 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5533 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5534 if (ret)
5535 return ret;
5536 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5537 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5538 if (ret)
5539 return ret;
5540 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5541 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5542 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5543 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5544 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
5545
5546 return 0;
5547 }
5548
5549 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5550 {
5551 /*
5552 * Parses the BMP structure for useful things, but does not act on them
5553 *
5554 * offset + 5: BMP major version
5555 * offset + 6: BMP minor version
5556 * offset + 9: BMP feature byte
5557 * offset + 10: BCD encoded BIOS version
5558 *
5559 * offset + 18: init script table pointer (for bios versions < 5.10h)
5560 * offset + 20: extra init script table pointer (for bios
5561 * versions < 5.10h)
5562 *
5563 * offset + 24: memory init table pointer (used on early bios versions)
5564 * offset + 26: SDR memory sequencing setup data table
5565 * offset + 28: DDR memory sequencing setup data table
5566 *
5567 * offset + 54: index of I2C CRTC pair to use for CRT output
5568 * offset + 55: index of I2C CRTC pair to use for TV output
5569 * offset + 56: index of I2C CRTC pair to use for flat panel output
5570 * offset + 58: write CRTC index for I2C pair 0
5571 * offset + 59: read CRTC index for I2C pair 0
5572 * offset + 60: write CRTC index for I2C pair 1
5573 * offset + 61: read CRTC index for I2C pair 1
5574 *
5575 * offset + 67: maximum internal PLL frequency (single stage PLL)
5576 * offset + 71: minimum internal PLL frequency (single stage PLL)
5577 *
5578 * offset + 75: script table pointers, as described in
5579 * parse_script_table_pointers
5580 *
5581 * offset + 89: TMDS single link output A table pointer
5582 * offset + 91: TMDS single link output B table pointer
5583 * offset + 95: LVDS single link output A table pointer
5584 * offset + 105: flat panel timings table pointer
5585 * offset + 107: flat panel strapping translation table pointer
5586 * offset + 117: LVDS manufacturer panel config table pointer
5587 * offset + 119: LVDS manufacturer strapping translation table pointer
5588 *
5589 * offset + 142: PLL limits table pointer
5590 *
5591 * offset + 156: minimum pixel clock for LVDS dual link
5592 */
5593
5594 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5595 uint16_t bmplength;
5596 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5597
5598 /* load needed defaults in case we can't parse this info */
5599 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5600 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5601 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5602 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
5603 bios->digital_min_front_porch = 0x4b;
5604 bios->fmaxvco = 256000;
5605 bios->fminvco = 128000;
5606 bios->fp.duallink_transition_clk = 90000;
5607
5608 bmp_version_major = bmp[5];
5609 bmp_version_minor = bmp[6];
5610
5611 NV_TRACE(dev, "BMP version %d.%d\n",
5612 bmp_version_major, bmp_version_minor);
5613
5614 /*
5615 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5616 * pointer on early versions
5617 */
5618 if (bmp_version_major < 5)
5619 *(uint16_t *)&bios->data[0x36] = 0;
5620
5621 /*
5622 * Seems that the minor version was 1 for all major versions prior
5623 * to 5. Version 6 could theoretically exist, but I suspect BIT
5624 * happened instead.
5625 */
5626 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5627 NV_ERROR(dev, "You have an unsupported BMP version. "
5628 "Please send in your bios\n");
5629 return -ENOSYS;
5630 }
5631
5632 if (bmp_version_major == 0)
5633 /* nothing that's currently useful in this version */
5634 return 0;
5635 else if (bmp_version_major == 1)
5636 bmplength = 44; /* exact for 1.01 */
5637 else if (bmp_version_major == 2)
5638 bmplength = 48; /* exact for 2.01 */
5639 else if (bmp_version_major == 3)
5640 bmplength = 54;
5641 /* guessed - mem init tables added in this version */
5642 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5643 /* don't know if 5.0 exists... */
5644 bmplength = 62;
5645 /* guessed - BMP I2C indices added in version 4*/
5646 else if (bmp_version_minor < 0x6)
5647 bmplength = 67; /* exact for 5.01 */
5648 else if (bmp_version_minor < 0x10)
5649 bmplength = 75; /* exact for 5.06 */
5650 else if (bmp_version_minor == 0x10)
5651 bmplength = 89; /* exact for 5.10h */
5652 else if (bmp_version_minor < 0x14)
5653 bmplength = 118; /* exact for 5.11h */
5654 else if (bmp_version_minor < 0x24)
5655 /*
5656 * Not sure of version where pll limits came in;
5657 * certainly exist by 0x24 though.
5658 */
5659 /* length not exact: this is long enough to get lvds members */
5660 bmplength = 123;
5661 else if (bmp_version_minor < 0x27)
5662 /*
5663 * Length not exact: this is long enough to get pll limit
5664 * member
5665 */
5666 bmplength = 144;
5667 else
5668 /*
5669 * Length not exact: this is long enough to get dual link
5670 * transition clock.
5671 */
5672 bmplength = 158;
5673
5674 /* checksum */
5675 if (nv_cksum(bmp, 8)) {
5676 NV_ERROR(dev, "Bad BMP checksum\n");
5677 return -EINVAL;
5678 }
5679
5680 /*
5681 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5682 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5683 * (not nv10gl), bit 5 that the flat panel tables are present, and
5684 * bit 6 a tv bios.
5685 */
5686 bios->feature_byte = bmp[9];
5687
5688 parse_bios_version(dev, bios, offset + 10);
5689
5690 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5691 bios->old_style_init = true;
5692 legacy_scripts_offset = 18;
5693 if (bmp_version_major < 2)
5694 legacy_scripts_offset -= 4;
5695 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5696 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5697
5698 if (bmp_version_major > 2) { /* appears in BMP 3 */
5699 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5700 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5701 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5702 }
5703
5704 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5705 if (bmplength > 61)
5706 legacy_i2c_offset = offset + 54;
5707 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5708 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5709 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
5710 if (bios->data[legacy_i2c_offset + 4])
5711 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5712 if (bios->data[legacy_i2c_offset + 5])
5713 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5714 if (bios->data[legacy_i2c_offset + 6])
5715 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5716 if (bios->data[legacy_i2c_offset + 7])
5717 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
5718
5719 if (bmplength > 74) {
5720 bios->fmaxvco = ROM32(bmp[67]);
5721 bios->fminvco = ROM32(bmp[71]);
5722 }
5723 if (bmplength > 88)
5724 parse_script_table_pointers(bios, offset + 75);
5725 if (bmplength > 94) {
5726 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5727 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5728 /*
5729 * Never observed in use with lvds scripts, but is reused for
5730 * 18/24 bit panel interface default for EDID equipped panels
5731 * (if_is_24bit not set directly to avoid any oscillation).
5732 */
5733 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5734 }
5735 if (bmplength > 108) {
5736 bios->fp.fptablepointer = ROM16(bmp[105]);
5737 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5738 bios->fp.xlatwidth = 1;
5739 }
5740 if (bmplength > 120) {
5741 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5742 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5743 }
5744 if (bmplength > 143)
5745 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5746
5747 if (bmplength > 157)
5748 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5749
5750 return 0;
5751 }
5752
5753 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5754 {
5755 int i, j;
5756
5757 for (i = 0; i <= (n - len); i++) {
5758 for (j = 0; j < len; j++)
5759 if (data[i + j] != str[j])
5760 break;
5761 if (j == len)
5762 return i;
5763 }
5764
5765 return 0;
5766 }
5767
5768 static struct dcb_gpio_entry *
5769 new_gpio_entry(struct nvbios *bios)
5770 {
5771 struct drm_device *dev = bios->dev;
5772 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
5773
5774 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) {
5775 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n");
5776 return NULL;
5777 }
5778
5779 return &gpio->entry[gpio->entries++];
5780 }
5781
5782 struct dcb_gpio_entry *
5783 nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5784 {
5785 struct drm_nouveau_private *dev_priv = dev->dev_private;
5786 struct nvbios *bios = &dev_priv->vbios;
5787 int i;
5788
5789 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5790 if (bios->dcb.gpio.entry[i].tag != tag)
5791 continue;
5792
5793 return &bios->dcb.gpio.entry[i];
5794 }
5795
5796 return NULL;
5797 }
5798
5799 static void
5800 parse_dcb_gpio_table(struct nvbios *bios)
5801 {
5802 struct drm_device *dev = bios->dev;
5803 struct dcb_gpio_entry *e;
5804 u8 headerlen, entries, recordlen;
5805 u8 *dcb, *gpio = NULL, *entry;
5806 int i;
5807
5808 dcb = ROMPTR(bios, bios->data[0x36]);
5809 if (dcb[0] >= 0x30) {
5810 gpio = ROMPTR(bios, dcb[10]);
5811 if (!gpio)
5812 goto no_table;
5813
5814 headerlen = gpio[1];
5815 entries = gpio[2];
5816 recordlen = gpio[3];
5817 } else
5818 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) {
5819 gpio = ROMPTR(bios, dcb[-15]);
5820 if (!gpio)
5821 goto no_table;
5822
5823 headerlen = 3;
5824 entries = gpio[2];
5825 recordlen = gpio[1];
5826 } else
5827 if (dcb[0] >= 0x22) {
5828 /* No GPIO table present, parse the TVDAC GPIO data. */
5829 uint8_t *tvdac_gpio = &dcb[-5];
5830
5831 if (tvdac_gpio[0] & 1) {
5832 e = new_gpio_entry(bios);
5833 e->tag = DCB_GPIO_TVDAC0;
5834 e->line = tvdac_gpio[1] >> 4;
5835 e->invert = tvdac_gpio[0] & 2;
5836 }
5837
5838 goto no_table;
5839 } else {
5840 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]);
5841 goto no_table;
5842 }
5843
5844 entry = gpio + headerlen;
5845 for (i = 0; i < entries; i++, entry += recordlen) {
5846 e = new_gpio_entry(bios);
5847 if (!e)
5848 break;
5849
5850 if (gpio[0] < 0x40) {
5851 e->entry = ROM16(entry[0]);
5852 e->tag = (e->entry & 0x07e0) >> 5;
5853 if (e->tag == 0x3f) {
5854 bios->dcb.gpio.entries--;
5855 continue;
5856 }
5857
5858 e->line = (e->entry & 0x001f);
5859 e->invert = ((e->entry & 0xf800) >> 11) != 4;
5860 } else {
5861 e->entry = ROM32(entry[0]);
5862 e->tag = (e->entry & 0x0000ff00) >> 8;
5863 if (e->tag == 0xff) {
5864 bios->dcb.gpio.entries--;
5865 continue;
5866 }
5867
5868 e->line = (e->entry & 0x0000001f) >> 0;
5869 e->state_default = (e->entry & 0x01000000) >> 24;
5870 e->state[0] = (e->entry & 0x18000000) >> 27;
5871 e->state[1] = (e->entry & 0x60000000) >> 29;
5872 }
5873 }
5874
5875 no_table:
5876 /* Apple iMac G4 NV18 */
5877 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5878 e = new_gpio_entry(bios);
5879 if (e) {
5880 e->tag = DCB_GPIO_TVDAC0;
5881 e->line = 4;
5882 }
5883 }
5884 }
5885
5886 struct dcb_connector_table_entry *
5887 nouveau_bios_connector_entry(struct drm_device *dev, int index)
5888 {
5889 struct drm_nouveau_private *dev_priv = dev->dev_private;
5890 struct nvbios *bios = &dev_priv->vbios;
5891 struct dcb_connector_table_entry *cte;
5892
5893 if (index >= bios->dcb.connector.entries)
5894 return NULL;
5895
5896 cte = &bios->dcb.connector.entry[index];
5897 if (cte->type == 0xff)
5898 return NULL;
5899
5900 return cte;
5901 }
5902
5903 static enum dcb_connector_type
5904 divine_connector_type(struct nvbios *bios, int index)
5905 {
5906 struct dcb_table *dcb = &bios->dcb;
5907 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5908 int i;
5909
5910 for (i = 0; i < dcb->entries; i++) {
5911 if (dcb->entry[i].connector == index)
5912 encoders |= (1 << dcb->entry[i].type);
5913 }
5914
5915 if (encoders & (1 << OUTPUT_DP)) {
5916 if (encoders & (1 << OUTPUT_TMDS))
5917 type = DCB_CONNECTOR_DP;
5918 else
5919 type = DCB_CONNECTOR_eDP;
5920 } else
5921 if (encoders & (1 << OUTPUT_TMDS)) {
5922 if (encoders & (1 << OUTPUT_ANALOG))
5923 type = DCB_CONNECTOR_DVI_I;
5924 else
5925 type = DCB_CONNECTOR_DVI_D;
5926 } else
5927 if (encoders & (1 << OUTPUT_ANALOG)) {
5928 type = DCB_CONNECTOR_VGA;
5929 } else
5930 if (encoders & (1 << OUTPUT_LVDS)) {
5931 type = DCB_CONNECTOR_LVDS;
5932 } else
5933 if (encoders & (1 << OUTPUT_TV)) {
5934 type = DCB_CONNECTOR_TV_0;
5935 }
5936
5937 return type;
5938 }
5939
5940 static void
5941 apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5942 {
5943 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5944 struct drm_device *dev = bios->dev;
5945
5946 /* Gigabyte NX85T */
5947 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
5948 if (cte->type == DCB_CONNECTOR_HDMI_1)
5949 cte->type = DCB_CONNECTOR_DVI_I;
5950 }
5951 }
5952
5953 static void
5954 parse_dcb_connector_table(struct nvbios *bios)
5955 {
5956 struct drm_device *dev = bios->dev;
5957 struct dcb_connector_table *ct = &bios->dcb.connector;
5958 struct dcb_connector_table_entry *cte;
5959 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
5960 uint8_t *entry;
5961 int i;
5962
5963 if (!bios->dcb.connector_table_ptr) {
5964 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
5965 return;
5966 }
5967
5968 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5969 conntab[0], conntab[1], conntab[2], conntab[3]);
5970 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5971 (conntab[3] != 2 && conntab[3] != 4)) {
5972 NV_ERROR(dev, " Unknown! Please report.\n");
5973 return;
5974 }
5975
5976 ct->entries = conntab[2];
5977
5978 entry = conntab + conntab[1];
5979 cte = &ct->entry[0];
5980 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
5981 cte->index = i;
5982 if (conntab[3] == 2)
5983 cte->entry = ROM16(entry[0]);
5984 else
5985 cte->entry = ROM32(entry[0]);
5986
5987 cte->type = (cte->entry & 0x000000ff) >> 0;
5988 cte->index2 = (cte->entry & 0x00000f00) >> 8;
5989 switch (cte->entry & 0x00033000) {
5990 case 0x00001000:
5991 cte->gpio_tag = 0x07;
5992 break;
5993 case 0x00002000:
5994 cte->gpio_tag = 0x08;
5995 break;
5996 case 0x00010000:
5997 cte->gpio_tag = 0x51;
5998 break;
5999 case 0x00020000:
6000 cte->gpio_tag = 0x52;
6001 break;
6002 default:
6003 cte->gpio_tag = 0xff;
6004 break;
6005 }
6006
6007 if (cte->type == 0xff)
6008 continue;
6009
6010 apply_dcb_connector_quirks(bios, i);
6011
6012 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
6013 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
6014
6015 /* check for known types, fallback to guessing the type
6016 * from attached encoders if we hit an unknown.
6017 */
6018 switch (cte->type) {
6019 case DCB_CONNECTOR_VGA:
6020 case DCB_CONNECTOR_TV_0:
6021 case DCB_CONNECTOR_TV_1:
6022 case DCB_CONNECTOR_TV_3:
6023 case DCB_CONNECTOR_DVI_I:
6024 case DCB_CONNECTOR_DVI_D:
6025 case DCB_CONNECTOR_LVDS:
6026 case DCB_CONNECTOR_DP:
6027 case DCB_CONNECTOR_eDP:
6028 case DCB_CONNECTOR_HDMI_0:
6029 case DCB_CONNECTOR_HDMI_1:
6030 break;
6031 default:
6032 cte->type = divine_connector_type(bios, cte->index);
6033 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
6034 break;
6035 }
6036
6037 if (nouveau_override_conntype) {
6038 int type = divine_connector_type(bios, cte->index);
6039 if (type != cte->type)
6040 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
6041 }
6042
6043 }
6044 }
6045
6046 static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6047 {
6048 struct dcb_entry *entry = &dcb->entry[dcb->entries];
6049
6050 memset(entry, 0, sizeof(struct dcb_entry));
6051 entry->index = dcb->entries++;
6052
6053 return entry;
6054 }
6055
6056 static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
6057 int heads, int or)
6058 {
6059 struct dcb_entry *entry = new_dcb_entry(dcb);
6060
6061 entry->type = type;
6062 entry->i2c_index = i2c;
6063 entry->heads = heads;
6064 if (type != OUTPUT_ANALOG)
6065 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
6066 entry->or = or;
6067 }
6068
6069 static bool
6070 parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6071 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6072 {
6073 entry->type = conn & 0xf;
6074 entry->i2c_index = (conn >> 4) & 0xf;
6075 entry->heads = (conn >> 8) & 0xf;
6076 if (dcb->version >= 0x40)
6077 entry->connector = (conn >> 12) & 0xf;
6078 entry->bus = (conn >> 16) & 0xf;
6079 entry->location = (conn >> 20) & 0x3;
6080 entry->or = (conn >> 24) & 0xf;
6081
6082 switch (entry->type) {
6083 case OUTPUT_ANALOG:
6084 /*
6085 * Although the rest of a CRT conf dword is usually
6086 * zeros, mac biosen have stuff there so we must mask
6087 */
6088 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6089 (conf & 0xffff) * 10 :
6090 (conf & 0xff) * 10000;
6091 break;
6092 case OUTPUT_LVDS:
6093 {
6094 uint32_t mask;
6095 if (conf & 0x1)
6096 entry->lvdsconf.use_straps_for_mode = true;
6097 if (dcb->version < 0x22) {
6098 mask = ~0xd;
6099 /*
6100 * The laptop in bug 14567 lies and claims to not use
6101 * straps when it does, so assume all DCB 2.0 laptops
6102 * use straps, until a broken EDID using one is produced
6103 */
6104 entry->lvdsconf.use_straps_for_mode = true;
6105 /*
6106 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
6107 * mean the same thing (probably wrong, but might work)
6108 */
6109 if (conf & 0x4 || conf & 0x8)
6110 entry->lvdsconf.use_power_scripts = true;
6111 } else {
6112 mask = ~0x7;
6113 if (conf & 0x2)
6114 entry->lvdsconf.use_acpi_for_edid = true;
6115 if (conf & 0x4)
6116 entry->lvdsconf.use_power_scripts = true;
6117 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6118 }
6119 if (conf & mask) {
6120 /*
6121 * Until we even try to use these on G8x, it's
6122 * useless reporting unknown bits. They all are.
6123 */
6124 if (dcb->version >= 0x40)
6125 break;
6126
6127 NV_ERROR(dev, "Unknown LVDS configuration bits, "
6128 "please report\n");
6129 }
6130 break;
6131 }
6132 case OUTPUT_TV:
6133 {
6134 if (dcb->version >= 0x30)
6135 entry->tvconf.has_component_output = conf & (0x8 << 4);
6136 else
6137 entry->tvconf.has_component_output = false;
6138
6139 break;
6140 }
6141 case OUTPUT_DP:
6142 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
6143 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
6144 switch ((conf & 0x0f000000) >> 24) {
6145 case 0xf:
6146 entry->dpconf.link_nr = 4;
6147 break;
6148 case 0x3:
6149 entry->dpconf.link_nr = 2;
6150 break;
6151 default:
6152 entry->dpconf.link_nr = 1;
6153 break;
6154 }
6155 break;
6156 case OUTPUT_TMDS:
6157 if (dcb->version >= 0x40)
6158 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
6159 else if (dcb->version >= 0x30)
6160 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
6161 else if (dcb->version >= 0x22)
6162 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
6163
6164 break;
6165 case OUTPUT_EOL:
6166 /* weird g80 mobile type that "nv" treats as a terminator */
6167 dcb->entries--;
6168 return false;
6169 default:
6170 break;
6171 }
6172
6173 if (dcb->version < 0x40) {
6174 /* Normal entries consist of a single bit, but dual link has
6175 * the next most significant bit set too
6176 */
6177 entry->duallink_possible =
6178 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6179 } else {
6180 entry->duallink_possible = (entry->sorconf.link == 3);
6181 }
6182
6183 /* unsure what DCB version introduces this, 3.0? */
6184 if (conf & 0x100000)
6185 entry->i2c_upper_default = true;
6186
6187 return true;
6188 }
6189
6190 static bool
6191 parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6192 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6193 {
6194 switch (conn & 0x0000000f) {
6195 case 0:
6196 entry->type = OUTPUT_ANALOG;
6197 break;
6198 case 1:
6199 entry->type = OUTPUT_TV;
6200 break;
6201 case 2:
6202 case 4:
6203 if (conn & 0x10)
6204 entry->type = OUTPUT_LVDS;
6205 else
6206 entry->type = OUTPUT_TMDS;
6207 break;
6208 case 3:
6209 entry->type = OUTPUT_LVDS;
6210 break;
6211 default:
6212 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6213 return false;
6214 }
6215
6216 entry->i2c_index = (conn & 0x0003c000) >> 14;
6217 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6218 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6219 entry->location = (conn & 0x01e00000) >> 21;
6220 entry->bus = (conn & 0x0e000000) >> 25;
6221 entry->duallink_possible = false;
6222
6223 switch (entry->type) {
6224 case OUTPUT_ANALOG:
6225 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6226 break;
6227 case OUTPUT_TV:
6228 entry->tvconf.has_component_output = false;
6229 break;
6230 case OUTPUT_LVDS:
6231 if ((conn & 0x00003f00) != 0x10)
6232 entry->lvdsconf.use_straps_for_mode = true;
6233 entry->lvdsconf.use_power_scripts = true;
6234 break;
6235 default:
6236 break;
6237 }
6238
6239 return true;
6240 }
6241
6242 static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6243 uint32_t conn, uint32_t conf)
6244 {
6245 struct dcb_entry *entry = new_dcb_entry(dcb);
6246 bool ret;
6247
6248 if (dcb->version >= 0x20)
6249 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6250 else
6251 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6252 if (!ret)
6253 return ret;
6254
6255 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6256 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6257
6258 return true;
6259 }
6260
6261 static
6262 void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6263 {
6264 /*
6265 * DCB v2.0 lists each output combination separately.
6266 * Here we merge compatible entries to have fewer outputs, with
6267 * more options
6268 */
6269
6270 int i, newentries = 0;
6271
6272 for (i = 0; i < dcb->entries; i++) {
6273 struct dcb_entry *ient = &dcb->entry[i];
6274 int j;
6275
6276 for (j = i + 1; j < dcb->entries; j++) {
6277 struct dcb_entry *jent = &dcb->entry[j];
6278
6279 if (jent->type == 100) /* already merged entry */
6280 continue;
6281
6282 /* merge heads field when all other fields the same */
6283 if (jent->i2c_index == ient->i2c_index &&
6284 jent->type == ient->type &&
6285 jent->location == ient->location &&
6286 jent->or == ient->or) {
6287 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6288 i, j);
6289 ient->heads |= jent->heads;
6290 jent->type = 100; /* dummy value */
6291 }
6292 }
6293 }
6294
6295 /* Compact entries merged into others out of dcb */
6296 for (i = 0; i < dcb->entries; i++) {
6297 if (dcb->entry[i].type == 100)
6298 continue;
6299
6300 if (newentries != i) {
6301 dcb->entry[newentries] = dcb->entry[i];
6302 dcb->entry[newentries].index = newentries;
6303 }
6304 newentries++;
6305 }
6306
6307 dcb->entries = newentries;
6308 }
6309
6310 static bool
6311 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6312 {
6313 /* Dell Precision M6300
6314 * DCB entry 2: 02025312 00000010
6315 * DCB entry 3: 02026312 00000020
6316 *
6317 * Identical, except apparently a different connector on a
6318 * different SOR link. Not a clue how we're supposed to know
6319 * which one is in use if it even shares an i2c line...
6320 *
6321 * Ignore the connector on the second SOR link to prevent
6322 * nasty problems until this is sorted (assuming it's not a
6323 * VBIOS bug).
6324 */
6325 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
6326 if (*conn == 0x02026312 && *conf == 0x00000020)
6327 return false;
6328 }
6329
6330 return true;
6331 }
6332
6333 static void
6334 fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6335 {
6336 struct dcb_table *dcb = &bios->dcb;
6337 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6338
6339 #ifdef __powerpc__
6340 /* Apple iMac G4 NV17 */
6341 if (of_machine_is_compatible("PowerMac4,5")) {
6342 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6343 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6344 return;
6345 }
6346 #endif
6347
6348 /* Make up some sane defaults */
6349 fabricate_dcb_output(dcb, OUTPUT_ANALOG, LEGACY_I2C_CRT, 1, 1);
6350
6351 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6352 fabricate_dcb_output(dcb, OUTPUT_TV, LEGACY_I2C_TV,
6353 all_heads, 0);
6354
6355 else if (bios->tmds.output0_script_ptr ||
6356 bios->tmds.output1_script_ptr)
6357 fabricate_dcb_output(dcb, OUTPUT_TMDS, LEGACY_I2C_PANEL,
6358 all_heads, 1);
6359 }
6360
6361 static int
6362 parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6363 {
6364 struct drm_nouveau_private *dev_priv = dev->dev_private;
6365 struct dcb_table *dcb = &bios->dcb;
6366 uint16_t dcbptr = 0, i2ctabptr = 0;
6367 uint8_t *dcbtable;
6368 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
6369 bool configblock = true;
6370 int recordlength = 8, confofs = 4;
6371 int i;
6372
6373 /* get the offset from 0x36 */
6374 if (dev_priv->card_type > NV_04) {
6375 dcbptr = ROM16(bios->data[0x36]);
6376 if (dcbptr == 0x0000)
6377 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
6378 }
6379
6380 /* this situation likely means a really old card, pre DCB */
6381 if (dcbptr == 0x0) {
6382 fabricate_dcb_encoder_table(dev, bios);
6383 return 0;
6384 }
6385
6386 dcbtable = &bios->data[dcbptr];
6387
6388 /* get DCB version */
6389 dcb->version = dcbtable[0];
6390 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
6391 dcb->version >> 4, dcb->version & 0xf);
6392
6393 if (dcb->version >= 0x20) { /* NV17+ */
6394 uint32_t sig;
6395
6396 if (dcb->version >= 0x30) { /* NV40+ */
6397 headerlen = dcbtable[1];
6398 entries = dcbtable[2];
6399 recordlength = dcbtable[3];
6400 i2ctabptr = ROM16(dcbtable[4]);
6401 sig = ROM32(dcbtable[6]);
6402 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
6403 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6404 } else {
6405 i2ctabptr = ROM16(dcbtable[2]);
6406 sig = ROM32(dcbtable[4]);
6407 headerlen = 8;
6408 }
6409
6410 if (sig != 0x4edcbdcb) {
6411 NV_ERROR(dev, "Bad Display Configuration Block "
6412 "signature (%08X)\n", sig);
6413 return -EINVAL;
6414 }
6415 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6416 char sig[8] = { 0 };
6417
6418 strncpy(sig, (char *)&dcbtable[-7], 7);
6419 i2ctabptr = ROM16(dcbtable[2]);
6420 recordlength = 10;
6421 confofs = 6;
6422
6423 if (strcmp(sig, "DEV_REC")) {
6424 NV_ERROR(dev, "Bad Display Configuration Block "
6425 "signature (%s)\n", sig);
6426 return -EINVAL;
6427 }
6428 } else {
6429 /*
6430 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6431 * has the same single (crt) entry, even when tv-out present, so
6432 * the conclusion is this version cannot really be used.
6433 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6434 * 5 entries, which are not specific to the card and so no use.
6435 * v1.2 does have an I2C table that read_dcb_i2c_table can
6436 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6437 * pointer, so use the indices parsed in parse_bmp_structure.
6438 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6439 */
6440 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
6441 "adding all possible outputs\n");
6442 fabricate_dcb_encoder_table(dev, bios);
6443 return 0;
6444 }
6445
6446 if (!i2ctabptr)
6447 NV_WARN(dev, "No pointer to DCB I2C port table\n");
6448 else {
6449 dcb->i2c_table = &bios->data[i2ctabptr];
6450 if (dcb->version >= 0x30)
6451 dcb->i2c_default_indices = dcb->i2c_table[4];
6452
6453 /*
6454 * Parse the "management" I2C bus, used for hardware
6455 * monitoring and some external TMDS transmitters.
6456 */
6457 if (dcb->version >= 0x22) {
6458 int idx = (dcb->version >= 0x40 ?
6459 dcb->i2c_default_indices & 0xf :
6460 2);
6461
6462 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6463 idx, &dcb->i2c[idx]);
6464 }
6465 }
6466
6467 if (entries > DCB_MAX_NUM_ENTRIES)
6468 entries = DCB_MAX_NUM_ENTRIES;
6469
6470 for (i = 0; i < entries; i++) {
6471 uint32_t connection, config = 0;
6472
6473 connection = ROM32(dcbtable[headerlen + recordlength * i]);
6474 if (configblock)
6475 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
6476
6477 /* seen on an NV11 with DCB v1.5 */
6478 if (connection == 0x00000000)
6479 break;
6480
6481 /* seen on an NV17 with DCB v2.0 */
6482 if (connection == 0xffffffff)
6483 break;
6484
6485 if ((connection & 0x0000000f) == 0x0000000f)
6486 continue;
6487
6488 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config))
6489 continue;
6490
6491 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
6492 dcb->entries, connection, config);
6493
6494 if (!parse_dcb_entry(dev, dcb, connection, config))
6495 break;
6496 }
6497
6498 /*
6499 * apart for v2.1+ not being known for requiring merging, this
6500 * guarantees dcbent->index is the index of the entry in the rom image
6501 */
6502 if (dcb->version < 0x21)
6503 merge_like_dcb_entries(dev, dcb);
6504
6505 if (!dcb->entries)
6506 return -ENXIO;
6507
6508 parse_dcb_gpio_table(bios);
6509 parse_dcb_connector_table(bios);
6510 return 0;
6511 }
6512
6513 static void
6514 fixup_legacy_connector(struct nvbios *bios)
6515 {
6516 struct dcb_table *dcb = &bios->dcb;
6517 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6518
6519 /*
6520 * DCB 3.0 also has the table in most cases, but there are some cards
6521 * where the table is filled with stub entries, and the DCB entriy
6522 * indices are all 0. We don't need the connector indices on pre-G80
6523 * chips (yet?) so limit the use to DCB 4.0 and above.
6524 */
6525 if (dcb->version >= 0x40)
6526 return;
6527
6528 dcb->connector.entries = 0;
6529
6530 /*
6531 * No known connector info before v3.0, so make it up. the rule here
6532 * is: anything on the same i2c bus is considered to be on the same
6533 * connector. any output without an associated i2c bus is assigned
6534 * its own unique connector index.
6535 */
6536 for (i = 0; i < dcb->entries; i++) {
6537 /*
6538 * Ignore the I2C index for on-chip TV-out, as there
6539 * are cards with bogus values (nv31m in bug 23212),
6540 * and it's otherwise useless.
6541 */
6542 if (dcb->entry[i].type == OUTPUT_TV &&
6543 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6544 dcb->entry[i].i2c_index = 0xf;
6545 i2c = dcb->entry[i].i2c_index;
6546
6547 if (i2c_conn[i2c]) {
6548 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6549 continue;
6550 }
6551
6552 dcb->entry[i].connector = dcb->connector.entries++;
6553 if (i2c != 0xf)
6554 i2c_conn[i2c] = dcb->connector.entries;
6555 }
6556
6557 /* Fake the connector table as well as just connector indices */
6558 for (i = 0; i < dcb->connector.entries; i++) {
6559 dcb->connector.entry[i].index = i;
6560 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6561 dcb->connector.entry[i].gpio_tag = 0xff;
6562 }
6563 }
6564
6565 static void
6566 fixup_legacy_i2c(struct nvbios *bios)
6567 {
6568 struct dcb_table *dcb = &bios->dcb;
6569 int i;
6570
6571 for (i = 0; i < dcb->entries; i++) {
6572 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
6573 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
6574 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
6575 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
6576 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
6577 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
6578 }
6579 }
6580
6581 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6582 {
6583 /*
6584 * The header following the "HWSQ" signature has the number of entries,
6585 * and the entry size
6586 *
6587 * An entry consists of a dword to write to the sequencer control reg
6588 * (0x00001304), followed by the ucode bytes, written sequentially,
6589 * starting at reg 0x00001400
6590 */
6591
6592 uint8_t bytes_to_write;
6593 uint16_t hwsq_entry_offset;
6594 int i;
6595
6596 if (bios->data[hwsq_offset] <= entry) {
6597 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6598 "requested entry\n");
6599 return -ENOENT;
6600 }
6601
6602 bytes_to_write = bios->data[hwsq_offset + 1];
6603
6604 if (bytes_to_write != 36) {
6605 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6606 return -EINVAL;
6607 }
6608
6609 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6610
6611 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6612
6613 /* set sequencer control */
6614 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6615 bytes_to_write -= 4;
6616
6617 /* write ucode */
6618 for (i = 0; i < bytes_to_write; i += 4)
6619 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6620
6621 /* twiddle NV_PBUS_DEBUG_4 */
6622 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6623
6624 return 0;
6625 }
6626
6627 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6628 struct nvbios *bios)
6629 {
6630 /*
6631 * BMP based cards, from NV17, need a microcode loading to correctly
6632 * control the GPIO etc for LVDS panels
6633 *
6634 * BIT based cards seem to do this directly in the init scripts
6635 *
6636 * The microcode entries are found by the "HWSQ" signature.
6637 */
6638
6639 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6640 const int sz = sizeof(hwsq_signature);
6641 int hwsq_offset;
6642
6643 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6644 if (!hwsq_offset)
6645 return 0;
6646
6647 /* always use entry 0? */
6648 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6649 }
6650
6651 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6652 {
6653 struct drm_nouveau_private *dev_priv = dev->dev_private;
6654 struct nvbios *bios = &dev_priv->vbios;
6655 const uint8_t edid_sig[] = {
6656 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6657 uint16_t offset = 0;
6658 uint16_t newoffset;
6659 int searchlen = NV_PROM_SIZE;
6660
6661 if (bios->fp.edid)
6662 return bios->fp.edid;
6663
6664 while (searchlen) {
6665 newoffset = findstr(&bios->data[offset], searchlen,
6666 edid_sig, 8);
6667 if (!newoffset)
6668 return NULL;
6669 offset += newoffset;
6670 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6671 break;
6672
6673 searchlen -= offset;
6674 offset++;
6675 }
6676
6677 NV_TRACE(dev, "Found EDID in BIOS\n");
6678
6679 return bios->fp.edid = &bios->data[offset];
6680 }
6681
6682 void
6683 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6684 struct dcb_entry *dcbent)
6685 {
6686 struct drm_nouveau_private *dev_priv = dev->dev_private;
6687 struct nvbios *bios = &dev_priv->vbios;
6688 struct init_exec iexec = { true, false };
6689
6690 mutex_lock(&bios->lock);
6691 bios->display.output = dcbent;
6692 parse_init_table(bios, table, &iexec);
6693 bios->display.output = NULL;
6694 mutex_unlock(&bios->lock);
6695 }
6696
6697 static bool NVInitVBIOS(struct drm_device *dev)
6698 {
6699 struct drm_nouveau_private *dev_priv = dev->dev_private;
6700 struct nvbios *bios = &dev_priv->vbios;
6701
6702 memset(bios, 0, sizeof(struct nvbios));
6703 mutex_init(&bios->lock);
6704 bios->dev = dev;
6705
6706 if (!NVShadowVBIOS(dev, bios->data))
6707 return false;
6708
6709 bios->length = NV_PROM_SIZE;
6710 return true;
6711 }
6712
6713 static int nouveau_parse_vbios_struct(struct drm_device *dev)
6714 {
6715 struct drm_nouveau_private *dev_priv = dev->dev_private;
6716 struct nvbios *bios = &dev_priv->vbios;
6717 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6718 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6719 int offset;
6720
6721 offset = findstr(bios->data, bios->length,
6722 bit_signature, sizeof(bit_signature));
6723 if (offset) {
6724 NV_TRACE(dev, "BIT BIOS found\n");
6725 bios->type = NVBIOS_BIT;
6726 bios->offset = offset;
6727 return parse_bit_structure(bios, offset + 6);
6728 }
6729
6730 offset = findstr(bios->data, bios->length,
6731 bmp_signature, sizeof(bmp_signature));
6732 if (offset) {
6733 NV_TRACE(dev, "BMP BIOS found\n");
6734 bios->type = NVBIOS_BMP;
6735 bios->offset = offset;
6736 return parse_bmp_structure(dev, bios, offset);
6737 }
6738
6739 NV_ERROR(dev, "No known BIOS signature found\n");
6740 return -ENODEV;
6741 }
6742
6743 int
6744 nouveau_run_vbios_init(struct drm_device *dev)
6745 {
6746 struct drm_nouveau_private *dev_priv = dev->dev_private;
6747 struct nvbios *bios = &dev_priv->vbios;
6748 int i, ret = 0;
6749
6750 /* Reset the BIOS head to 0. */
6751 bios->state.crtchead = 0;
6752
6753 if (bios->major_version < 5) /* BMP only */
6754 load_nv17_hw_sequencer_ucode(dev, bios);
6755
6756 if (bios->execute) {
6757 bios->fp.last_script_invoc = 0;
6758 bios->fp.lvds_init_run = false;
6759 }
6760
6761 parse_init_tables(bios);
6762
6763 /*
6764 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6765 * parser will run this right after the init tables, the binary
6766 * driver appears to run it at some point later.
6767 */
6768 if (bios->some_script_ptr) {
6769 struct init_exec iexec = {true, false};
6770
6771 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6772 bios->some_script_ptr);
6773 parse_init_table(bios, bios->some_script_ptr, &iexec);
6774 }
6775
6776 if (dev_priv->card_type >= NV_50) {
6777 for (i = 0; i < bios->dcb.entries; i++) {
6778 nouveau_bios_run_display_table(dev,
6779 &bios->dcb.entry[i],
6780 0, 0);
6781 }
6782 }
6783
6784 return ret;
6785 }
6786
6787 static void
6788 nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6789 {
6790 struct drm_nouveau_private *dev_priv = dev->dev_private;
6791 struct nvbios *bios = &dev_priv->vbios;
6792 struct dcb_i2c_entry *entry;
6793 int i;
6794
6795 entry = &bios->dcb.i2c[0];
6796 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6797 nouveau_i2c_fini(dev, entry);
6798 }
6799
6800 static bool
6801 nouveau_bios_posted(struct drm_device *dev)
6802 {
6803 struct drm_nouveau_private *dev_priv = dev->dev_private;
6804 unsigned htotal;
6805
6806 if (dev_priv->card_type >= NV_50) {
6807 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6808 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6809 return false;
6810 return true;
6811 }
6812
6813 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6814 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6815 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6816 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6817 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6818
6819 return (htotal != 0);
6820 }
6821
6822 int
6823 nouveau_bios_init(struct drm_device *dev)
6824 {
6825 struct drm_nouveau_private *dev_priv = dev->dev_private;
6826 struct nvbios *bios = &dev_priv->vbios;
6827 int ret;
6828
6829 if (!NVInitVBIOS(dev))
6830 return -ENODEV;
6831
6832 ret = nouveau_parse_vbios_struct(dev);
6833 if (ret)
6834 return ret;
6835
6836 ret = parse_dcb_table(dev, bios);
6837 if (ret)
6838 return ret;
6839
6840 fixup_legacy_i2c(bios);
6841 fixup_legacy_connector(bios);
6842
6843 if (!bios->major_version) /* we don't run version 0 bios */
6844 return 0;
6845
6846 /* init script execution disabled */
6847 bios->execute = false;
6848
6849 /* ... unless card isn't POSTed already */
6850 if (!nouveau_bios_posted(dev)) {
6851 NV_INFO(dev, "Adaptor not initialised, "
6852 "running VBIOS init tables.\n");
6853 bios->execute = true;
6854 }
6855 if (nouveau_force_post)
6856 bios->execute = true;
6857
6858 ret = nouveau_run_vbios_init(dev);
6859 if (ret)
6860 return ret;
6861
6862 /* feature_byte on BMP is poor, but init always sets CR4B */
6863 if (bios->major_version < 5)
6864 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6865
6866 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6867 if (bios->is_mobile || bios->major_version >= 5)
6868 ret = parse_fp_mode_table(dev, bios);
6869
6870 /* allow subsequent scripts to execute */
6871 bios->execute = true;
6872
6873 return 0;
6874 }
6875
6876 void
6877 nouveau_bios_takedown(struct drm_device *dev)
6878 {
6879 nouveau_bios_i2c_devices_takedown(dev);
6880 }
(deprecated) Btrfs devel tree