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serial: max310x: Add MAX14830 support
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / max310x.c
blob4ab5b272a593e37320ab5f6e10b0937a207bb904
1 /*
2 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
3 *
4 * Copyright (C) 2012-2013 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/bitops.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/regmap.h>
25 #include <linux/gpio.h>
26 #include <linux/spi/spi.h>
27
28 #include <linux/platform_data/max310x.h>
29
30 #define MAX310X_NAME "max310x"
31 #define MAX310X_MAJOR 204
32 #define MAX310X_MINOR 209
33
34 /* MAX310X register definitions */
35 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
36 #define MAX310X_THR_REG (0x00) /* TX FIFO */
37 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
38 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
39 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
40 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
41 #define MAX310X_REG_05 (0x05)
42 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
43 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
44 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
45 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
46 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
47 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
48 #define MAX310X_LCR_REG (0x0b) /* LCR */
49 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
50 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
51 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
52 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
53 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
54 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
55 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
56 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
57 #define MAX310X_XON1_REG (0x14) /* XON1 character */
58 #define MAX310X_XON2_REG (0x15) /* XON2 character */
59 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
60 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
63 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
64 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
65 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
66 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
67 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
68 #define MAX310X_REG_1F (0x1f)
69
70 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
71
72 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
74
75 /* Extended registers */
76 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
77
78 /* IRQ register bits */
79 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
80 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
81 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
82 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
83 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
84 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
85 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
86 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
87
88 /* LSR register bits */
89 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
90 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
91 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
92 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
93 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
94 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
95 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
96
97 /* Special character register bits */
98 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
99 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
100 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
101 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
102 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
103 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
104
105 /* Status register bits */
106 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
107 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
108 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
109 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
110 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
111 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
112
113 /* MODE1 register bits */
114 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
115 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
116 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
117 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
118 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
119 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
120 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
121 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
122
123 /* MODE2 register bits */
124 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
125 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
126 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
127 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
128 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
129 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
130 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
131 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
132
133 /* LCR register bits */
134 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
135 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
136 *
137 * Word length bits table:
138 * 00 -> 5 bit words
139 * 01 -> 6 bit words
140 * 10 -> 7 bit words
141 * 11 -> 8 bit words
142 */
143 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
144 *
145 * STOP length bit table:
146 * 0 -> 1 stop bit
147 * 1 -> 1-1.5 stop bits if
148 * word length is 5,
149 * 2 stop bits otherwise
150 */
151 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
152 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
153 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
154 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
155 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
156 #define MAX310X_LCR_WORD_LEN_5 (0x00)
157 #define MAX310X_LCR_WORD_LEN_6 (0x01)
158 #define MAX310X_LCR_WORD_LEN_7 (0x02)
159 #define MAX310X_LCR_WORD_LEN_8 (0x03)
160
161 /* IRDA register bits */
162 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
163 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
164 #define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
165 #define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
166 #define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
167 #define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
168
169 /* Flow control trigger level register masks */
170 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
171 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
172 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
173 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
174
175 /* FIFO interrupt trigger level register masks */
176 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
177 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
178 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
179 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
180
181 /* Flow control register bits */
182 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
183 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
184 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
185 * are used in conjunction with
186 * XOFF2 for definition of
187 * special character */
188 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
189 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
190 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
191 *
192 * SWFLOW bits 1 & 0 table:
193 * 00 -> no transmitter flow
194 * control
195 * 01 -> receiver compares
196 * XON2 and XOFF2
197 * and controls
198 * transmitter
199 * 10 -> receiver compares
200 * XON1 and XOFF1
201 * and controls
202 * transmitter
203 * 11 -> receiver compares
204 * XON1, XON2, XOFF1 and
205 * XOFF2 and controls
206 * transmitter
207 */
208 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
209 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
210 *
211 * SWFLOW bits 3 & 2 table:
212 * 00 -> no received flow
213 * control
214 * 01 -> transmitter generates
215 * XON2 and XOFF2
216 * 10 -> transmitter generates
217 * XON1 and XOFF1
218 * 11 -> transmitter generates
219 * XON1, XON2, XOFF1 and
220 * XOFF2
221 */
222
223 /* GPIO configuration register bits */
224 #define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
225 #define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
226 #define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
227 #define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
228 #define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
229 #define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
230 #define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
231 #define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
232
233 /* GPIO DATA register bits */
234 #define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
235 #define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
236 #define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
237 #define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
238 #define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
239 #define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
240 #define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
241 #define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
242
243 /* PLL configuration register masks */
244 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
245 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
246
247 /* Baud rate generator configuration register bits */
248 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
249 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
250
251 /* Clock source register bits */
252 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
253 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
254 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
255 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
256 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
257
258 /* Global commands */
259 #define MAX310X_EXTREG_ENBL (0xce)
260 #define MAX310X_EXTREG_DSBL (0xcd)
261
262 /* Misc definitions */
263 #define MAX310X_FIFO_SIZE (128)
264 #define MAX310x_REV_MASK (0xfc)
265
266 /* MAX3107 specific */
267 #define MAX3107_REV_ID (0xa0)
268
269 /* MAX3109 specific */
270 #define MAX3109_REV_ID (0xc0)
271
272 /* MAX14830 specific */
273 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
274 #define MAX14830_REV_ID (0xb0)
275
276 struct max310x_devtype {
277 char name[9];
278 int nr;
279 int (*detect)(struct device *);
280 void (*power)(struct uart_port *, int);
281 };
282
283 struct max310x_one {
284 struct uart_port port;
285 struct work_struct tx_work;
286 };
287
288 struct max310x_port {
289 struct uart_driver uart;
290 struct max310x_devtype *devtype;
291 struct regmap *regmap;
292 struct regmap_config regcfg;
293 struct mutex mutex;
294 struct max310x_pdata *pdata;
295 int gpio_used;
296 #ifdef CONFIG_GPIOLIB
297 struct gpio_chip gpio;
298 #endif
299 struct max310x_one p[0];
300 };
301
302 static u8 max310x_port_read(struct uart_port *port, u8 reg)
303 {
304 struct max310x_port *s = dev_get_drvdata(port->dev);
305 unsigned int val = 0;
306
307 regmap_read(s->regmap, port->iobase + reg, &val);
308
309 return val;
310 }
311
312 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
313 {
314 struct max310x_port *s = dev_get_drvdata(port->dev);
315
316 regmap_write(s->regmap, port->iobase + reg, val);
317 }
318
319 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
320 {
321 struct max310x_port *s = dev_get_drvdata(port->dev);
322
323 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
324 }
325
326 static int max3107_detect(struct device *dev)
327 {
328 struct max310x_port *s = dev_get_drvdata(dev);
329 unsigned int val = 0;
330 int ret;
331
332 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
333 if (ret)
334 return ret;
335
336 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
337 dev_err(dev,
338 "%s ID 0x%02x does not match\n", s->devtype->name, val);
339 return -ENODEV;
340 }
341
342 return 0;
343 }
344
345 static int max3108_detect(struct device *dev)
346 {
347 struct max310x_port *s = dev_get_drvdata(dev);
348 unsigned int val = 0;
349 int ret;
350
351 /* MAX3108 have not REV ID register, we just check default value
352 * from clocksource register to make sure everything works.
353 */
354 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
355 if (ret)
356 return ret;
357
358 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
359 dev_err(dev, "%s not present\n", s->devtype->name);
360 return -ENODEV;
361 }
362
363 return 0;
364 }
365
366 static int max3109_detect(struct device *dev)
367 {
368 struct max310x_port *s = dev_get_drvdata(dev);
369 unsigned int val = 0;
370 int ret;
371
372 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
373 if (ret)
374 return ret;
375
376 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
377 dev_err(dev,
378 "%s ID 0x%02x does not match\n", s->devtype->name, val);
379 return -ENODEV;
380 }
381
382 return 0;
383 }
384
385 static void max310x_power(struct uart_port *port, int on)
386 {
387 max310x_port_update(port, MAX310X_MODE1_REG,
388 MAX310X_MODE1_FORCESLEEP_BIT,
389 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
390 if (on)
391 msleep(50);
392 }
393
394 static int max14830_detect(struct device *dev)
395 {
396 struct max310x_port *s = dev_get_drvdata(dev);
397 unsigned int val = 0;
398 int ret;
399
400 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
401 MAX310X_EXTREG_ENBL);
402 if (ret)
403 return ret;
404
405 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
406 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
407 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
408 dev_err(dev,
409 "%s ID 0x%02x does not match\n", s->devtype->name, val);
410 return -ENODEV;
411 }
412
413 return 0;
414 }
415
416 static void max14830_power(struct uart_port *port, int on)
417 {
418 max310x_port_update(port, MAX310X_BRGCFG_REG,
419 MAX14830_BRGCFG_CLKDIS_BIT,
420 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
421 if (on)
422 msleep(50);
423 }
424
425 static const struct max310x_devtype max3107_devtype = {
426 .name = "MAX3107",
427 .nr = 1,
428 .detect = max3107_detect,
429 .power = max310x_power,
430 };
431
432 static const struct max310x_devtype max3108_devtype = {
433 .name = "MAX3108",
434 .nr = 1,
435 .detect = max3108_detect,
436 .power = max310x_power,
437 };
438
439 static const struct max310x_devtype max3109_devtype = {
440 .name = "MAX3109",
441 .nr = 2,
442 .detect = max3109_detect,
443 .power = max310x_power,
444 };
445
446 static const struct max310x_devtype max14830_devtype = {
447 .name = "MAX14830",
448 .nr = 4,
449 .detect = max14830_detect,
450 .power = max14830_power,
451 };
452
453 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
454 {
455 switch (reg & 0x1f) {
456 case MAX310X_IRQSTS_REG:
457 case MAX310X_LSR_IRQSTS_REG:
458 case MAX310X_SPCHR_IRQSTS_REG:
459 case MAX310X_STS_IRQSTS_REG:
460 case MAX310X_TXFIFOLVL_REG:
461 case MAX310X_RXFIFOLVL_REG:
462 return false;
463 default:
464 break;
465 }
466
467 return true;
468 }
469
470 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
471 {
472 switch (reg & 0x1f) {
473 case MAX310X_RHR_REG:
474 case MAX310X_IRQSTS_REG:
475 case MAX310X_LSR_IRQSTS_REG:
476 case MAX310X_SPCHR_IRQSTS_REG:
477 case MAX310X_STS_IRQSTS_REG:
478 case MAX310X_TXFIFOLVL_REG:
479 case MAX310X_RXFIFOLVL_REG:
480 case MAX310X_GPIODATA_REG:
481 case MAX310X_BRGDIVLSB_REG:
482 case MAX310X_REG_05:
483 case MAX310X_REG_1F:
484 return true;
485 default:
486 break;
487 }
488
489 return false;
490 }
491
492 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
493 {
494 switch (reg & 0x1f) {
495 case MAX310X_RHR_REG:
496 case MAX310X_IRQSTS_REG:
497 case MAX310X_SPCHR_IRQSTS_REG:
498 case MAX310X_STS_IRQSTS_REG:
499 return true;
500 default:
501 break;
502 }
503
504 return false;
505 }
506
507 static void max310x_set_baud(struct uart_port *port, int baud)
508 {
509 unsigned int mode = 0, div = port->uartclk / baud;
510
511 if (!(div / 16)) {
512 /* Mode x2 */
513 mode = MAX310X_BRGCFG_2XMODE_BIT;
514 div = (port->uartclk * 2) / baud;
515 }
516
517 if (!(div / 16)) {
518 /* Mode x4 */
519 mode = MAX310X_BRGCFG_4XMODE_BIT;
520 div = (port->uartclk * 4) / baud;
521 }
522
523 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);
524 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);
525 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode);
526 }
527
528 static int max310x_update_best_err(unsigned long f, long *besterr)
529 {
530 /* Use baudrate 115200 for calculate error */
531 long err = f % (115200 * 16);
532
533 if ((*besterr < 0) || (*besterr > err)) {
534 *besterr = err;
535 return 0;
536 }
537
538 return 1;
539 }
540
541 static int max310x_set_ref_clk(struct max310x_port *s)
542 {
543 unsigned int div, clksrc, pllcfg = 0;
544 long besterr = -1;
545 unsigned long fdiv, fmul, bestfreq = s->pdata->frequency;
546
547 /* First, update error without PLL */
548 max310x_update_best_err(s->pdata->frequency, &besterr);
549
550 /* Try all possible PLL dividers */
551 for (div = 1; (div <= 63) && besterr; div++) {
552 fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div);
553
554 /* Try multiplier 6 */
555 fmul = fdiv * 6;
556 if ((fdiv >= 500000) && (fdiv <= 800000))
557 if (!max310x_update_best_err(fmul, &besterr)) {
558 pllcfg = (0 << 6) | div;
559 bestfreq = fmul;
560 }
561 /* Try multiplier 48 */
562 fmul = fdiv * 48;
563 if ((fdiv >= 850000) && (fdiv <= 1200000))
564 if (!max310x_update_best_err(fmul, &besterr)) {
565 pllcfg = (1 << 6) | div;
566 bestfreq = fmul;
567 }
568 /* Try multiplier 96 */
569 fmul = fdiv * 96;
570 if ((fdiv >= 425000) && (fdiv <= 1000000))
571 if (!max310x_update_best_err(fmul, &besterr)) {
572 pllcfg = (2 << 6) | div;
573 bestfreq = fmul;
574 }
575 /* Try multiplier 144 */
576 fmul = fdiv * 144;
577 if ((fdiv >= 390000) && (fdiv <= 667000))
578 if (!max310x_update_best_err(fmul, &besterr)) {
579 pllcfg = (3 << 6) | div;
580 bestfreq = fmul;
581 }
582 }
583
584 /* Configure clock source */
585 if (s->pdata->driver_flags & MAX310X_EXT_CLK)
586 clksrc = MAX310X_CLKSRC_EXTCLK_BIT;
587 else
588 clksrc = MAX310X_CLKSRC_CRYST_BIT;
589
590 /* Configure PLL */
591 if (pllcfg) {
592 clksrc |= MAX310X_CLKSRC_PLL_BIT;
593 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
594 } else
595 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
596
597 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
598
599 /* Wait for crystal */
600 if (pllcfg && !(s->pdata->driver_flags & MAX310X_EXT_CLK))
601 msleep(10);
602
603 return (int)bestfreq;
604 }
605
606 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
607 {
608 unsigned int sts, ch, flag;
609
610 if (unlikely(rxlen >= port->fifosize)) {
611 dev_warn_ratelimited(port->dev,
612 "Port %i: Possible RX FIFO overrun\n",
613 port->line);
614 port->icount.buf_overrun++;
615 /* Ensure sanity of RX level */
616 rxlen = port->fifosize;
617 }
618
619 while (rxlen--) {
620 ch = max310x_port_read(port, MAX310X_RHR_REG);
621 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
622
623 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
624 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
625
626 port->icount.rx++;
627 flag = TTY_NORMAL;
628
629 if (unlikely(sts)) {
630 if (sts & MAX310X_LSR_RXBRK_BIT) {
631 port->icount.brk++;
632 if (uart_handle_break(port))
633 continue;
634 } else if (sts & MAX310X_LSR_RXPAR_BIT)
635 port->icount.parity++;
636 else if (sts & MAX310X_LSR_FRERR_BIT)
637 port->icount.frame++;
638 else if (sts & MAX310X_LSR_RXOVR_BIT)
639 port->icount.overrun++;
640
641 sts &= port->read_status_mask;
642 if (sts & MAX310X_LSR_RXBRK_BIT)
643 flag = TTY_BREAK;
644 else if (sts & MAX310X_LSR_RXPAR_BIT)
645 flag = TTY_PARITY;
646 else if (sts & MAX310X_LSR_FRERR_BIT)
647 flag = TTY_FRAME;
648 else if (sts & MAX310X_LSR_RXOVR_BIT)
649 flag = TTY_OVERRUN;
650 }
651
652 if (uart_handle_sysrq_char(port, ch))
653 continue;
654
655 if (sts & port->ignore_status_mask)
656 continue;
657
658 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
659 }
660
661 tty_flip_buffer_push(&port->state->port);
662 }
663
664 static void max310x_handle_tx(struct uart_port *port)
665 {
666 struct circ_buf *xmit = &port->state->xmit;
667 unsigned int txlen, to_send;
668
669 if (unlikely(port->x_char)) {
670 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
671 port->icount.tx++;
672 port->x_char = 0;
673 return;
674 }
675
676 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
677 return;
678
679 /* Get length of data pending in circular buffer */
680 to_send = uart_circ_chars_pending(xmit);
681 if (likely(to_send)) {
682 /* Limit to size of TX FIFO */
683 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
684 txlen = port->fifosize - txlen;
685 to_send = (to_send > txlen) ? txlen : to_send;
686
687 /* Add data to send */
688 port->icount.tx += to_send;
689 while (to_send--) {
690 max310x_port_write(port, MAX310X_THR_REG,
691 xmit->buf[xmit->tail]);
692 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
693 };
694 }
695
696 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
697 uart_write_wakeup(port);
698 }
699
700 static void max310x_port_irq(struct max310x_port *s, int portno)
701 {
702 struct uart_port *port = &s->p[portno].port;
703
704 do {
705 unsigned int ists, lsr, rxlen;
706
707 /* Read IRQ status & RX FIFO level */
708 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
709 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
710 if (!ists && !rxlen)
711 break;
712
713 if (ists & MAX310X_IRQ_CTS_BIT) {
714 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
715 uart_handle_cts_change(port,
716 !!(lsr & MAX310X_LSR_CTS_BIT));
717 }
718 if (rxlen)
719 max310x_handle_rx(port, rxlen);
720 if (ists & MAX310X_IRQ_TXEMPTY_BIT) {
721 mutex_lock(&s->mutex);
722 max310x_handle_tx(port);
723 mutex_unlock(&s->mutex);
724 }
725 } while (1);
726 }
727
728 static irqreturn_t max310x_ist(int irq, void *dev_id)
729 {
730 struct max310x_port *s = (struct max310x_port *)dev_id;
731
732 if (s->uart.nr > 1) {
733 do {
734 unsigned int val = ~0;
735
736 WARN_ON_ONCE(regmap_read(s->regmap,
737 MAX310X_GLOBALIRQ_REG, &val));
738 val = ((1 << s->uart.nr) - 1) & ~val;
739 if (!val)
740 break;
741 max310x_port_irq(s, fls(val) - 1);
742 } while (1);
743 } else
744 max310x_port_irq(s, 0);
745
746 return IRQ_HANDLED;
747 }
748
749 static void max310x_wq_proc(struct work_struct *ws)
750 {
751 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
752 struct max310x_port *s = dev_get_drvdata(one->port.dev);
753
754 mutex_lock(&s->mutex);
755 max310x_handle_tx(&one->port);
756 mutex_unlock(&s->mutex);
757 }
758
759 static void max310x_start_tx(struct uart_port *port)
760 {
761 struct max310x_one *one = container_of(port, struct max310x_one, port);
762
763 if (!work_pending(&one->tx_work))
764 schedule_work(&one->tx_work);
765 }
766
767 static unsigned int max310x_tx_empty(struct uart_port *port)
768 {
769 unsigned int lvl, sts;
770
771 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
772 sts = max310x_port_read(port, MAX310X_IRQSTS_REG);
773
774 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0;
775 }
776
777 static unsigned int max310x_get_mctrl(struct uart_port *port)
778 {
779 /* DCD and DSR are not wired and CTS/RTS is handled automatically
780 * so just indicate DSR and CAR asserted
781 */
782 return TIOCM_DSR | TIOCM_CAR;
783 }
784
785 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
786 {
787 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
788 * so do nothing
789 */
790 }
791
792 static void max310x_break_ctl(struct uart_port *port, int break_state)
793 {
794 max310x_port_update(port, MAX310X_LCR_REG,
795 MAX310X_LCR_TXBREAK_BIT,
796 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
797 }
798
799 static void max310x_set_termios(struct uart_port *port,
800 struct ktermios *termios,
801 struct ktermios *old)
802 {
803 unsigned int lcr, flow = 0;
804 int baud;
805
806 /* Mask termios capabilities we don't support */
807 termios->c_cflag &= ~CMSPAR;
808
809 /* Word size */
810 switch (termios->c_cflag & CSIZE) {
811 case CS5:
812 lcr = MAX310X_LCR_WORD_LEN_5;
813 break;
814 case CS6:
815 lcr = MAX310X_LCR_WORD_LEN_6;
816 break;
817 case CS7:
818 lcr = MAX310X_LCR_WORD_LEN_7;
819 break;
820 case CS8:
821 default:
822 lcr = MAX310X_LCR_WORD_LEN_8;
823 break;
824 }
825
826 /* Parity */
827 if (termios->c_cflag & PARENB) {
828 lcr |= MAX310X_LCR_PARITY_BIT;
829 if (!(termios->c_cflag & PARODD))
830 lcr |= MAX310X_LCR_EVENPARITY_BIT;
831 }
832
833 /* Stop bits */
834 if (termios->c_cflag & CSTOPB)
835 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
836
837 /* Update LCR register */
838 max310x_port_write(port, MAX310X_LCR_REG, lcr);
839
840 /* Set read status mask */
841 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
842 if (termios->c_iflag & INPCK)
843 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
844 MAX310X_LSR_FRERR_BIT;
845 if (termios->c_iflag & (BRKINT | PARMRK))
846 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
847
848 /* Set status ignore mask */
849 port->ignore_status_mask = 0;
850 if (termios->c_iflag & IGNBRK)
851 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
852 if (!(termios->c_cflag & CREAD))
853 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
854 MAX310X_LSR_RXOVR_BIT |
855 MAX310X_LSR_FRERR_BIT |
856 MAX310X_LSR_RXBRK_BIT;
857
858 /* Configure flow control */
859 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
860 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
861 if (termios->c_cflag & CRTSCTS)
862 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
863 MAX310X_FLOWCTRL_AUTORTS_BIT;
864 if (termios->c_iflag & IXON)
865 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
866 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
867 if (termios->c_iflag & IXOFF)
868 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
869 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
870 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
871
872 /* Get baud rate generator configuration */
873 baud = uart_get_baud_rate(port, termios, old,
874 port->uartclk / 16 / 0xffff,
875 port->uartclk / 4);
876
877 /* Setup baudrate generator */
878 max310x_set_baud(port, baud);
879
880 /* Update timeout according to new baud rate */
881 uart_update_timeout(port, termios->c_cflag, baud);
882 }
883
884 static int max310x_startup(struct uart_port *port)
885 {
886 unsigned int val, line = port->line;
887 struct max310x_port *s = dev_get_drvdata(port->dev);
888
889 s->devtype->power(port, 1);
890
891 /* Configure baud rate, 9600 as default */
892 max310x_set_baud(port, 9600);
893
894 /* Configure LCR register, 8N1 mode by default */
895 max310x_port_write(port, MAX310X_LCR_REG, MAX310X_LCR_WORD_LEN_8);
896
897 /* Configure MODE1 register */
898 max310x_port_update(port, MAX310X_MODE1_REG,
899 MAX310X_MODE1_TRNSCVCTRL_BIT,
900 (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL)
901 ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0);
902
903 /* Configure MODE2 register */
904 val = MAX310X_MODE2_RXEMPTINV_BIT;
905 if (s->pdata->uart_flags[line] & MAX310X_LOOPBACK)
906 val |= MAX310X_MODE2_LOOPBACK_BIT;
907 if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS)
908 val |= MAX310X_MODE2_ECHOSUPR_BIT;
909
910 /* Reset FIFOs */
911 val |= MAX310X_MODE2_FIFORST_BIT;
912 max310x_port_write(port, MAX310X_MODE2_REG, val);
913 max310x_port_update(port, MAX310X_MODE2_REG,
914 MAX310X_MODE2_FIFORST_BIT, 0);
915
916 /* Configure flow control levels */
917 /* Flow control halt level 96, resume level 48 */
918 max310x_port_write(port, MAX310X_FLOWLVL_REG,
919 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
920
921 /* Clear IRQ status register */
922 max310x_port_read(port, MAX310X_IRQSTS_REG);
923
924 /* Enable RX, TX, CTS change interrupts */
925 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
926 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
927
928 return 0;
929 }
930
931 static void max310x_shutdown(struct uart_port *port)
932 {
933 struct max310x_port *s = dev_get_drvdata(port->dev);
934
935 /* Disable all interrupts */
936 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
937
938 s->devtype->power(port, 0);
939 }
940
941 static const char *max310x_type(struct uart_port *port)
942 {
943 struct max310x_port *s = dev_get_drvdata(port->dev);
944
945 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
946 }
947
948 static int max310x_request_port(struct uart_port *port)
949 {
950 /* Do nothing */
951 return 0;
952 }
953
954 static void max310x_config_port(struct uart_port *port, int flags)
955 {
956 if (flags & UART_CONFIG_TYPE)
957 port->type = PORT_MAX310X;
958 }
959
960 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
961 {
962 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
963 return -EINVAL;
964 if (s->irq != port->irq)
965 return -EINVAL;
966
967 return 0;
968 }
969
970 static void max310x_null_void(struct uart_port *port)
971 {
972 /* Do nothing */
973 }
974
975 static const struct uart_ops max310x_ops = {
976 .tx_empty = max310x_tx_empty,
977 .set_mctrl = max310x_set_mctrl,
978 .get_mctrl = max310x_get_mctrl,
979 .stop_tx = max310x_null_void,
980 .start_tx = max310x_start_tx,
981 .stop_rx = max310x_null_void,
982 .enable_ms = max310x_null_void,
983 .break_ctl = max310x_break_ctl,
984 .startup = max310x_startup,
985 .shutdown = max310x_shutdown,
986 .set_termios = max310x_set_termios,
987 .type = max310x_type,
988 .request_port = max310x_request_port,
989 .release_port = max310x_null_void,
990 .config_port = max310x_config_port,
991 .verify_port = max310x_verify_port,
992 };
993
994 static int __maybe_unused max310x_suspend(struct spi_device *spi,
995 pm_message_t state)
996 {
997 struct max310x_port *s = dev_get_drvdata(&spi->dev);
998 int i;
999
1000 for (i = 0; i < s->uart.nr; i++) {
1001 uart_suspend_port(&s->uart, &s->p[i].port);
1002 s->devtype->power(&s->p[i].port, 0);
1003 }
1004
1005 return 0;
1006 }
1007
1008 static int __maybe_unused max310x_resume(struct spi_device *spi)
1009 {
1010 struct max310x_port *s = dev_get_drvdata(&spi->dev);
1011 int i;
1012
1013 for (i = 0; i < s->uart.nr; i++) {
1014 s->devtype->power(&s->p[i].port, 1);
1015 uart_resume_port(&s->uart, &s->p[i].port);
1016 }
1017
1018 return 0;
1019 }
1020
1021 #ifdef CONFIG_GPIOLIB
1022 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1023 {
1024 unsigned int val;
1025 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1026 struct uart_port *port = &s->p[offset / 4].port;
1027
1028 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1029
1030 return !!((val >> 4) & (1 << (offset % 4)));
1031 }
1032
1033 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1034 {
1035 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1036 struct uart_port *port = &s->p[offset / 4].port;
1037
1038 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1039 value ? 1 << (offset % 4) : 0);
1040 }
1041
1042 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1043 {
1044 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1045 struct uart_port *port = &s->p[offset / 4].port;
1046
1047 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1048
1049 return 0;
1050 }
1051
1052 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1053 unsigned offset, int value)
1054 {
1055 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1056 struct uart_port *port = &s->p[offset / 4].port;
1057
1058 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1059 value ? 1 << (offset % 4) : 0);
1060 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1061 1 << (offset % 4));
1062
1063 return 0;
1064 }
1065 #endif
1066
1067 static int max310x_probe(struct device *dev, int is_spi,
1068 struct max310x_devtype *devtype, int irq)
1069 {
1070 struct max310x_port *s;
1071 struct max310x_pdata *pdata = dev_get_platdata(dev);
1072 int i, ret, uartclk;
1073
1074 /* Check for IRQ */
1075 if (irq <= 0) {
1076 dev_err(dev, "No IRQ specified\n");
1077 return -ENOTSUPP;
1078 }
1079
1080 if (!pdata) {
1081 dev_err(dev, "No platform data supplied\n");
1082 return -EINVAL;
1083 }
1084
1085 /* Alloc port structure */
1086 s = devm_kzalloc(dev, sizeof(*s) +
1087 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1088 if (!s) {
1089 dev_err(dev, "Error allocating port structure\n");
1090 return -ENOMEM;
1091 }
1092
1093 /* Check input frequency */
1094 if ((pdata->driver_flags & MAX310X_EXT_CLK) &&
1095 ((pdata->frequency < 500000) || (pdata->frequency > 35000000)))
1096 goto err_freq;
1097 /* Check frequency for quartz */
1098 if (!(pdata->driver_flags & MAX310X_EXT_CLK) &&
1099 ((pdata->frequency < 1000000) || (pdata->frequency > 4000000)))
1100 goto err_freq;
1101
1102 s->pdata = pdata;
1103 s->devtype = devtype;
1104 dev_set_drvdata(dev, s);
1105
1106 mutex_init(&s->mutex);
1107
1108 /* Setup regmap */
1109 s->regcfg.reg_bits = 8;
1110 s->regcfg.val_bits = 8;
1111 s->regcfg.read_flag_mask = 0x00;
1112 s->regcfg.write_flag_mask = 0x80;
1113 s->regcfg.cache_type = REGCACHE_RBTREE;
1114 s->regcfg.writeable_reg = max310x_reg_writeable;
1115 s->regcfg.volatile_reg = max310x_reg_volatile;
1116 s->regcfg.precious_reg = max310x_reg_precious;
1117 s->regcfg.max_register = devtype->nr * 0x20 - 1;
1118
1119 if (IS_ENABLED(CONFIG_SPI_MASTER) && is_spi) {
1120 struct spi_device *spi = to_spi_device(dev);
1121
1122 s->regmap = devm_regmap_init_spi(spi, &s->regcfg);
1123 } else
1124 return -ENOTSUPP;
1125
1126 if (IS_ERR(s->regmap)) {
1127 dev_err(dev, "Failed to initialize register map\n");
1128 return PTR_ERR(s->regmap);
1129 }
1130
1131 /* Board specific configure */
1132 if (s->pdata->init)
1133 s->pdata->init();
1134
1135 /* Check device to ensure we are talking to what we expect */
1136 ret = devtype->detect(dev);
1137 if (ret)
1138 return ret;
1139
1140 for (i = 0; i < devtype->nr; i++) {
1141 unsigned int offs = i << 5;
1142
1143 /* Reset port */
1144 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1145 MAX310X_MODE2_RST_BIT);
1146 /* Clear port reset */
1147 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1148
1149 /* Wait for port startup */
1150 do {
1151 regmap_read(s->regmap,
1152 MAX310X_BRGDIVLSB_REG + offs, &ret);
1153 } while (ret != 0x01);
1154
1155 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1156 MAX310X_MODE1_AUTOSLEEP_BIT,
1157 MAX310X_MODE1_AUTOSLEEP_BIT);
1158 }
1159
1160 uartclk = max310x_set_ref_clk(s);
1161 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1162
1163 /* Register UART driver */
1164 s->uart.owner = THIS_MODULE;
1165 s->uart.dev_name = "ttyMAX";
1166 s->uart.major = MAX310X_MAJOR;
1167 s->uart.minor = MAX310X_MINOR;
1168 s->uart.nr = devtype->nr;
1169 ret = uart_register_driver(&s->uart);
1170 if (ret) {
1171 dev_err(dev, "Registering UART driver failed\n");
1172 return ret;
1173 }
1174
1175 for (i = 0; i < devtype->nr; i++) {
1176 /* Initialize port data */
1177 s->p[i].port.line = i;
1178 s->p[i].port.dev = dev;
1179 s->p[i].port.irq = irq;
1180 s->p[i].port.type = PORT_MAX310X;
1181 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1182 s->p[i].port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE |
1183 UPF_LOW_LATENCY;
1184 s->p[i].port.iotype = UPIO_PORT;
1185 s->p[i].port.iobase = i * 0x20;
1186 s->p[i].port.membase = (void __iomem *)~0;
1187 s->p[i].port.uartclk = uartclk;
1188 s->p[i].port.ops = &max310x_ops;
1189 /* Disable all interrupts */
1190 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1191 /* Clear IRQ status register */
1192 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1193 /* Enable IRQ pin */
1194 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1195 MAX310X_MODE1_IRQSEL_BIT,
1196 MAX310X_MODE1_IRQSEL_BIT);
1197 /* Initialize queue for start TX */
1198 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1199 /* Register port */
1200 uart_add_one_port(&s->uart, &s->p[i].port);
1201 /* Go to suspend mode */
1202 devtype->power(&s->p[i].port, 0);
1203 }
1204
1205 #ifdef CONFIG_GPIOLIB
1206 /* Setup GPIO cotroller */
1207 if (s->pdata->gpio_base) {
1208 s->gpio.owner = THIS_MODULE;
1209 s->gpio.dev = dev;
1210 s->gpio.label = dev_name(dev);
1211 s->gpio.direction_input = max310x_gpio_direction_input;
1212 s->gpio.get = max310x_gpio_get;
1213 s->gpio.direction_output= max310x_gpio_direction_output;
1214 s->gpio.set = max310x_gpio_set;
1215 s->gpio.base = s->pdata->gpio_base;
1216 s->gpio.ngpio = devtype->nr * 4;
1217 s->gpio.can_sleep = 1;
1218 if (!gpiochip_add(&s->gpio))
1219 s->gpio_used = 1;
1220 } else
1221 dev_info(dev, "GPIO support not enabled\n");
1222 #endif
1223
1224 /* Setup interrupt */
1225 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1226 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1227 dev_name(dev), s);
1228 if (ret) {
1229 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1230 #ifdef CONFIG_GPIOLIB
1231 if (s->gpio_used)
1232 WARN_ON(gpiochip_remove(&s->gpio));
1233 #endif
1234 }
1235
1236 return ret;
1237
1238 err_freq:
1239 dev_err(dev, "Frequency parameter incorrect\n");
1240 return -EINVAL;
1241 }
1242
1243 static int max310x_remove(struct device *dev)
1244 {
1245 struct max310x_port *s = dev_get_drvdata(dev);
1246 int i, ret = 0;
1247
1248 for (i = 0; i < s->uart.nr; i++) {
1249 cancel_work_sync(&s->p[i].tx_work);
1250 uart_remove_one_port(&s->uart, &s->p[i].port);
1251 s->devtype->power(&s->p[i].port, 0);
1252 }
1253
1254 uart_unregister_driver(&s->uart);
1255
1256 #ifdef CONFIG_GPIOLIB
1257 if (s->gpio_used)
1258 ret = gpiochip_remove(&s->gpio);
1259 #endif
1260
1261 if (s->pdata->exit)
1262 s->pdata->exit();
1263
1264 return ret;
1265 }
1266
1267 #ifdef CONFIG_SPI_MASTER
1268 static int max310x_spi_probe(struct spi_device *spi)
1269 {
1270 struct max310x_devtype *devtype =
1271 (struct max310x_devtype *)spi_get_device_id(spi)->driver_data;
1272 int ret;
1273
1274 /* Setup SPI bus */
1275 spi->bits_per_word = 8;
1276 spi->mode = spi->mode ? : SPI_MODE_0;
1277 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1278 ret = spi_setup(spi);
1279 if (ret) {
1280 dev_err(&spi->dev, "SPI setup failed\n");
1281 return ret;
1282 }
1283
1284 return max310x_probe(&spi->dev, 1, devtype, spi->irq);
1285 }
1286
1287 static int max310x_spi_remove(struct spi_device *spi)
1288 {
1289 return max310x_remove(&spi->dev);
1290 }
1291
1292 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1293
1294 static const struct spi_device_id max310x_id_table[] = {
1295 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1296 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1297 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1298 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1299 { }
1300 };
1301 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1302
1303 static struct spi_driver max310x_uart_driver = {
1304 .driver = {
1305 .name = MAX310X_NAME,
1306 .owner = THIS_MODULE,
1307 .pm = &max310x_pm_ops,
1308 },
1309 .probe = max310x_spi_probe,
1310 .remove = max310x_spi_remove,
1311 .id_table = max310x_id_table,
1312 };
1313 module_spi_driver(max310x_uart_driver);
1314 #endif
1315
1316 MODULE_LICENSE("GPL");
1317 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1318 MODULE_DESCRIPTION("MAX310X serial driver");
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