2 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
4 * Copyright (C) 2011-2012 International Business Machines Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 only.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 * Author: Kent Yoder <yoder1@us.ibm.com>
22 #include <crypto/internal/hash.h>
23 #include <crypto/sha.h>
24 #include <linux/module.h>
27 #include "nx_csbcpb.h"
31 static int nx_sha512_init(struct shash_desc
*desc
)
33 struct sha512_state
*sctx
= shash_desc_ctx(desc
);
34 struct nx_crypto_ctx
*nx_ctx
= crypto_tfm_ctx(&desc
->tfm
->base
);
38 nx_ctx_init(nx_ctx
, HCOP_FC_SHA
);
40 memset(sctx
, 0, sizeof *sctx
);
42 nx_ctx
->ap
= &nx_ctx
->props
[NX_PROPS_SHA512
];
44 NX_CPB_SET_DIGEST_SIZE(nx_ctx
->csbcpb
, NX_DS_SHA512
);
46 len
= SHA512_DIGEST_SIZE
;
47 rc
= nx_sha_build_sg_list(nx_ctx
, nx_ctx
->out_sg
,
53 if (rc
|| len
!= SHA512_DIGEST_SIZE
)
56 sctx
->state
[0] = __cpu_to_be64(SHA512_H0
);
57 sctx
->state
[1] = __cpu_to_be64(SHA512_H1
);
58 sctx
->state
[2] = __cpu_to_be64(SHA512_H2
);
59 sctx
->state
[3] = __cpu_to_be64(SHA512_H3
);
60 sctx
->state
[4] = __cpu_to_be64(SHA512_H4
);
61 sctx
->state
[5] = __cpu_to_be64(SHA512_H5
);
62 sctx
->state
[6] = __cpu_to_be64(SHA512_H6
);
63 sctx
->state
[7] = __cpu_to_be64(SHA512_H7
);
70 static int nx_sha512_update(struct shash_desc
*desc
, const u8
*data
,
73 struct sha512_state
*sctx
= shash_desc_ctx(desc
);
74 struct nx_crypto_ctx
*nx_ctx
= crypto_tfm_ctx(&desc
->tfm
->base
);
75 struct nx_csbcpb
*csbcpb
= (struct nx_csbcpb
*)nx_ctx
->csbcpb
;
76 u64 to_process
, leftover
= 0, total
;
77 unsigned long irq_flags
;
80 u64 buf_len
= (sctx
->count
[0] % SHA512_BLOCK_SIZE
);
82 spin_lock_irqsave(&nx_ctx
->lock
, irq_flags
);
84 /* 2 cases for total data len:
85 * 1: < SHA512_BLOCK_SIZE: copy into state, return 0
86 * 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
88 total
= (sctx
->count
[0] % SHA512_BLOCK_SIZE
) + len
;
89 if (total
< SHA512_BLOCK_SIZE
) {
90 memcpy(sctx
->buf
+ buf_len
, data
, len
);
91 sctx
->count
[0] += len
;
95 memcpy(csbcpb
->cpb
.sha512
.message_digest
, sctx
->state
, SHA512_DIGEST_SIZE
);
96 NX_CPB_FDM(csbcpb
) |= NX_FDM_INTERMEDIATE
;
97 NX_CPB_FDM(csbcpb
) |= NX_FDM_CONTINUATION
;
101 * to_process: the SHA512_BLOCK_SIZE data chunk to process in
102 * this update. This value is also restricted by the sg list
105 to_process
= total
- leftover
;
106 to_process
= to_process
& ~(SHA512_BLOCK_SIZE
- 1);
107 leftover
= total
- to_process
;
111 rc
= nx_sha_build_sg_list(nx_ctx
, nx_ctx
->in_sg
,
117 if (rc
|| data_len
!= buf_len
)
121 data_len
= to_process
- buf_len
;
122 rc
= nx_sha_build_sg_list(nx_ctx
, nx_ctx
->in_sg
,
128 if (rc
|| data_len
!= (to_process
- buf_len
))
131 to_process
= (data_len
+ buf_len
);
132 leftover
= total
- to_process
;
135 * we've hit the nx chip previously and we're updating
136 * again, so copy over the partial digest.
138 memcpy(csbcpb
->cpb
.sha512
.input_partial_digest
,
139 csbcpb
->cpb
.sha512
.message_digest
,
142 if (!nx_ctx
->op
.inlen
|| !nx_ctx
->op
.outlen
) {
147 rc
= nx_hcall_sync(nx_ctx
, &nx_ctx
->op
,
148 desc
->flags
& CRYPTO_TFM_REQ_MAY_SLEEP
);
152 atomic_inc(&(nx_ctx
->stats
->sha512_ops
));
155 data
+= to_process
- buf_len
;
158 } while (leftover
>= SHA512_BLOCK_SIZE
);
160 /* copy the leftover back into the state struct */
162 memcpy(sctx
->buf
, data
, leftover
);
163 sctx
->count
[0] += len
;
164 memcpy(sctx
->state
, csbcpb
->cpb
.sha512
.message_digest
, SHA512_DIGEST_SIZE
);
166 spin_unlock_irqrestore(&nx_ctx
->lock
, irq_flags
);
170 static int nx_sha512_final(struct shash_desc
*desc
, u8
*out
)
172 struct sha512_state
*sctx
= shash_desc_ctx(desc
);
173 struct nx_crypto_ctx
*nx_ctx
= crypto_tfm_ctx(&desc
->tfm
->base
);
174 struct nx_csbcpb
*csbcpb
= (struct nx_csbcpb
*)nx_ctx
->csbcpb
;
176 unsigned long irq_flags
;
180 spin_lock_irqsave(&nx_ctx
->lock
, irq_flags
);
182 /* final is represented by continuing the operation and indicating that
183 * this is not an intermediate operation */
184 if (sctx
->count
[0] >= SHA512_BLOCK_SIZE
) {
185 /* we've hit the nx chip previously, now we're finalizing,
186 * so copy over the partial digest */
187 memcpy(csbcpb
->cpb
.sha512
.input_partial_digest
, sctx
->state
,
189 NX_CPB_FDM(csbcpb
) &= ~NX_FDM_INTERMEDIATE
;
190 NX_CPB_FDM(csbcpb
) |= NX_FDM_CONTINUATION
;
192 NX_CPB_FDM(csbcpb
) &= ~NX_FDM_INTERMEDIATE
;
193 NX_CPB_FDM(csbcpb
) &= ~NX_FDM_CONTINUATION
;
196 NX_CPB_FDM(csbcpb
) &= ~NX_FDM_INTERMEDIATE
;
198 count0
= sctx
->count
[0] * 8;
200 csbcpb
->cpb
.sha512
.message_bit_length_lo
= count0
;
202 len
= sctx
->count
[0] & (SHA512_BLOCK_SIZE
- 1);
203 rc
= nx_sha_build_sg_list(nx_ctx
, nx_ctx
->in_sg
,
209 if (rc
|| len
!= (sctx
->count
[0] & (SHA512_BLOCK_SIZE
- 1)))
212 len
= SHA512_DIGEST_SIZE
;
213 rc
= nx_sha_build_sg_list(nx_ctx
, nx_ctx
->out_sg
,
222 if (!nx_ctx
->op
.outlen
) {
227 rc
= nx_hcall_sync(nx_ctx
, &nx_ctx
->op
,
228 desc
->flags
& CRYPTO_TFM_REQ_MAY_SLEEP
);
232 atomic_inc(&(nx_ctx
->stats
->sha512_ops
));
233 atomic64_add(sctx
->count
[0], &(nx_ctx
->stats
->sha512_bytes
));
235 memcpy(out
, csbcpb
->cpb
.sha512
.message_digest
, SHA512_DIGEST_SIZE
);
237 spin_unlock_irqrestore(&nx_ctx
->lock
, irq_flags
);
241 static int nx_sha512_export(struct shash_desc
*desc
, void *out
)
243 struct sha512_state
*sctx
= shash_desc_ctx(desc
);
245 memcpy(out
, sctx
, sizeof(*sctx
));
250 static int nx_sha512_import(struct shash_desc
*desc
, const void *in
)
252 struct sha512_state
*sctx
= shash_desc_ctx(desc
);
254 memcpy(sctx
, in
, sizeof(*sctx
));
259 struct shash_alg nx_shash_sha512_alg
= {
260 .digestsize
= SHA512_DIGEST_SIZE
,
261 .init
= nx_sha512_init
,
262 .update
= nx_sha512_update
,
263 .final
= nx_sha512_final
,
264 .export
= nx_sha512_export
,
265 .import
= nx_sha512_import
,
266 .descsize
= sizeof(struct sha512_state
),
267 .statesize
= sizeof(struct sha512_state
),
269 .cra_name
= "sha512",
270 .cra_driver_name
= "sha512-nx",
272 .cra_flags
= CRYPTO_ALG_TYPE_SHASH
,
273 .cra_blocksize
= SHA512_BLOCK_SIZE
,
274 .cra_module
= THIS_MODULE
,
275 .cra_ctxsize
= sizeof(struct nx_crypto_ctx
),
276 .cra_init
= nx_crypto_ctx_sha_init
,
277 .cra_exit
= nx_crypto_ctx_exit
,