3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
28 #include "zd_ieee80211.h"
33 void zd_chip_init(struct zd_chip
*chip
,
34 struct net_device
*netdev
,
35 struct usb_interface
*intf
)
37 memset(chip
, 0, sizeof(*chip
));
38 mutex_init(&chip
->mutex
);
39 zd_usb_init(&chip
->usb
, netdev
, intf
);
40 zd_rf_init(&chip
->rf
);
43 void zd_chip_clear(struct zd_chip
*chip
)
45 ZD_ASSERT(!mutex_is_locked(&chip
->mutex
));
46 zd_usb_clear(&chip
->usb
);
47 zd_rf_clear(&chip
->rf
);
48 mutex_destroy(&chip
->mutex
);
49 ZD_MEMCLEAR(chip
, sizeof(*chip
));
52 static int scnprint_mac_oui(struct zd_chip
*chip
, char *buffer
, size_t size
)
54 u8
*addr
= zd_usb_to_netdev(&chip
->usb
)->dev_addr
;
55 return scnprintf(buffer
, size
, "%02x-%02x-%02x",
56 addr
[0], addr
[1], addr
[2]);
59 /* Prints an identifier line, which will support debugging. */
60 static int scnprint_id(struct zd_chip
*chip
, char *buffer
, size_t size
)
64 i
= scnprintf(buffer
, size
, "zd1211%s chip ",
65 zd_chip_is_zd1211b(chip
) ? "b" : "");
66 i
+= zd_usb_scnprint_id(&chip
->usb
, buffer
+i
, size
-i
);
67 i
+= scnprintf(buffer
+i
, size
-i
, " ");
68 i
+= scnprint_mac_oui(chip
, buffer
+i
, size
-i
);
69 i
+= scnprintf(buffer
+i
, size
-i
, " ");
70 i
+= zd_rf_scnprint_id(&chip
->rf
, buffer
+i
, size
-i
);
71 i
+= scnprintf(buffer
+i
, size
-i
, " pa%1x %c%c%c%c%c", chip
->pa_type
,
72 chip
->patch_cck_gain
? 'g' : '-',
73 chip
->patch_cr157
? '7' : '-',
74 chip
->patch_6m_band_edge
? '6' : '-',
75 chip
->new_phy_layout
? 'N' : '-',
76 chip
->al2230s_bit
? 'S' : '-');
80 static void print_id(struct zd_chip
*chip
)
84 scnprint_id(chip
, buffer
, sizeof(buffer
));
85 buffer
[sizeof(buffer
)-1] = 0;
86 dev_info(zd_chip_dev(chip
), "%s\n", buffer
);
89 static zd_addr_t
inc_addr(zd_addr_t addr
)
92 /* Control registers use byte addressing, but everything else uses word
94 if ((a
& 0xf000) == CR_START
)
101 /* Read a variable number of 32-bit values. Parameter count is not allowed to
102 * exceed USB_MAX_IOREAD32_COUNT.
104 int zd_ioread32v_locked(struct zd_chip
*chip
, u32
*values
, const zd_addr_t
*addr
,
109 zd_addr_t
*a16
= (zd_addr_t
*)NULL
;
111 unsigned int count16
;
113 if (count
> USB_MAX_IOREAD32_COUNT
)
116 /* Allocate a single memory block for values and addresses. */
118 a16
= (zd_addr_t
*) kmalloc(count16
* (sizeof(zd_addr_t
) + sizeof(u16
)),
121 dev_dbg_f(zd_chip_dev(chip
),
122 "error ENOMEM in allocation of a16\n");
126 v16
= (u16
*)(a16
+ count16
);
128 for (i
= 0; i
< count
; i
++) {
130 /* We read the high word always first. */
131 a16
[j
] = inc_addr(addr
[i
]);
135 r
= zd_ioread16v_locked(chip
, v16
, a16
, count16
);
137 dev_dbg_f(zd_chip_dev(chip
),
138 "error: zd_ioread16v_locked. Error number %d\n", r
);
142 for (i
= 0; i
< count
; i
++) {
144 values
[i
] = (v16
[j
] << 16) | v16
[j
+1];
152 int _zd_iowrite32v_locked(struct zd_chip
*chip
, const struct zd_ioreq32
*ioreqs
,
156 struct zd_ioreq16
*ioreqs16
;
157 unsigned int count16
;
159 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
163 if (count
> USB_MAX_IOWRITE32_COUNT
)
166 /* Allocate a single memory block for values and addresses. */
168 ioreqs16
= kmalloc(count16
* sizeof(struct zd_ioreq16
), GFP_KERNEL
);
171 dev_dbg_f(zd_chip_dev(chip
),
172 "error %d in ioreqs16 allocation\n", r
);
176 for (i
= 0; i
< count
; i
++) {
178 /* We write the high word always first. */
179 ioreqs16
[j
].value
= ioreqs
[i
].value
>> 16;
180 ioreqs16
[j
].addr
= inc_addr(ioreqs
[i
].addr
);
181 ioreqs16
[j
+1].value
= ioreqs
[i
].value
;
182 ioreqs16
[j
+1].addr
= ioreqs
[i
].addr
;
185 r
= zd_usb_iowrite16v(&chip
->usb
, ioreqs16
, count16
);
188 dev_dbg_f(zd_chip_dev(chip
),
189 "error %d in zd_usb_write16v\n", r
);
197 int zd_iowrite16a_locked(struct zd_chip
*chip
,
198 const struct zd_ioreq16
*ioreqs
, unsigned int count
)
201 unsigned int i
, j
, t
, max
;
203 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
204 for (i
= 0; i
< count
; i
+= j
+ t
) {
207 if (max
> USB_MAX_IOWRITE16_COUNT
)
208 max
= USB_MAX_IOWRITE16_COUNT
;
209 for (j
= 0; j
< max
; j
++) {
210 if (!ioreqs
[i
+j
].addr
) {
216 r
= zd_usb_iowrite16v(&chip
->usb
, &ioreqs
[i
], j
);
218 dev_dbg_f(zd_chip_dev(chip
),
219 "error zd_usb_iowrite16v. Error number %d\n",
228 /* Writes a variable number of 32 bit registers. The functions will split
229 * that in several USB requests. A split can be forced by inserting an IO
230 * request with an zero address field.
232 int zd_iowrite32a_locked(struct zd_chip
*chip
,
233 const struct zd_ioreq32
*ioreqs
, unsigned int count
)
236 unsigned int i
, j
, t
, max
;
238 for (i
= 0; i
< count
; i
+= j
+ t
) {
241 if (max
> USB_MAX_IOWRITE32_COUNT
)
242 max
= USB_MAX_IOWRITE32_COUNT
;
243 for (j
= 0; j
< max
; j
++) {
244 if (!ioreqs
[i
+j
].addr
) {
250 r
= _zd_iowrite32v_locked(chip
, &ioreqs
[i
], j
);
252 dev_dbg_f(zd_chip_dev(chip
),
253 "error _zd_iowrite32v_locked."
254 " Error number %d\n", r
);
262 int zd_ioread16(struct zd_chip
*chip
, zd_addr_t addr
, u16
*value
)
266 mutex_lock(&chip
->mutex
);
267 r
= zd_ioread16_locked(chip
, value
, addr
);
268 mutex_unlock(&chip
->mutex
);
272 int zd_ioread32(struct zd_chip
*chip
, zd_addr_t addr
, u32
*value
)
276 mutex_lock(&chip
->mutex
);
277 r
= zd_ioread32_locked(chip
, value
, addr
);
278 mutex_unlock(&chip
->mutex
);
282 int zd_iowrite16(struct zd_chip
*chip
, zd_addr_t addr
, u16 value
)
286 mutex_lock(&chip
->mutex
);
287 r
= zd_iowrite16_locked(chip
, value
, addr
);
288 mutex_unlock(&chip
->mutex
);
292 int zd_iowrite32(struct zd_chip
*chip
, zd_addr_t addr
, u32 value
)
296 mutex_lock(&chip
->mutex
);
297 r
= zd_iowrite32_locked(chip
, value
, addr
);
298 mutex_unlock(&chip
->mutex
);
302 int zd_ioread32v(struct zd_chip
*chip
, const zd_addr_t
*addresses
,
303 u32
*values
, unsigned int count
)
307 mutex_lock(&chip
->mutex
);
308 r
= zd_ioread32v_locked(chip
, values
, addresses
, count
);
309 mutex_unlock(&chip
->mutex
);
313 int zd_iowrite32a(struct zd_chip
*chip
, const struct zd_ioreq32
*ioreqs
,
318 mutex_lock(&chip
->mutex
);
319 r
= zd_iowrite32a_locked(chip
, ioreqs
, count
);
320 mutex_unlock(&chip
->mutex
);
324 static int read_pod(struct zd_chip
*chip
, u8
*rf_type
)
329 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
330 r
= zd_ioread32_locked(chip
, &value
, E2P_POD
);
333 dev_dbg_f(zd_chip_dev(chip
), "E2P_POD %#010x\n", value
);
335 /* FIXME: AL2230 handling (Bit 7 in POD) */
336 *rf_type
= value
& 0x0f;
337 chip
->pa_type
= (value
>> 16) & 0x0f;
338 chip
->patch_cck_gain
= (value
>> 8) & 0x1;
339 chip
->patch_cr157
= (value
>> 13) & 0x1;
340 chip
->patch_6m_band_edge
= (value
>> 21) & 0x1;
341 chip
->new_phy_layout
= (value
>> 31) & 0x1;
342 chip
->al2230s_bit
= (value
>> 7) & 0x1;
343 chip
->link_led
= ((value
>> 4) & 1) ? LED1
: LED2
;
344 chip
->supports_tx_led
= 1;
345 if (value
& (1 << 24)) { /* LED scenario */
346 if (value
& (1 << 29))
347 chip
->supports_tx_led
= 0;
350 dev_dbg_f(zd_chip_dev(chip
),
351 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
352 "patch 6M %d new PHY %d link LED%d tx led %d\n",
353 zd_rf_name(*rf_type
), *rf_type
,
354 chip
->pa_type
, chip
->patch_cck_gain
,
355 chip
->patch_cr157
, chip
->patch_6m_band_edge
,
356 chip
->new_phy_layout
,
357 chip
->link_led
== LED1
? 1 : 2,
358 chip
->supports_tx_led
);
363 chip
->patch_cck_gain
= 0;
364 chip
->patch_cr157
= 0;
365 chip
->patch_6m_band_edge
= 0;
366 chip
->new_phy_layout
= 0;
370 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
371 * CR_MAC_ADDR_P2 must be overwritten
373 int zd_write_mac_addr(struct zd_chip
*chip
, const u8
*mac_addr
)
376 struct zd_ioreq32 reqs
[2] = {
377 [0] = { .addr
= CR_MAC_ADDR_P1
},
378 [1] = { .addr
= CR_MAC_ADDR_P2
},
381 reqs
[0].value
= (mac_addr
[3] << 24)
382 | (mac_addr
[2] << 16)
385 reqs
[1].value
= (mac_addr
[5] << 8)
388 dev_dbg_f(zd_chip_dev(chip
),
389 "mac addr " MAC_FMT
"\n", MAC_ARG(mac_addr
));
391 mutex_lock(&chip
->mutex
);
392 r
= zd_iowrite32a_locked(chip
, reqs
, ARRAY_SIZE(reqs
));
393 mutex_unlock(&chip
->mutex
);
397 int zd_read_regdomain(struct zd_chip
*chip
, u8
*regdomain
)
402 mutex_lock(&chip
->mutex
);
403 r
= zd_ioread32_locked(chip
, &value
, E2P_SUBID
);
404 mutex_unlock(&chip
->mutex
);
408 *regdomain
= value
>> 16;
409 dev_dbg_f(zd_chip_dev(chip
), "regdomain: %#04x\n", *regdomain
);
414 static int read_values(struct zd_chip
*chip
, u8
*values
, size_t count
,
415 zd_addr_t e2p_addr
, u32 guard
)
421 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
423 r
= zd_ioread32_locked(chip
, &v
,
424 (zd_addr_t
)((u16
)e2p_addr
+i
/2));
430 values
[i
++] = v
>> 8;
431 values
[i
++] = v
>> 16;
432 values
[i
++] = v
>> 24;
435 for (;i
< count
; i
++)
436 values
[i
] = v
>> (8*(i
%3));
441 static int read_pwr_cal_values(struct zd_chip
*chip
)
443 return read_values(chip
, chip
->pwr_cal_values
,
444 E2P_CHANNEL_COUNT
, E2P_PWR_CAL_VALUE1
,
448 static int read_pwr_int_values(struct zd_chip
*chip
)
450 return read_values(chip
, chip
->pwr_int_values
,
451 E2P_CHANNEL_COUNT
, E2P_PWR_INT_VALUE1
,
455 static int read_ofdm_cal_values(struct zd_chip
*chip
)
459 static const zd_addr_t addresses
[] = {
465 for (i
= 0; i
< 3; i
++) {
466 r
= read_values(chip
, chip
->ofdm_cal_values
[i
],
467 E2P_CHANNEL_COUNT
, addresses
[i
], 0);
474 static int read_cal_int_tables(struct zd_chip
*chip
)
478 r
= read_pwr_cal_values(chip
);
481 r
= read_pwr_int_values(chip
);
484 r
= read_ofdm_cal_values(chip
);
490 /* phy means physical registers */
491 int zd_chip_lock_phy_regs(struct zd_chip
*chip
)
496 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
497 r
= zd_ioread32_locked(chip
, &tmp
, CR_REG1
);
499 dev_err(zd_chip_dev(chip
), "error ioread32(CR_REG1): %d\n", r
);
503 tmp
&= ~UNLOCK_PHY_REGS
;
505 r
= zd_iowrite32_locked(chip
, tmp
, CR_REG1
);
507 dev_err(zd_chip_dev(chip
), "error iowrite32(CR_REG1): %d\n", r
);
511 int zd_chip_unlock_phy_regs(struct zd_chip
*chip
)
516 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
517 r
= zd_ioread32_locked(chip
, &tmp
, CR_REG1
);
519 dev_err(zd_chip_dev(chip
),
520 "error ioread32(CR_REG1): %d\n", r
);
524 tmp
|= UNLOCK_PHY_REGS
;
526 r
= zd_iowrite32_locked(chip
, tmp
, CR_REG1
);
528 dev_err(zd_chip_dev(chip
), "error iowrite32(CR_REG1): %d\n", r
);
532 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
533 static int patch_cr157(struct zd_chip
*chip
)
538 if (!chip
->patch_cr157
)
541 r
= zd_ioread16_locked(chip
, &value
, E2P_PHY_REG
);
545 dev_dbg_f(zd_chip_dev(chip
), "patching value %x\n", value
>> 8);
546 return zd_iowrite32_locked(chip
, value
>> 8, CR157
);
550 * 6M band edge can be optionally overwritten for certain RF's
551 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
552 * bit (for AL2230, AL2230S)
554 static int patch_6m_band_edge(struct zd_chip
*chip
, u8 channel
)
556 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
557 if (!chip
->patch_6m_band_edge
)
560 return zd_rf_patch_6m_band_edge(&chip
->rf
, channel
);
563 /* Generic implementation of 6M band edge patching, used by most RFs via
564 * zd_rf_generic_patch_6m() */
565 int zd_chip_generic_patch_6m_band(struct zd_chip
*chip
, int channel
)
567 struct zd_ioreq16 ioreqs
[] = {
568 { CR128
, 0x14 }, { CR129
, 0x12 }, { CR130
, 0x10 },
572 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
573 if (channel
== 1 || channel
== 11)
574 ioreqs
[0].value
= 0x12;
576 dev_dbg_f(zd_chip_dev(chip
), "patching for channel %d\n", channel
);
577 return zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
580 static int zd1211_hw_reset_phy(struct zd_chip
*chip
)
582 static const struct zd_ioreq16 ioreqs
[] = {
583 { CR0
, 0x0a }, { CR1
, 0x06 }, { CR2
, 0x26 },
584 { CR3
, 0x38 }, { CR4
, 0x80 }, { CR9
, 0xa0 },
585 { CR10
, 0x81 }, { CR11
, 0x00 }, { CR12
, 0x7f },
586 { CR13
, 0x8c }, { CR14
, 0x80 }, { CR15
, 0x3d },
587 { CR16
, 0x20 }, { CR17
, 0x1e }, { CR18
, 0x0a },
588 { CR19
, 0x48 }, { CR20
, 0x0c }, { CR21
, 0x0c },
589 { CR22
, 0x23 }, { CR23
, 0x90 }, { CR24
, 0x14 },
590 { CR25
, 0x40 }, { CR26
, 0x10 }, { CR27
, 0x19 },
591 { CR28
, 0x7f }, { CR29
, 0x80 }, { CR30
, 0x4b },
592 { CR31
, 0x60 }, { CR32
, 0x43 }, { CR33
, 0x08 },
593 { CR34
, 0x06 }, { CR35
, 0x0a }, { CR36
, 0x00 },
594 { CR37
, 0x00 }, { CR38
, 0x38 }, { CR39
, 0x0c },
595 { CR40
, 0x84 }, { CR41
, 0x2a }, { CR42
, 0x80 },
596 { CR43
, 0x10 }, { CR44
, 0x12 }, { CR46
, 0xff },
597 { CR47
, 0x1E }, { CR48
, 0x26 }, { CR49
, 0x5b },
598 { CR64
, 0xd0 }, { CR65
, 0x04 }, { CR66
, 0x58 },
599 { CR67
, 0xc9 }, { CR68
, 0x88 }, { CR69
, 0x41 },
600 { CR70
, 0x23 }, { CR71
, 0x10 }, { CR72
, 0xff },
601 { CR73
, 0x32 }, { CR74
, 0x30 }, { CR75
, 0x65 },
602 { CR76
, 0x41 }, { CR77
, 0x1b }, { CR78
, 0x30 },
603 { CR79
, 0x68 }, { CR80
, 0x64 }, { CR81
, 0x64 },
604 { CR82
, 0x00 }, { CR83
, 0x00 }, { CR84
, 0x00 },
605 { CR85
, 0x02 }, { CR86
, 0x00 }, { CR87
, 0x00 },
606 { CR88
, 0xff }, { CR89
, 0xfc }, { CR90
, 0x00 },
607 { CR91
, 0x00 }, { CR92
, 0x00 }, { CR93
, 0x08 },
608 { CR94
, 0x00 }, { CR95
, 0x00 }, { CR96
, 0xff },
609 { CR97
, 0xe7 }, { CR98
, 0x00 }, { CR99
, 0x00 },
610 { CR100
, 0x00 }, { CR101
, 0xae }, { CR102
, 0x02 },
611 { CR103
, 0x00 }, { CR104
, 0x03 }, { CR105
, 0x65 },
612 { CR106
, 0x04 }, { CR107
, 0x00 }, { CR108
, 0x0a },
613 { CR109
, 0xaa }, { CR110
, 0xaa }, { CR111
, 0x25 },
614 { CR112
, 0x25 }, { CR113
, 0x00 }, { CR119
, 0x1e },
615 { CR125
, 0x90 }, { CR126
, 0x00 }, { CR127
, 0x00 },
617 { CR5
, 0x00 }, { CR6
, 0x00 }, { CR7
, 0x00 },
618 { CR8
, 0x00 }, { CR9
, 0x20 }, { CR12
, 0xf0 },
619 { CR20
, 0x0e }, { CR21
, 0x0e }, { CR27
, 0x10 },
620 { CR44
, 0x33 }, { CR47
, 0x1E }, { CR83
, 0x24 },
621 { CR84
, 0x04 }, { CR85
, 0x00 }, { CR86
, 0x0C },
622 { CR87
, 0x12 }, { CR88
, 0x0C }, { CR89
, 0x00 },
623 { CR90
, 0x10 }, { CR91
, 0x08 }, { CR93
, 0x00 },
624 { CR94
, 0x01 }, { CR95
, 0x00 }, { CR96
, 0x50 },
625 { CR97
, 0x37 }, { CR98
, 0x35 }, { CR101
, 0x13 },
626 { CR102
, 0x27 }, { CR103
, 0x27 }, { CR104
, 0x18 },
627 { CR105
, 0x12 }, { CR109
, 0x27 }, { CR110
, 0x27 },
628 { CR111
, 0x27 }, { CR112
, 0x27 }, { CR113
, 0x27 },
629 { CR114
, 0x27 }, { CR115
, 0x26 }, { CR116
, 0x24 },
630 { CR117
, 0xfc }, { CR118
, 0xfa }, { CR120
, 0x4f },
631 { CR125
, 0xaa }, { CR127
, 0x03 }, { CR128
, 0x14 },
632 { CR129
, 0x12 }, { CR130
, 0x10 }, { CR131
, 0x0C },
633 { CR136
, 0xdf }, { CR137
, 0x40 }, { CR138
, 0xa0 },
634 { CR139
, 0xb0 }, { CR140
, 0x99 }, { CR141
, 0x82 },
635 { CR142
, 0x54 }, { CR143
, 0x1c }, { CR144
, 0x6c },
636 { CR147
, 0x07 }, { CR148
, 0x4c }, { CR149
, 0x50 },
637 { CR150
, 0x0e }, { CR151
, 0x18 }, { CR160
, 0xfe },
638 { CR161
, 0xee }, { CR162
, 0xaa }, { CR163
, 0xfa },
639 { CR164
, 0xfa }, { CR165
, 0xea }, { CR166
, 0xbe },
640 { CR167
, 0xbe }, { CR168
, 0x6a }, { CR169
, 0xba },
641 { CR170
, 0xba }, { CR171
, 0xba },
642 /* Note: CR204 must lead the CR203 */
650 dev_dbg_f(zd_chip_dev(chip
), "\n");
652 r
= zd_chip_lock_phy_regs(chip
);
656 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
660 r
= patch_cr157(chip
);
662 t
= zd_chip_unlock_phy_regs(chip
);
669 static int zd1211b_hw_reset_phy(struct zd_chip
*chip
)
671 static const struct zd_ioreq16 ioreqs
[] = {
672 { CR0
, 0x14 }, { CR1
, 0x06 }, { CR2
, 0x26 },
673 { CR3
, 0x38 }, { CR4
, 0x80 }, { CR9
, 0xe0 },
675 /* power control { { CR11, 1 << 6 }, */
677 { CR12
, 0xf0 }, { CR13
, 0x8c }, { CR14
, 0x80 },
678 { CR15
, 0x3d }, { CR16
, 0x20 }, { CR17
, 0x1e },
679 { CR18
, 0x0a }, { CR19
, 0x48 },
680 { CR20
, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
681 { CR21
, 0x0e }, { CR22
, 0x23 }, { CR23
, 0x90 },
682 { CR24
, 0x14 }, { CR25
, 0x40 }, { CR26
, 0x10 },
683 { CR27
, 0x10 }, { CR28
, 0x7f }, { CR29
, 0x80 },
684 { CR30
, 0x4b }, /* ASIC/FWT, no jointly decoder */
685 { CR31
, 0x60 }, { CR32
, 0x43 }, { CR33
, 0x08 },
686 { CR34
, 0x06 }, { CR35
, 0x0a }, { CR36
, 0x00 },
687 { CR37
, 0x00 }, { CR38
, 0x38 }, { CR39
, 0x0c },
688 { CR40
, 0x84 }, { CR41
, 0x2a }, { CR42
, 0x80 },
689 { CR43
, 0x10 }, { CR44
, 0x33 }, { CR46
, 0xff },
690 { CR47
, 0x1E }, { CR48
, 0x26 }, { CR49
, 0x5b },
691 { CR64
, 0xd0 }, { CR65
, 0x04 }, { CR66
, 0x58 },
692 { CR67
, 0xc9 }, { CR68
, 0x88 }, { CR69
, 0x41 },
693 { CR70
, 0x23 }, { CR71
, 0x10 }, { CR72
, 0xff },
694 { CR73
, 0x32 }, { CR74
, 0x30 }, { CR75
, 0x65 },
695 { CR76
, 0x41 }, { CR77
, 0x1b }, { CR78
, 0x30 },
696 { CR79
, 0xf0 }, { CR80
, 0x64 }, { CR81
, 0x64 },
697 { CR82
, 0x00 }, { CR83
, 0x24 }, { CR84
, 0x04 },
698 { CR85
, 0x00 }, { CR86
, 0x0c }, { CR87
, 0x12 },
699 { CR88
, 0x0c }, { CR89
, 0x00 }, { CR90
, 0x58 },
700 { CR91
, 0x04 }, { CR92
, 0x00 }, { CR93
, 0x00 },
702 { CR95
, 0x20 }, /* ZD1211B */
703 { CR96
, 0x50 }, { CR97
, 0x37 }, { CR98
, 0x35 },
704 { CR99
, 0x00 }, { CR100
, 0x01 }, { CR101
, 0x13 },
705 { CR102
, 0x27 }, { CR103
, 0x27 }, { CR104
, 0x18 },
706 { CR105
, 0x12 }, { CR106
, 0x04 }, { CR107
, 0x00 },
707 { CR108
, 0x0a }, { CR109
, 0x27 }, { CR110
, 0x27 },
708 { CR111
, 0x27 }, { CR112
, 0x27 }, { CR113
, 0x27 },
709 { CR114
, 0x27 }, { CR115
, 0x26 }, { CR116
, 0x24 },
710 { CR117
, 0xfc }, { CR118
, 0xfa }, { CR119
, 0x1e },
711 { CR125
, 0x90 }, { CR126
, 0x00 }, { CR127
, 0x00 },
712 { CR128
, 0x14 }, { CR129
, 0x12 }, { CR130
, 0x10 },
713 { CR131
, 0x0c }, { CR136
, 0xdf }, { CR137
, 0xa0 },
714 { CR138
, 0xa8 }, { CR139
, 0xb4 }, { CR140
, 0x98 },
715 { CR141
, 0x82 }, { CR142
, 0x53 }, { CR143
, 0x1c },
716 { CR144
, 0x6c }, { CR147
, 0x07 }, { CR148
, 0x40 },
717 { CR149
, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
718 { CR150
, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
719 { CR151
, 0x18 }, { CR159
, 0x70 }, { CR160
, 0xfe },
720 { CR161
, 0xee }, { CR162
, 0xaa }, { CR163
, 0xfa },
721 { CR164
, 0xfa }, { CR165
, 0xea }, { CR166
, 0xbe },
722 { CR167
, 0xbe }, { CR168
, 0x6a }, { CR169
, 0xba },
723 { CR170
, 0xba }, { CR171
, 0xba },
724 /* Note: CR204 must lead the CR203 */
732 dev_dbg_f(zd_chip_dev(chip
), "\n");
734 r
= zd_chip_lock_phy_regs(chip
);
738 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
739 t
= zd_chip_unlock_phy_regs(chip
);
746 static int hw_reset_phy(struct zd_chip
*chip
)
748 return zd_chip_is_zd1211b(chip
) ? zd1211b_hw_reset_phy(chip
) :
749 zd1211_hw_reset_phy(chip
);
752 static int zd1211_hw_init_hmac(struct zd_chip
*chip
)
754 static const struct zd_ioreq32 ioreqs
[] = {
755 { CR_ZD1211_RETRY_MAX
, 0x2 },
756 { CR_RX_THRESHOLD
, 0x000c0640 },
759 dev_dbg_f(zd_chip_dev(chip
), "\n");
760 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
761 return zd_iowrite32a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
764 static int zd1211b_hw_init_hmac(struct zd_chip
*chip
)
766 static const struct zd_ioreq32 ioreqs
[] = {
767 { CR_ZD1211B_RETRY_MAX
, 0x02020202 },
768 { CR_ZD1211B_TX_PWR_CTL4
, 0x007f003f },
769 { CR_ZD1211B_TX_PWR_CTL3
, 0x007f003f },
770 { CR_ZD1211B_TX_PWR_CTL2
, 0x003f001f },
771 { CR_ZD1211B_TX_PWR_CTL1
, 0x001f000f },
772 { CR_ZD1211B_AIFS_CTL1
, 0x00280028 },
773 { CR_ZD1211B_AIFS_CTL2
, 0x008C003C },
774 { CR_ZD1211B_TXOP
, 0x01800824 },
775 { CR_RX_THRESHOLD
, 0x000c0eff, },
778 dev_dbg_f(zd_chip_dev(chip
), "\n");
779 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
780 return zd_iowrite32a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
783 static int hw_init_hmac(struct zd_chip
*chip
)
786 static const struct zd_ioreq32 ioreqs
[] = {
787 { CR_ACK_TIMEOUT_EXT
, 0x20 },
788 { CR_ADDA_MBIAS_WARMTIME
, 0x30000808 },
789 { CR_SNIFFER_ON
, 0 },
790 { CR_RX_FILTER
, STA_RX_FILTER
},
791 { CR_GROUP_HASH_P1
, 0x00 },
792 { CR_GROUP_HASH_P2
, 0x80000000 },
794 { CR_ADDA_PWR_DWN
, 0x7f },
795 { CR_BCN_PLCP_CFG
, 0x00f00401 },
796 { CR_PHY_DELAY
, 0x00 },
797 { CR_ACK_TIMEOUT_EXT
, 0x80 },
798 { CR_ADDA_PWR_DWN
, 0x00 },
799 { CR_ACK_TIME_80211
, 0x100 },
800 { CR_RX_PE_DELAY
, 0x70 },
801 { CR_PS_CTRL
, 0x10000000 },
802 { CR_RTS_CTS_RATE
, 0x02030203 },
803 { CR_AFTER_PNP
, 0x1 },
804 { CR_WEP_PROTECT
, 0x114 },
805 { CR_IFS_VALUE
, IFS_VALUE_DEFAULT
},
808 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
809 r
= zd_iowrite32a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
813 return zd_chip_is_zd1211b(chip
) ?
814 zd1211b_hw_init_hmac(chip
) : zd1211_hw_init_hmac(chip
);
823 static int get_aw_pt_bi(struct zd_chip
*chip
, struct aw_pt_bi
*s
)
826 static const zd_addr_t aw_pt_bi_addr
[] =
827 { CR_ATIM_WND_PERIOD
, CR_PRE_TBTT
, CR_BCN_INTERVAL
};
830 r
= zd_ioread32v_locked(chip
, values
, (const zd_addr_t
*)aw_pt_bi_addr
,
831 ARRAY_SIZE(aw_pt_bi_addr
));
833 memset(s
, 0, sizeof(*s
));
837 s
->atim_wnd_period
= values
[0];
838 s
->pre_tbtt
= values
[1];
839 s
->beacon_interval
= values
[2];
843 static int set_aw_pt_bi(struct zd_chip
*chip
, struct aw_pt_bi
*s
)
845 struct zd_ioreq32 reqs
[3];
847 if (s
->beacon_interval
<= 5)
848 s
->beacon_interval
= 5;
849 if (s
->pre_tbtt
< 4 || s
->pre_tbtt
>= s
->beacon_interval
)
850 s
->pre_tbtt
= s
->beacon_interval
- 1;
851 if (s
->atim_wnd_period
>= s
->pre_tbtt
)
852 s
->atim_wnd_period
= s
->pre_tbtt
- 1;
854 reqs
[0].addr
= CR_ATIM_WND_PERIOD
;
855 reqs
[0].value
= s
->atim_wnd_period
;
856 reqs
[1].addr
= CR_PRE_TBTT
;
857 reqs
[1].value
= s
->pre_tbtt
;
858 reqs
[2].addr
= CR_BCN_INTERVAL
;
859 reqs
[2].value
= s
->beacon_interval
;
861 return zd_iowrite32a_locked(chip
, reqs
, ARRAY_SIZE(reqs
));
865 static int set_beacon_interval(struct zd_chip
*chip
, u32 interval
)
870 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
871 r
= get_aw_pt_bi(chip
, &s
);
874 s
.beacon_interval
= interval
;
875 return set_aw_pt_bi(chip
, &s
);
878 int zd_set_beacon_interval(struct zd_chip
*chip
, u32 interval
)
882 mutex_lock(&chip
->mutex
);
883 r
= set_beacon_interval(chip
, interval
);
884 mutex_unlock(&chip
->mutex
);
888 static int hw_init(struct zd_chip
*chip
)
892 dev_dbg_f(zd_chip_dev(chip
), "\n");
893 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
894 r
= hw_reset_phy(chip
);
898 r
= hw_init_hmac(chip
);
902 return set_beacon_interval(chip
, 100);
905 static zd_addr_t
fw_reg_addr(struct zd_chip
*chip
, u16 offset
)
907 return (zd_addr_t
)((u16
)chip
->fw_regs_base
+ offset
);
911 static int dump_cr(struct zd_chip
*chip
, const zd_addr_t addr
,
912 const char *addr_string
)
917 r
= zd_ioread32_locked(chip
, &value
, addr
);
919 dev_dbg_f(zd_chip_dev(chip
),
920 "error reading %s. Error number %d\n", addr_string
, r
);
924 dev_dbg_f(zd_chip_dev(chip
), "%s %#010x\n",
925 addr_string
, (unsigned int)value
);
929 static int test_init(struct zd_chip
*chip
)
933 r
= dump_cr(chip
, CR_AFTER_PNP
, "CR_AFTER_PNP");
936 r
= dump_cr(chip
, CR_GPI_EN
, "CR_GPI_EN");
939 return dump_cr(chip
, CR_INTERRUPT
, "CR_INTERRUPT");
942 static void dump_fw_registers(struct zd_chip
*chip
)
944 const zd_addr_t addr
[4] = {
945 fw_reg_addr(chip
, FW_REG_FIRMWARE_VER
),
946 fw_reg_addr(chip
, FW_REG_USB_SPEED
),
947 fw_reg_addr(chip
, FW_REG_FIX_TX_RATE
),
948 fw_reg_addr(chip
, FW_REG_LED_LINK_STATUS
),
954 r
= zd_ioread16v_locked(chip
, values
, (const zd_addr_t
*)addr
,
957 dev_dbg_f(zd_chip_dev(chip
), "error %d zd_ioread16v_locked\n",
962 dev_dbg_f(zd_chip_dev(chip
), "FW_FIRMWARE_VER %#06hx\n", values
[0]);
963 dev_dbg_f(zd_chip_dev(chip
), "FW_USB_SPEED %#06hx\n", values
[1]);
964 dev_dbg_f(zd_chip_dev(chip
), "FW_FIX_TX_RATE %#06hx\n", values
[2]);
965 dev_dbg_f(zd_chip_dev(chip
), "FW_LINK_STATUS %#06hx\n", values
[3]);
969 static int print_fw_version(struct zd_chip
*chip
)
974 r
= zd_ioread16_locked(chip
, &version
,
975 fw_reg_addr(chip
, FW_REG_FIRMWARE_VER
));
979 dev_info(zd_chip_dev(chip
),"firmware version %04hx\n", version
);
983 static int set_mandatory_rates(struct zd_chip
*chip
, enum ieee80211_std std
)
986 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
987 /* This sets the mandatory rates, which only depend from the standard
988 * that the device is supporting. Until further notice we should try
989 * to support 802.11g also for full speed USB.
993 rates
= CR_RATE_1M
|CR_RATE_2M
|CR_RATE_5_5M
|CR_RATE_11M
;
996 rates
= CR_RATE_1M
|CR_RATE_2M
|CR_RATE_5_5M
|CR_RATE_11M
|
997 CR_RATE_6M
|CR_RATE_12M
|CR_RATE_24M
;
1002 return zd_iowrite32_locked(chip
, rates
, CR_MANDATORY_RATE_TBL
);
1005 int zd_chip_set_rts_cts_rate_locked(struct zd_chip
*chip
,
1006 u8 rts_rate
, int preamble
)
1008 int rts_mod
= ZD_RX_CCK
;
1011 /* Modulation bit */
1012 if (ZD_CS_TYPE(rts_rate
) == ZD_CS_OFDM
)
1013 rts_mod
= ZD_RX_OFDM
;
1015 dev_dbg_f(zd_chip_dev(chip
), "rts_rate=%x preamble=%x\n",
1016 rts_rate
, preamble
);
1018 value
|= rts_rate
<< RTSCTS_SH_RTS_RATE
;
1019 value
|= rts_mod
<< RTSCTS_SH_RTS_MOD_TYPE
;
1020 value
|= preamble
<< RTSCTS_SH_RTS_PMB_TYPE
;
1021 value
|= preamble
<< RTSCTS_SH_CTS_PMB_TYPE
;
1023 /* We always send 11M self-CTS messages, like the vendor driver. */
1024 value
|= ZD_CCK_RATE_11M
<< RTSCTS_SH_CTS_RATE
;
1025 value
|= ZD_RX_CCK
<< RTSCTS_SH_CTS_MOD_TYPE
;
1027 return zd_iowrite32_locked(chip
, value
, CR_RTS_CTS_RATE
);
1030 int zd_chip_enable_hwint(struct zd_chip
*chip
)
1034 mutex_lock(&chip
->mutex
);
1035 r
= zd_iowrite32_locked(chip
, HWINT_ENABLED
, CR_INTERRUPT
);
1036 mutex_unlock(&chip
->mutex
);
1040 static int disable_hwint(struct zd_chip
*chip
)
1042 return zd_iowrite32_locked(chip
, HWINT_DISABLED
, CR_INTERRUPT
);
1045 int zd_chip_disable_hwint(struct zd_chip
*chip
)
1049 mutex_lock(&chip
->mutex
);
1050 r
= disable_hwint(chip
);
1051 mutex_unlock(&chip
->mutex
);
1055 static int read_fw_regs_offset(struct zd_chip
*chip
)
1059 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
1060 r
= zd_ioread16_locked(chip
, (u16
*)&chip
->fw_regs_base
,
1064 dev_dbg_f(zd_chip_dev(chip
), "fw_regs_base: %#06hx\n",
1065 (u16
)chip
->fw_regs_base
);
1070 /* Read mac address using pre-firmware interface */
1071 int zd_chip_read_mac_addr_fw(struct zd_chip
*chip
, u8
*addr
)
1073 dev_dbg_f(zd_chip_dev(chip
), "\n");
1074 return zd_usb_read_fw(&chip
->usb
, E2P_MAC_ADDR_P1
, addr
,
1078 int zd_chip_init_hw(struct zd_chip
*chip
)
1083 dev_dbg_f(zd_chip_dev(chip
), "\n");
1085 mutex_lock(&chip
->mutex
);
1088 r
= test_init(chip
);
1092 r
= zd_iowrite32_locked(chip
, 1, CR_AFTER_PNP
);
1096 r
= read_fw_regs_offset(chip
);
1100 /* GPI is always disabled, also in the other driver.
1102 r
= zd_iowrite32_locked(chip
, 0, CR_GPI_EN
);
1105 r
= zd_iowrite32_locked(chip
, CWIN_SIZE
, CR_CWMIN_CWMAX
);
1108 /* Currently we support IEEE 802.11g for full and high speed USB.
1109 * It might be discussed, whether we should suppport pure b mode for
1112 r
= set_mandatory_rates(chip
, IEEE80211G
);
1115 /* Disabling interrupts is certainly a smart thing here.
1117 r
= disable_hwint(chip
);
1120 r
= read_pod(chip
, &rf_type
);
1126 r
= zd_rf_init_hw(&chip
->rf
, rf_type
);
1130 r
= print_fw_version(chip
);
1135 dump_fw_registers(chip
);
1136 r
= test_init(chip
);
1141 r
= read_cal_int_tables(chip
);
1147 mutex_unlock(&chip
->mutex
);
1151 static int update_pwr_int(struct zd_chip
*chip
, u8 channel
)
1153 u8 value
= chip
->pwr_int_values
[channel
- 1];
1154 return zd_iowrite16_locked(chip
, value
, CR31
);
1157 static int update_pwr_cal(struct zd_chip
*chip
, u8 channel
)
1159 u8 value
= chip
->pwr_cal_values
[channel
-1];
1160 return zd_iowrite16_locked(chip
, value
, CR68
);
1163 static int update_ofdm_cal(struct zd_chip
*chip
, u8 channel
)
1165 struct zd_ioreq16 ioreqs
[3];
1167 ioreqs
[0].addr
= CR67
;
1168 ioreqs
[0].value
= chip
->ofdm_cal_values
[OFDM_36M_INDEX
][channel
-1];
1169 ioreqs
[1].addr
= CR66
;
1170 ioreqs
[1].value
= chip
->ofdm_cal_values
[OFDM_48M_INDEX
][channel
-1];
1171 ioreqs
[2].addr
= CR65
;
1172 ioreqs
[2].value
= chip
->ofdm_cal_values
[OFDM_54M_INDEX
][channel
-1];
1174 return zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1177 static int update_channel_integration_and_calibration(struct zd_chip
*chip
,
1182 if (!zd_rf_should_update_pwr_int(&chip
->rf
))
1185 r
= update_pwr_int(chip
, channel
);
1188 if (zd_chip_is_zd1211b(chip
)) {
1189 static const struct zd_ioreq16 ioreqs
[] = {
1195 r
= update_ofdm_cal(chip
, channel
);
1198 r
= update_pwr_cal(chip
, channel
);
1201 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1209 /* The CCK baseband gain can be optionally patched by the EEPROM */
1210 static int patch_cck_gain(struct zd_chip
*chip
)
1215 if (!chip
->patch_cck_gain
|| !zd_rf_should_patch_cck_gain(&chip
->rf
))
1218 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
1219 r
= zd_ioread32_locked(chip
, &value
, E2P_PHY_REG
);
1222 dev_dbg_f(zd_chip_dev(chip
), "patching value %x\n", value
& 0xff);
1223 return zd_iowrite16_locked(chip
, value
& 0xff, CR47
);
1226 int zd_chip_set_channel(struct zd_chip
*chip
, u8 channel
)
1230 mutex_lock(&chip
->mutex
);
1231 r
= zd_chip_lock_phy_regs(chip
);
1234 r
= zd_rf_set_channel(&chip
->rf
, channel
);
1237 r
= update_channel_integration_and_calibration(chip
, channel
);
1240 r
= patch_cck_gain(chip
);
1243 r
= patch_6m_band_edge(chip
, channel
);
1246 r
= zd_iowrite32_locked(chip
, 0, CR_CONFIG_PHILIPS
);
1248 t
= zd_chip_unlock_phy_regs(chip
);
1252 mutex_unlock(&chip
->mutex
);
1256 u8
zd_chip_get_channel(struct zd_chip
*chip
)
1260 mutex_lock(&chip
->mutex
);
1261 channel
= chip
->rf
.channel
;
1262 mutex_unlock(&chip
->mutex
);
1266 int zd_chip_control_leds(struct zd_chip
*chip
, enum led_status status
)
1268 const zd_addr_t a
[] = {
1269 fw_reg_addr(chip
, FW_REG_LED_LINK_STATUS
),
1274 u16 v
[ARRAY_SIZE(a
)];
1275 struct zd_ioreq16 ioreqs
[ARRAY_SIZE(a
)] = {
1276 [0] = { fw_reg_addr(chip
, FW_REG_LED_LINK_STATUS
) },
1281 mutex_lock(&chip
->mutex
);
1282 r
= zd_ioread16v_locked(chip
, v
, (const zd_addr_t
*)a
, ARRAY_SIZE(a
));
1286 other_led
= chip
->link_led
== LED1
? LED2
: LED1
;
1290 ioreqs
[0].value
= FW_LINK_OFF
;
1291 ioreqs
[1].value
= v
[1] & ~(LED1
|LED2
);
1294 ioreqs
[0].value
= FW_LINK_OFF
;
1295 ioreqs
[1].value
= v
[1] & ~other_led
;
1296 if (get_seconds() % 3 == 0) {
1297 ioreqs
[1].value
&= ~chip
->link_led
;
1299 ioreqs
[1].value
|= chip
->link_led
;
1302 case LED_ASSOCIATED
:
1303 ioreqs
[0].value
= FW_LINK_TX
;
1304 ioreqs
[1].value
= v
[1] & ~other_led
;
1305 ioreqs
[1].value
|= chip
->link_led
;
1312 if (v
[0] != ioreqs
[0].value
|| v
[1] != ioreqs
[1].value
) {
1313 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1319 mutex_unlock(&chip
->mutex
);
1323 int zd_chip_set_basic_rates_locked(struct zd_chip
*chip
, u16 cr_rates
)
1325 ZD_ASSERT((cr_rates
& ~(CR_RATES_80211B
| CR_RATES_80211G
)) == 0);
1326 dev_dbg_f(zd_chip_dev(chip
), "%x\n", cr_rates
);
1328 return zd_iowrite32_locked(chip
, cr_rates
, CR_BASIC_RATE_TBL
);
1331 static int ofdm_qual_db(u8 status_quality
, u8 rate
, unsigned int size
)
1333 static const u16 constants
[] = {
1334 715, 655, 585, 540, 470, 410, 360, 315,
1335 270, 235, 205, 175, 150, 125, 105, 85,
1342 /* It seems that their quality parameter is somehow per signal
1343 * and is now transferred per bit.
1346 case ZD_OFDM_RATE_6M
:
1347 case ZD_OFDM_RATE_12M
:
1348 case ZD_OFDM_RATE_24M
:
1351 case ZD_OFDM_RATE_9M
:
1352 case ZD_OFDM_RATE_18M
:
1353 case ZD_OFDM_RATE_36M
:
1354 case ZD_OFDM_RATE_54M
:
1358 case ZD_OFDM_RATE_48M
:
1366 x
= (10000 * status_quality
)/size
;
1367 for (i
= 0; i
< ARRAY_SIZE(constants
); i
++) {
1368 if (x
> constants
[i
])
1373 case ZD_OFDM_RATE_6M
:
1374 case ZD_OFDM_RATE_9M
:
1377 case ZD_OFDM_RATE_12M
:
1378 case ZD_OFDM_RATE_18M
:
1381 case ZD_OFDM_RATE_24M
:
1382 case ZD_OFDM_RATE_36M
:
1385 case ZD_OFDM_RATE_48M
:
1386 case ZD_OFDM_RATE_54M
:
1396 static int ofdm_qual_percent(u8 status_quality
, u8 rate
, unsigned int size
)
1400 r
= ofdm_qual_db(status_quality
, rate
, size
);
1406 return r
<= 100 ? r
: 100;
1409 static unsigned int log10times100(unsigned int x
)
1411 static const u8 log10
[] = {
1413 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1414 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1415 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1416 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1417 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1418 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1419 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1420 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1421 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1422 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1423 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1424 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1425 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1426 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1427 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1428 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1429 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1430 223, 223, 223, 224, 224, 224, 224,
1433 return x
< ARRAY_SIZE(log10
) ? log10
[x
] : 225;
1437 MAX_CCK_EVM_DB
= 45,
1440 static int cck_evm_db(u8 status_quality
)
1442 return (20 * log10times100(status_quality
)) / 100;
1445 static int cck_snr_db(u8 status_quality
)
1447 int r
= MAX_CCK_EVM_DB
- cck_evm_db(status_quality
);
1452 static int cck_qual_percent(u8 status_quality
)
1456 r
= cck_snr_db(status_quality
);
1458 return r
<= 100 ? r
: 100;
1461 u8
zd_rx_qual_percent(const void *rx_frame
, unsigned int size
,
1462 const struct rx_status
*status
)
1464 return (status
->frame_status
&ZD_RX_OFDM
) ?
1465 ofdm_qual_percent(status
->signal_quality_ofdm
,
1466 zd_ofdm_plcp_header_rate(rx_frame
),
1468 cck_qual_percent(status
->signal_quality_cck
);
1471 u8
zd_rx_strength_percent(u8 rssi
)
1473 int r
= (rssi
*100) / 41;
1479 u16
zd_rx_rate(const void *rx_frame
, const struct rx_status
*status
)
1481 static const u16 ofdm_rates
[] = {
1482 [ZD_OFDM_RATE_6M
] = 60,
1483 [ZD_OFDM_RATE_9M
] = 90,
1484 [ZD_OFDM_RATE_12M
] = 120,
1485 [ZD_OFDM_RATE_18M
] = 180,
1486 [ZD_OFDM_RATE_24M
] = 240,
1487 [ZD_OFDM_RATE_36M
] = 360,
1488 [ZD_OFDM_RATE_48M
] = 480,
1489 [ZD_OFDM_RATE_54M
] = 540,
1492 if (status
->frame_status
& ZD_RX_OFDM
) {
1493 u8 ofdm_rate
= zd_ofdm_plcp_header_rate(rx_frame
);
1494 rate
= ofdm_rates
[ofdm_rate
& 0xf];
1496 u8 cck_rate
= zd_cck_plcp_header_rate(rx_frame
);
1498 case ZD_CCK_SIGNAL_1M
:
1501 case ZD_CCK_SIGNAL_2M
:
1504 case ZD_CCK_SIGNAL_5M5
:
1507 case ZD_CCK_SIGNAL_11M
:
1518 int zd_chip_switch_radio_on(struct zd_chip
*chip
)
1522 mutex_lock(&chip
->mutex
);
1523 r
= zd_switch_radio_on(&chip
->rf
);
1524 mutex_unlock(&chip
->mutex
);
1528 int zd_chip_switch_radio_off(struct zd_chip
*chip
)
1532 mutex_lock(&chip
->mutex
);
1533 r
= zd_switch_radio_off(&chip
->rf
);
1534 mutex_unlock(&chip
->mutex
);
1538 int zd_chip_enable_int(struct zd_chip
*chip
)
1542 mutex_lock(&chip
->mutex
);
1543 r
= zd_usb_enable_int(&chip
->usb
);
1544 mutex_unlock(&chip
->mutex
);
1548 void zd_chip_disable_int(struct zd_chip
*chip
)
1550 mutex_lock(&chip
->mutex
);
1551 zd_usb_disable_int(&chip
->usb
);
1552 mutex_unlock(&chip
->mutex
);
1555 int zd_chip_enable_rx(struct zd_chip
*chip
)
1559 mutex_lock(&chip
->mutex
);
1560 r
= zd_usb_enable_rx(&chip
->usb
);
1561 mutex_unlock(&chip
->mutex
);
1565 void zd_chip_disable_rx(struct zd_chip
*chip
)
1567 mutex_lock(&chip
->mutex
);
1568 zd_usb_disable_rx(&chip
->usb
);
1569 mutex_unlock(&chip
->mutex
);
1572 int zd_rfwritev_locked(struct zd_chip
*chip
,
1573 const u32
* values
, unsigned int count
, u8 bits
)
1578 for (i
= 0; i
< count
; i
++) {
1579 r
= zd_rfwrite_locked(chip
, values
[i
], bits
);
1588 * We can optionally program the RF directly through CR regs, if supported by
1589 * the hardware. This is much faster than the older method.
1591 int zd_rfwrite_cr_locked(struct zd_chip
*chip
, u32 value
)
1593 struct zd_ioreq16 ioreqs
[] = {
1594 { CR244
, (value
>> 16) & 0xff },
1595 { CR243
, (value
>> 8) & 0xff },
1596 { CR242
, value
& 0xff },
1598 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
1599 return zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1602 int zd_rfwritev_cr_locked(struct zd_chip
*chip
,
1603 const u32
*values
, unsigned int count
)
1608 for (i
= 0; i
< count
; i
++) {
1609 r
= zd_rfwrite_cr_locked(chip
, values
[i
]);
1617 int zd_chip_set_multicast_hash(struct zd_chip
*chip
,
1618 struct zd_mc_hash
*hash
)
1620 struct zd_ioreq32 ioreqs
[] = {
1621 { CR_GROUP_HASH_P1
, hash
->low
},
1622 { CR_GROUP_HASH_P2
, hash
->high
},
1625 return zd_iowrite32a(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));