2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/interrupt.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/edma.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/spi_bitbang.h>
33 #include <linux/slab.h>
35 #include <linux/platform_data/spi-davinci.h>
37 #define SPI_NO_RESOURCE ((resource_size_t)-1)
39 #define SPI_MAX_CHIPSELECT 2
41 #define CS_DEFAULT 0xFF
43 #define SPIFMT_PHASE_MASK BIT(16)
44 #define SPIFMT_POLARITY_MASK BIT(17)
45 #define SPIFMT_DISTIMER_MASK BIT(18)
46 #define SPIFMT_SHIFTDIR_MASK BIT(20)
47 #define SPIFMT_WAITENA_MASK BIT(21)
48 #define SPIFMT_PARITYENA_MASK BIT(22)
49 #define SPIFMT_ODD_PARITY_MASK BIT(23)
50 #define SPIFMT_WDELAY_MASK 0x3f000000u
51 #define SPIFMT_WDELAY_SHIFT 24
52 #define SPIFMT_PRESCALE_SHIFT 8
55 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
56 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
57 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
58 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
60 #define SPIINT_MASKALL 0x0101035F
61 #define SPIINT_MASKINT 0x0000015F
62 #define SPI_INTLVL_1 0x000001FF
63 #define SPI_INTLVL_0 0x00000000
65 /* SPIDAT1 (upper 16 bit defines) */
66 #define SPIDAT1_CSHOLD_MASK BIT(12)
69 #define SPIGCR1_CLKMOD_MASK BIT(1)
70 #define SPIGCR1_MASTER_MASK BIT(0)
71 #define SPIGCR1_POWERDOWN_MASK BIT(8)
72 #define SPIGCR1_LOOPBACK_MASK BIT(16)
73 #define SPIGCR1_SPIENA_MASK BIT(24)
76 #define SPIBUF_TXFULL_MASK BIT(29)
77 #define SPIBUF_RXEMPTY_MASK BIT(31)
80 #define SPIDELAY_C2TDELAY_SHIFT 24
81 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
82 #define SPIDELAY_T2CDELAY_SHIFT 16
83 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
84 #define SPIDELAY_T2EDELAY_SHIFT 8
85 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
86 #define SPIDELAY_C2EDELAY_SHIFT 0
87 #define SPIDELAY_C2EDELAY_MASK 0xFF
90 #define SPIFLG_DLEN_ERR_MASK BIT(0)
91 #define SPIFLG_TIMEOUT_MASK BIT(1)
92 #define SPIFLG_PARERR_MASK BIT(2)
93 #define SPIFLG_DESYNC_MASK BIT(3)
94 #define SPIFLG_BITERR_MASK BIT(4)
95 #define SPIFLG_OVRRUN_MASK BIT(6)
96 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
97 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
98 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
99 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
100 | SPIFLG_OVRRUN_MASK)
102 #define SPIINT_DMA_REQ_EN BIT(16)
104 /* SPI Controller registers */
113 #define SPIDELAY 0x48
117 /* SPI Controller driver's private data. */
119 struct spi_bitbang bitbang
;
123 resource_size_t pbase
;
126 struct completion done
;
133 struct dma_chan
*dma_rx
;
134 struct dma_chan
*dma_tx
;
138 struct davinci_spi_platform_data
*pdata
;
140 void (*get_rx
)(u32 rx_data
, struct davinci_spi
*);
141 u32 (*get_tx
)(struct davinci_spi
*);
143 u8 bytes_per_word
[SPI_MAX_CHIPSELECT
];
146 static struct davinci_spi_config davinci_spi_default_cfg
;
148 static void davinci_spi_rx_buf_u8(u32 data
, struct davinci_spi
*dspi
)
157 static void davinci_spi_rx_buf_u16(u32 data
, struct davinci_spi
*dspi
)
166 static u32
davinci_spi_tx_buf_u8(struct davinci_spi
*dspi
)
170 const u8
*tx
= dspi
->tx
;
177 static u32
davinci_spi_tx_buf_u16(struct davinci_spi
*dspi
)
181 const u16
*tx
= dspi
->tx
;
188 static inline void set_io_bits(void __iomem
*addr
, u32 bits
)
190 u32 v
= ioread32(addr
);
196 static inline void clear_io_bits(void __iomem
*addr
, u32 bits
)
198 u32 v
= ioread32(addr
);
205 * Interface to control the chip select signal
207 static void davinci_spi_chipselect(struct spi_device
*spi
, int value
)
209 struct davinci_spi
*dspi
;
210 struct davinci_spi_platform_data
*pdata
;
211 u8 chip_sel
= spi
->chip_select
;
212 u16 spidat1
= CS_DEFAULT
;
213 bool gpio_chipsel
= false;
215 dspi
= spi_master_get_devdata(spi
->master
);
218 if (pdata
->chip_sel
&& chip_sel
< pdata
->num_chipselect
&&
219 pdata
->chip_sel
[chip_sel
] != SPI_INTERN_CS
)
223 * Board specific chip select logic decides the polarity and cs
224 * line for the controller
227 if (value
== BITBANG_CS_ACTIVE
)
228 gpio_set_value(pdata
->chip_sel
[chip_sel
], 0);
230 gpio_set_value(pdata
->chip_sel
[chip_sel
], 1);
232 if (value
== BITBANG_CS_ACTIVE
) {
233 spidat1
|= SPIDAT1_CSHOLD_MASK
;
234 spidat1
&= ~(0x1 << chip_sel
);
237 iowrite16(spidat1
, dspi
->base
+ SPIDAT1
+ 2);
242 * davinci_spi_get_prescale - Calculates the correct prescale value
243 * @maxspeed_hz: the maximum rate the SPI clock can run at
245 * This function calculates the prescale value that generates a clock rate
246 * less than or equal to the specified maximum.
248 * Returns: calculated prescale - 1 for easy programming into SPI registers
249 * or negative error number if valid prescalar cannot be updated.
251 static inline int davinci_spi_get_prescale(struct davinci_spi
*dspi
,
256 ret
= DIV_ROUND_UP(clk_get_rate(dspi
->clk
), max_speed_hz
);
258 if (ret
< 3 || ret
> 256)
265 * davinci_spi_setup_transfer - This functions will determine transfer method
266 * @spi: spi device on which data transfer to be done
267 * @t: spi transfer in which transfer info is filled
269 * This function determines data transfer method (8/16/32 bit transfer).
270 * It will also set the SPI Clock Control register according to
271 * SPI slave device freq.
273 static int davinci_spi_setup_transfer(struct spi_device
*spi
,
274 struct spi_transfer
*t
)
277 struct davinci_spi
*dspi
;
278 struct davinci_spi_config
*spicfg
;
279 u8 bits_per_word
= 0;
280 u32 hz
= 0, spifmt
= 0, prescale
= 0;
282 dspi
= spi_master_get_devdata(spi
->master
);
283 spicfg
= (struct davinci_spi_config
*)spi
->controller_data
;
285 spicfg
= &davinci_spi_default_cfg
;
288 bits_per_word
= t
->bits_per_word
;
292 /* if bits_per_word is not set then set it default */
294 bits_per_word
= spi
->bits_per_word
;
297 * Assign function pointer to appropriate transfer method
298 * 8bit, 16bit or 32bit transfer
300 if (bits_per_word
<= 8 && bits_per_word
>= 2) {
301 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
302 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
303 dspi
->bytes_per_word
[spi
->chip_select
] = 1;
304 } else if (bits_per_word
<= 16 && bits_per_word
>= 2) {
305 dspi
->get_rx
= davinci_spi_rx_buf_u16
;
306 dspi
->get_tx
= davinci_spi_tx_buf_u16
;
307 dspi
->bytes_per_word
[spi
->chip_select
] = 2;
312 hz
= spi
->max_speed_hz
;
314 /* Set up SPIFMTn register, unique to this chipselect. */
316 prescale
= davinci_spi_get_prescale(dspi
, hz
);
320 spifmt
= (prescale
<< SPIFMT_PRESCALE_SHIFT
) | (bits_per_word
& 0x1f);
322 if (spi
->mode
& SPI_LSB_FIRST
)
323 spifmt
|= SPIFMT_SHIFTDIR_MASK
;
325 if (spi
->mode
& SPI_CPOL
)
326 spifmt
|= SPIFMT_POLARITY_MASK
;
328 if (!(spi
->mode
& SPI_CPHA
))
329 spifmt
|= SPIFMT_PHASE_MASK
;
332 * Version 1 hardware supports two basic SPI modes:
333 * - Standard SPI mode uses 4 pins, with chipselect
334 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
335 * (distinct from SPI_3WIRE, with just one data wire;
336 * or similar variants without MOSI or without MISO)
338 * Version 2 hardware supports an optional handshaking signal,
339 * so it can support two more modes:
340 * - 5 pin SPI variant is standard SPI plus SPI_READY
341 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
344 if (dspi
->version
== SPI_VERSION_2
) {
348 spifmt
|= ((spicfg
->wdelay
<< SPIFMT_WDELAY_SHIFT
)
349 & SPIFMT_WDELAY_MASK
);
351 if (spicfg
->odd_parity
)
352 spifmt
|= SPIFMT_ODD_PARITY_MASK
;
354 if (spicfg
->parity_enable
)
355 spifmt
|= SPIFMT_PARITYENA_MASK
;
357 if (spicfg
->timer_disable
) {
358 spifmt
|= SPIFMT_DISTIMER_MASK
;
360 delay
|= (spicfg
->c2tdelay
<< SPIDELAY_C2TDELAY_SHIFT
)
361 & SPIDELAY_C2TDELAY_MASK
;
362 delay
|= (spicfg
->t2cdelay
<< SPIDELAY_T2CDELAY_SHIFT
)
363 & SPIDELAY_T2CDELAY_MASK
;
366 if (spi
->mode
& SPI_READY
) {
367 spifmt
|= SPIFMT_WAITENA_MASK
;
368 delay
|= (spicfg
->t2edelay
<< SPIDELAY_T2EDELAY_SHIFT
)
369 & SPIDELAY_T2EDELAY_MASK
;
370 delay
|= (spicfg
->c2edelay
<< SPIDELAY_C2EDELAY_SHIFT
)
371 & SPIDELAY_C2EDELAY_MASK
;
374 iowrite32(delay
, dspi
->base
+ SPIDELAY
);
377 iowrite32(spifmt
, dspi
->base
+ SPIFMT0
);
383 * davinci_spi_setup - This functions will set default transfer method
384 * @spi: spi device on which data transfer to be done
386 * This functions sets the default transfer method.
388 static int davinci_spi_setup(struct spi_device
*spi
)
391 struct davinci_spi
*dspi
;
392 struct davinci_spi_platform_data
*pdata
;
394 dspi
= spi_master_get_devdata(spi
->master
);
397 /* if bits per word length is zero then set it default 8 */
398 if (!spi
->bits_per_word
)
399 spi
->bits_per_word
= 8;
401 if (!(spi
->mode
& SPI_NO_CS
)) {
402 if ((pdata
->chip_sel
== NULL
) ||
403 (pdata
->chip_sel
[spi
->chip_select
] == SPI_INTERN_CS
))
404 set_io_bits(dspi
->base
+ SPIPC0
, 1 << spi
->chip_select
);
408 if (spi
->mode
& SPI_READY
)
409 set_io_bits(dspi
->base
+ SPIPC0
, SPIPC0_SPIENA_MASK
);
411 if (spi
->mode
& SPI_LOOP
)
412 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
414 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
419 static int davinci_spi_check_error(struct davinci_spi
*dspi
, int int_status
)
421 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
423 if (int_status
& SPIFLG_TIMEOUT_MASK
) {
424 dev_dbg(sdev
, "SPI Time-out Error\n");
427 if (int_status
& SPIFLG_DESYNC_MASK
) {
428 dev_dbg(sdev
, "SPI Desynchronization Error\n");
431 if (int_status
& SPIFLG_BITERR_MASK
) {
432 dev_dbg(sdev
, "SPI Bit error\n");
436 if (dspi
->version
== SPI_VERSION_2
) {
437 if (int_status
& SPIFLG_DLEN_ERR_MASK
) {
438 dev_dbg(sdev
, "SPI Data Length Error\n");
441 if (int_status
& SPIFLG_PARERR_MASK
) {
442 dev_dbg(sdev
, "SPI Parity Error\n");
445 if (int_status
& SPIFLG_OVRRUN_MASK
) {
446 dev_dbg(sdev
, "SPI Data Overrun error\n");
449 if (int_status
& SPIFLG_BUF_INIT_ACTIVE_MASK
) {
450 dev_dbg(sdev
, "SPI Buffer Init Active\n");
459 * davinci_spi_process_events - check for and handle any SPI controller events
460 * @dspi: the controller data
462 * This function will check the SPIFLG register and handle any events that are
465 static int davinci_spi_process_events(struct davinci_spi
*dspi
)
467 u32 buf
, status
, errors
= 0, spidat1
;
469 buf
= ioread32(dspi
->base
+ SPIBUF
);
471 if (dspi
->rcount
> 0 && !(buf
& SPIBUF_RXEMPTY_MASK
)) {
472 dspi
->get_rx(buf
& 0xFFFF, dspi
);
476 status
= ioread32(dspi
->base
+ SPIFLG
);
478 if (unlikely(status
& SPIFLG_ERROR_MASK
)) {
479 errors
= status
& SPIFLG_ERROR_MASK
;
483 if (dspi
->wcount
> 0 && !(buf
& SPIBUF_TXFULL_MASK
)) {
484 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
487 spidat1
|= 0xFFFF & dspi
->get_tx(dspi
);
488 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
495 static void davinci_spi_dma_rx_callback(void *data
)
497 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
501 if (!dspi
->wcount
&& !dspi
->rcount
)
502 complete(&dspi
->done
);
505 static void davinci_spi_dma_tx_callback(void *data
)
507 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
511 if (!dspi
->wcount
&& !dspi
->rcount
)
512 complete(&dspi
->done
);
516 * davinci_spi_bufs - functions which will handle transfer data
517 * @spi: spi device on which data transfer to be done
518 * @t: spi transfer in which transfer info is filled
520 * This function will put data to be transferred into data register
521 * of SPI controller and then wait until the completion will be marked
522 * by the IRQ Handler.
524 static int davinci_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
)
526 struct davinci_spi
*dspi
;
527 int data_type
, ret
= -ENOMEM
;
528 u32 tx_data
, spidat1
;
530 struct davinci_spi_config
*spicfg
;
531 struct davinci_spi_platform_data
*pdata
;
532 unsigned uninitialized_var(rx_buf_count
);
533 void *dummy_buf
= NULL
;
534 struct scatterlist sg_rx
, sg_tx
;
536 dspi
= spi_master_get_devdata(spi
->master
);
538 spicfg
= (struct davinci_spi_config
*)spi
->controller_data
;
540 spicfg
= &davinci_spi_default_cfg
;
542 /* convert len to words based on bits_per_word */
543 data_type
= dspi
->bytes_per_word
[spi
->chip_select
];
545 dspi
->tx
= t
->tx_buf
;
546 dspi
->rx
= t
->rx_buf
;
547 dspi
->wcount
= t
->len
/ data_type
;
548 dspi
->rcount
= dspi
->wcount
;
550 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
552 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
553 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
555 INIT_COMPLETION(dspi
->done
);
557 if (spicfg
->io_type
== SPI_IO_TYPE_INTR
)
558 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
560 if (spicfg
->io_type
!= SPI_IO_TYPE_DMA
) {
561 /* start the transfer */
563 tx_data
= dspi
->get_tx(dspi
);
564 spidat1
&= 0xFFFF0000;
565 spidat1
|= tx_data
& 0xFFFF;
566 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
568 struct dma_slave_config dma_rx_conf
= {
569 .direction
= DMA_DEV_TO_MEM
,
570 .src_addr
= (unsigned long)dspi
->pbase
+ SPIBUF
,
571 .src_addr_width
= data_type
,
574 struct dma_slave_config dma_tx_conf
= {
575 .direction
= DMA_MEM_TO_DEV
,
576 .dst_addr
= (unsigned long)dspi
->pbase
+ SPIDAT1
,
577 .dst_addr_width
= data_type
,
580 struct dma_async_tx_descriptor
*rxdesc
;
581 struct dma_async_tx_descriptor
*txdesc
;
584 dummy_buf
= kzalloc(t
->len
, GFP_KERNEL
);
586 goto err_alloc_dummy_buf
;
588 dmaengine_slave_config(dspi
->dma_rx
, &dma_rx_conf
);
589 dmaengine_slave_config(dspi
->dma_tx
, &dma_tx_conf
);
591 sg_init_table(&sg_rx
, 1);
596 t
->rx_dma
= dma_map_single(&spi
->dev
, buf
,
597 t
->len
, DMA_FROM_DEVICE
);
602 sg_dma_address(&sg_rx
) = t
->rx_dma
;
603 sg_dma_len(&sg_rx
) = t
->len
;
605 sg_init_table(&sg_tx
, 1);
609 buf
= (void *)t
->tx_buf
;
610 t
->tx_dma
= dma_map_single(&spi
->dev
, buf
,
611 t
->len
, DMA_FROM_DEVICE
);
616 sg_dma_address(&sg_tx
) = t
->tx_dma
;
617 sg_dma_len(&sg_tx
) = t
->len
;
619 rxdesc
= dmaengine_prep_slave_sg(dspi
->dma_rx
,
620 &sg_rx
, 1, DMA_DEV_TO_MEM
,
621 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
625 txdesc
= dmaengine_prep_slave_sg(dspi
->dma_tx
,
626 &sg_tx
, 1, DMA_MEM_TO_DEV
,
627 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
631 rxdesc
->callback
= davinci_spi_dma_rx_callback
;
632 rxdesc
->callback_param
= (void *)dspi
;
633 txdesc
->callback
= davinci_spi_dma_tx_callback
;
634 txdesc
->callback_param
= (void *)dspi
;
636 if (pdata
->cshold_bug
)
637 iowrite16(spidat1
>> 16, dspi
->base
+ SPIDAT1
+ 2);
639 dmaengine_submit(rxdesc
);
640 dmaengine_submit(txdesc
);
642 dma_async_issue_pending(dspi
->dma_rx
);
643 dma_async_issue_pending(dspi
->dma_tx
);
645 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
648 /* Wait for the transfer to complete */
649 if (spicfg
->io_type
!= SPI_IO_TYPE_POLL
) {
650 wait_for_completion_interruptible(&(dspi
->done
));
652 while (dspi
->rcount
> 0 || dspi
->wcount
> 0) {
653 errors
= davinci_spi_process_events(dspi
);
660 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKALL
);
661 if (spicfg
->io_type
== SPI_IO_TYPE_DMA
) {
662 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
664 dma_unmap_single(&spi
->dev
, t
->rx_dma
,
665 t
->len
, DMA_FROM_DEVICE
);
666 dma_unmap_single(&spi
->dev
, t
->tx_dma
,
667 t
->len
, DMA_TO_DEVICE
);
671 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
672 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
675 * Check for bit error, desync error,parity error,timeout error and
676 * receive overflow errors
679 ret
= davinci_spi_check_error(dspi
, errors
);
680 WARN(!ret
, "%s: error reported but no error found!\n",
681 dev_name(&spi
->dev
));
685 if (dspi
->rcount
!= 0 || dspi
->wcount
!= 0) {
686 dev_err(&spi
->dev
, "SPI data transfer error\n");
693 dma_unmap_single(&spi
->dev
, t
->tx_dma
, t
->len
, DMA_TO_DEVICE
);
695 dma_unmap_single(&spi
->dev
, t
->rx_dma
, t
->len
, DMA_FROM_DEVICE
);
703 * davinci_spi_irq - Interrupt handler for SPI Master Controller
704 * @irq: IRQ number for this SPI Master
705 * @context_data: structure for SPI Master controller davinci_spi
707 * ISR will determine that interrupt arrives either for READ or WRITE command.
708 * According to command it will do the appropriate action. It will check
709 * transfer length and if it is not zero then dispatch transfer command again.
710 * If transfer length is zero then it will indicate the COMPLETION so that
711 * davinci_spi_bufs function can go ahead.
713 static irqreturn_t
davinci_spi_irq(s32 irq
, void *data
)
715 struct davinci_spi
*dspi
= data
;
718 status
= davinci_spi_process_events(dspi
);
719 if (unlikely(status
!= 0))
720 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
722 if ((!dspi
->rcount
&& !dspi
->wcount
) || status
)
723 complete(&dspi
->done
);
728 static int davinci_spi_request_dma(struct davinci_spi
*dspi
)
731 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
735 dma_cap_set(DMA_SLAVE
, mask
);
737 dspi
->dma_rx
= dma_request_channel(mask
, edma_filter_fn
,
738 &dspi
->dma_rx_chnum
);
740 dev_err(sdev
, "request RX DMA channel failed\n");
745 dspi
->dma_tx
= dma_request_channel(mask
, edma_filter_fn
,
746 &dspi
->dma_tx_chnum
);
748 dev_err(sdev
, "request TX DMA channel failed\n");
756 dma_release_channel(dspi
->dma_rx
);
762 * davinci_spi_probe - probe function for SPI Master Controller
763 * @pdev: platform_device structure which contains plateform specific data
765 * According to Linux Device Model this function will be invoked by Linux
766 * with platform_device struct which contains the device specific info.
767 * This function will map the SPI controller's memory, register IRQ,
768 * Reset SPI controller and setting its registers to default value.
769 * It will invoke spi_bitbang_start to create work queue so that client driver
770 * can register transfer method to work queue.
772 static int __devinit
davinci_spi_probe(struct platform_device
*pdev
)
774 struct spi_master
*master
;
775 struct davinci_spi
*dspi
;
776 struct davinci_spi_platform_data
*pdata
;
777 struct resource
*r
, *mem
;
778 resource_size_t dma_rx_chan
= SPI_NO_RESOURCE
;
779 resource_size_t dma_tx_chan
= SPI_NO_RESOURCE
;
783 pdata
= pdev
->dev
.platform_data
;
789 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct davinci_spi
));
790 if (master
== NULL
) {
795 dev_set_drvdata(&pdev
->dev
, master
);
797 dspi
= spi_master_get_devdata(master
);
803 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
809 dspi
->pbase
= r
->start
;
812 mem
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
818 dspi
->base
= ioremap(r
->start
, resource_size(r
));
819 if (dspi
->base
== NULL
) {
824 dspi
->irq
= platform_get_irq(pdev
, 0);
825 if (dspi
->irq
<= 0) {
830 ret
= request_irq(dspi
->irq
, davinci_spi_irq
, 0, dev_name(&pdev
->dev
),
835 dspi
->bitbang
.master
= spi_master_get(master
);
836 if (dspi
->bitbang
.master
== NULL
) {
841 dspi
->clk
= clk_get(&pdev
->dev
, NULL
);
842 if (IS_ERR(dspi
->clk
)) {
846 clk_enable(dspi
->clk
);
848 master
->bus_num
= pdev
->id
;
849 master
->num_chipselect
= pdata
->num_chipselect
;
850 master
->setup
= davinci_spi_setup
;
852 dspi
->bitbang
.chipselect
= davinci_spi_chipselect
;
853 dspi
->bitbang
.setup_transfer
= davinci_spi_setup_transfer
;
855 dspi
->version
= pdata
->version
;
857 dspi
->bitbang
.flags
= SPI_NO_CS
| SPI_LSB_FIRST
| SPI_LOOP
;
858 if (dspi
->version
== SPI_VERSION_2
)
859 dspi
->bitbang
.flags
|= SPI_READY
;
861 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
863 dma_rx_chan
= r
->start
;
864 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
866 dma_tx_chan
= r
->start
;
868 dspi
->bitbang
.txrx_bufs
= davinci_spi_bufs
;
869 if (dma_rx_chan
!= SPI_NO_RESOURCE
&&
870 dma_tx_chan
!= SPI_NO_RESOURCE
) {
871 dspi
->dma_rx_chnum
= dma_rx_chan
;
872 dspi
->dma_tx_chnum
= dma_tx_chan
;
874 ret
= davinci_spi_request_dma(dspi
);
878 dev_info(&pdev
->dev
, "DMA: supported\n");
879 dev_info(&pdev
->dev
, "DMA: RX channel: %d, TX channel: %d, "
880 "event queue: %d\n", dma_rx_chan
, dma_tx_chan
,
884 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
885 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
887 init_completion(&dspi
->done
);
889 /* Reset In/OUT SPI module */
890 iowrite32(0, dspi
->base
+ SPIGCR0
);
892 iowrite32(1, dspi
->base
+ SPIGCR0
);
894 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
895 spipc0
= SPIPC0_DIFUN_MASK
| SPIPC0_DOFUN_MASK
| SPIPC0_CLKFUN_MASK
;
896 iowrite32(spipc0
, dspi
->base
+ SPIPC0
);
898 /* initialize chip selects */
899 if (pdata
->chip_sel
) {
900 for (i
= 0; i
< pdata
->num_chipselect
; i
++) {
901 if (pdata
->chip_sel
[i
] != SPI_INTERN_CS
)
902 gpio_direction_output(pdata
->chip_sel
[i
], 1);
906 if (pdata
->intr_line
)
907 iowrite32(SPI_INTLVL_1
, dspi
->base
+ SPILVL
);
909 iowrite32(SPI_INTLVL_0
, dspi
->base
+ SPILVL
);
911 iowrite32(CS_DEFAULT
, dspi
->base
+ SPIDEF
);
913 /* master mode default */
914 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_CLKMOD_MASK
);
915 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_MASTER_MASK
);
916 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
918 ret
= spi_bitbang_start(&dspi
->bitbang
);
922 dev_info(&pdev
->dev
, "Controller at 0x%p\n", dspi
->base
);
927 dma_release_channel(dspi
->dma_rx
);
928 dma_release_channel(dspi
->dma_tx
);
930 clk_disable(dspi
->clk
);
933 spi_master_put(master
);
935 free_irq(dspi
->irq
, dspi
);
939 release_mem_region(dspi
->pbase
, resource_size(r
));
947 * davinci_spi_remove - remove function for SPI Master Controller
948 * @pdev: platform_device structure which contains plateform specific data
950 * This function will do the reverse action of davinci_spi_probe function
951 * It will free the IRQ and SPI controller's memory region.
952 * It will also call spi_bitbang_stop to destroy the work queue which was
953 * created by spi_bitbang_start.
955 static int __devexit
davinci_spi_remove(struct platform_device
*pdev
)
957 struct davinci_spi
*dspi
;
958 struct spi_master
*master
;
961 master
= dev_get_drvdata(&pdev
->dev
);
962 dspi
= spi_master_get_devdata(master
);
964 spi_bitbang_stop(&dspi
->bitbang
);
966 clk_disable(dspi
->clk
);
968 spi_master_put(master
);
969 free_irq(dspi
->irq
, dspi
);
971 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
972 release_mem_region(dspi
->pbase
, resource_size(r
));
977 static struct platform_driver davinci_spi_driver
= {
979 .name
= "spi_davinci",
980 .owner
= THIS_MODULE
,
982 .probe
= davinci_spi_probe
,
983 .remove
= __devexit_p(davinci_spi_remove
),
985 module_platform_driver(davinci_spi_driver
);
987 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
988 MODULE_LICENSE("GPL");