1 #include <linux/linkage.h>
2 #include <linux/init.h>
3 #include <asm/segment.h>
4 #include <asm/page_types.h>
5 #include <asm/processor-flags.h>
6 #include <asm/msr-index.h>
10 * The following code and data reboots the machine by switching to real
11 * mode and jumping to the BIOS reset entry point, as if the CPU has
12 * really been reset. The previous version asked the keyboard
13 * controller to pulse the CPU reset line, which is more thorough, but
14 * doesn't work with at least one type of 486 motherboard. It is easy
15 * to stop this code working; hence the copious comments.
17 * This code is called with the restart type (0 = BIOS, 1 = APM) in
18 * the primary argument register (%eax for 32 bit, %edi for 64 bit).
20 .section ".text32", "ax"
22 ENTRY(machine_real_restart_asm)
25 /* Switch to trampoline GDT as it is guaranteed < 4 GiB */
26 movl $__KERNEL_DS, %eax
30 /* Disable paging to drop us out of long mode */
32 andl $~X86_CR0_PG, %eax
34 ljmpl $__KERNEL32_CS, $pa_machine_real_restart_paging_off
36 GLOBAL(machine_real_restart_paging_off)
44 #endif /* CONFIG_X86_64 */
46 /* Set up the IDT for real mode. */
47 lidtl pa_machine_real_restart_idt
50 * Set up a GDT from which we can load segment descriptors for real
51 * mode. The GDT is not used in real mode; it is just needed here to
52 * prepare the descriptors.
54 lgdtl pa_machine_real_restart_gdt
57 * Load the data segment registers with 16-bit compatible values
68 * This is 16-bit protected mode code to disable paging and the cache,
69 * switch to real mode and jump to the BIOS reset code.
71 * The instruction that switches to real mode by writing to CR0 must be
72 * followed immediately by a far jump instruction, which set CS to a
73 * valid value for real mode, and flushes the prefetch queue to avoid
74 * running instructions that have already been decoded in protected
77 * Clears all the flags except ET, especially PG (paging), PE
78 * (protected-mode enable) and TS (task switch for coprocessor state
79 * save). Flushes the TLB after paging has been disabled. Sets CD and
80 * NW, to disable the cache on a 486, and invalidates the cache. This
81 * is more like the state of a 486 after reset. I don't know if
82 * something else should be done for other chips.
84 * More could be done here to set up the registers as if a CPU reset had
85 * occurred; hopefully real BIOSs don't assume much. This is not the
86 * actual BIOS entry point, anyway (that is at 0xfffffff0).
88 * Most of this work is probably excessive, but it is what is tested.
94 machine_real_restart_asm16:
98 andl $0x00000011, %edx
103 testl $0x60000000, %edx /* If no cache bits -> no wbinvd */
122 /* This should never return... */
125 ljmpw $0xf000, $0xfff0
127 .section ".rodata", "a"
130 GLOBAL(machine_real_restart_idt)
131 .word 0xffff /* Length - real mode default value */
132 .long 0 /* Base - real mode default value */
133 END(machine_real_restart_idt)
136 GLOBAL(machine_real_restart_gdt)
138 .word 0xffff /* Length - real mode default value */
139 .long pa_machine_real_restart_gdt
143 * 16-bit code segment pointing to real_mode_seg
146 .word 0xffff /* Limit */
147 .long 0x9b000000 + pa_real_mode_base
151 * 16-bit data segment with the selector value 16 = 0x10 and
152 * base value 0x100; since this is consistent with real mode
153 * semantics we don't have to reload the segments once CR0.PE = 0.
155 .quad GDT_ENTRY(0x0093, 0x100, 0xffff)
156 END(machine_real_restart_gdt)