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[PATCH] Driver core: PM_DEBUG device suspend() messages become informative
[linux-2.6.git] / drivers / pci / probe.c
bloba10ed9dab2c2d5a04327760de02e140c20ef6f2c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 #ifdef HAVE_PCI_LEGACY
26 /**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34 static void pci_create_legacy_files(struct pci_bus *b)
35 {
36 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 b->legacy_io->attr.name = "legacy_io";
40 b->legacy_io->size = 0xffff;
41 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
42 b->legacy_io->attr.owner = THIS_MODULE;
43 b->legacy_io->read = pci_read_legacy_io;
44 b->legacy_io->write = pci_write_legacy_io;
45 class_device_create_bin_file(&b->class_dev, b->legacy_io);
46
47 /* Allocated above after the legacy_io struct */
48 b->legacy_mem = b->legacy_io + 1;
49 b->legacy_mem->attr.name = "legacy_mem";
50 b->legacy_mem->size = 1024*1024;
51 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
52 b->legacy_mem->attr.owner = THIS_MODULE;
53 b->legacy_mem->mmap = pci_mmap_legacy_mem;
54 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
55 }
56 }
57
58 void pci_remove_legacy_files(struct pci_bus *b)
59 {
60 if (b->legacy_io) {
61 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
62 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
63 kfree(b->legacy_io); /* both are allocated here */
64 }
65 }
66 #else /* !HAVE_PCI_LEGACY */
67 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
68 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
69 #endif /* HAVE_PCI_LEGACY */
70
71 /*
72 * PCI Bus Class Devices
73 */
74 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
75 char *buf)
76 {
77 int ret;
78 cpumask_t cpumask;
79
80 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
81 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
82 if (ret < PAGE_SIZE)
83 buf[ret++] = '\n';
84 return ret;
85 }
86 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
87
88 /*
89 * PCI Bus Class
90 */
91 static void release_pcibus_dev(struct class_device *class_dev)
92 {
93 struct pci_bus *pci_bus = to_pci_bus(class_dev);
94
95 if (pci_bus->bridge)
96 put_device(pci_bus->bridge);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .release = &release_pcibus_dev,
103 };
104
105 static int __init pcibus_class_init(void)
106 {
107 return class_register(&pcibus_class);
108 }
109 postcore_initcall(pcibus_class_init);
110
111 /*
112 * Translate the low bits of the PCI base
113 * to the resource type
114 */
115 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
116 {
117 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
118 return IORESOURCE_IO;
119
120 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
121 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
122
123 return IORESOURCE_MEM;
124 }
125
126 /*
127 * Find the extent of a PCI decode..
128 */
129 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
130 {
131 u32 size = mask & maxbase; /* Find the significant bits */
132 if (!size)
133 return 0;
134
135 /* Get the lowest of them to find the decode size, and
136 from that the extent. */
137 size = (size & ~(size-1)) - 1;
138
139 /* base == maxbase can be valid only if the BAR has
140 already been programmed with all 1s. */
141 if (base == maxbase && ((base | size) & mask) != mask)
142 return 0;
143
144 return size;
145 }
146
147 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
148 {
149 unsigned int pos, reg, next;
150 u32 l, sz;
151 struct resource *res;
152
153 for(pos=0; pos<howmany; pos = next) {
154 next = pos+1;
155 res = &dev->resource[pos];
156 res->name = pci_name(dev);
157 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
158 pci_read_config_dword(dev, reg, &l);
159 pci_write_config_dword(dev, reg, ~0);
160 pci_read_config_dword(dev, reg, &sz);
161 pci_write_config_dword(dev, reg, l);
162 if (!sz || sz == 0xffffffff)
163 continue;
164 if (l == 0xffffffff)
165 l = 0;
166 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
167 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
168 if (!sz)
169 continue;
170 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
171 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
172 } else {
173 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
174 if (!sz)
175 continue;
176 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
177 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
178 }
179 res->end = res->start + (unsigned long) sz;
180 res->flags |= pci_calc_resource_flags(l);
181 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
182 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
183 pci_read_config_dword(dev, reg+4, &l);
184 next++;
185 #if BITS_PER_LONG == 64
186 res->start |= ((unsigned long) l) << 32;
187 res->end = res->start + sz;
188 pci_write_config_dword(dev, reg+4, ~0);
189 pci_read_config_dword(dev, reg+4, &sz);
190 pci_write_config_dword(dev, reg+4, l);
191 sz = pci_size(l, sz, 0xffffffff);
192 if (sz) {
193 /* This BAR needs > 4GB? Wow. */
194 res->end |= (unsigned long)sz<<32;
195 }
196 #else
197 if (l) {
198 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
199 res->start = 0;
200 res->flags = 0;
201 continue;
202 }
203 #endif
204 }
205 }
206 if (rom) {
207 dev->rom_base_reg = rom;
208 res = &dev->resource[PCI_ROM_RESOURCE];
209 res->name = pci_name(dev);
210 pci_read_config_dword(dev, rom, &l);
211 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
212 pci_read_config_dword(dev, rom, &sz);
213 pci_write_config_dword(dev, rom, l);
214 if (l == 0xffffffff)
215 l = 0;
216 if (sz && sz != 0xffffffff) {
217 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
218 if (sz) {
219 res->flags = (l & IORESOURCE_ROM_ENABLE) |
220 IORESOURCE_MEM | IORESOURCE_PREFETCH |
221 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
222 res->start = l & PCI_ROM_ADDRESS_MASK;
223 res->end = res->start + (unsigned long) sz;
224 }
225 }
226 }
227 }
228
229 void __devinit pci_read_bridge_bases(struct pci_bus *child)
230 {
231 struct pci_dev *dev = child->self;
232 u8 io_base_lo, io_limit_lo;
233 u16 mem_base_lo, mem_limit_lo;
234 unsigned long base, limit;
235 struct resource *res;
236 int i;
237
238 if (!dev) /* It's a host bus, nothing to read */
239 return;
240
241 if (dev->transparent) {
242 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
243 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
244 child->resource[i] = child->parent->resource[i - 3];
245 }
246
247 for(i=0; i<3; i++)
248 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
249
250 res = child->resource[0];
251 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
252 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
253 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
254 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
255
256 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
257 u16 io_base_hi, io_limit_hi;
258 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
259 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
260 base |= (io_base_hi << 16);
261 limit |= (io_limit_hi << 16);
262 }
263
264 if (base <= limit) {
265 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
266 if (!res->start)
267 res->start = base;
268 if (!res->end)
269 res->end = limit + 0xfff;
270 }
271
272 res = child->resource[1];
273 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
274 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
275 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
276 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
277 if (base <= limit) {
278 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
279 res->start = base;
280 res->end = limit + 0xfffff;
281 }
282
283 res = child->resource[2];
284 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
285 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
286 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
287 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
288
289 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
290 u32 mem_base_hi, mem_limit_hi;
291 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
292 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
293
294 /*
295 * Some bridges set the base > limit by default, and some
296 * (broken) BIOSes do not initialize them. If we find
297 * this, just assume they are not being used.
298 */
299 if (mem_base_hi <= mem_limit_hi) {
300 #if BITS_PER_LONG == 64
301 base |= ((long) mem_base_hi) << 32;
302 limit |= ((long) mem_limit_hi) << 32;
303 #else
304 if (mem_base_hi || mem_limit_hi) {
305 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
306 return;
307 }
308 #endif
309 }
310 }
311 if (base <= limit) {
312 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
313 res->start = base;
314 res->end = limit + 0xfffff;
315 }
316 }
317
318 static struct pci_bus * __devinit pci_alloc_bus(void)
319 {
320 struct pci_bus *b;
321
322 b = kzalloc(sizeof(*b), GFP_KERNEL);
323 if (b) {
324 INIT_LIST_HEAD(&b->node);
325 INIT_LIST_HEAD(&b->children);
326 INIT_LIST_HEAD(&b->devices);
327 }
328 return b;
329 }
330
331 static struct pci_bus * __devinit
332 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
333 {
334 struct pci_bus *child;
335 int i;
336
337 /*
338 * Allocate a new bus, and inherit stuff from the parent..
339 */
340 child = pci_alloc_bus();
341 if (!child)
342 return NULL;
343
344 child->self = bridge;
345 child->parent = parent;
346 child->ops = parent->ops;
347 child->sysdata = parent->sysdata;
348 child->bus_flags = parent->bus_flags;
349 child->bridge = get_device(&bridge->dev);
350
351 child->class_dev.class = &pcibus_class;
352 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
353 class_device_register(&child->class_dev);
354 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
355
356 /*
357 * Set up the primary, secondary and subordinate
358 * bus numbers.
359 */
360 child->number = child->secondary = busnr;
361 child->primary = parent->secondary;
362 child->subordinate = 0xff;
363
364 /* Set up default resource pointers and names.. */
365 for (i = 0; i < 4; i++) {
366 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
367 child->resource[i]->name = child->name;
368 }
369 bridge->subordinate = child;
370
371 return child;
372 }
373
374 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
375 {
376 struct pci_bus *child;
377
378 child = pci_alloc_child_bus(parent, dev, busnr);
379 if (child) {
380 spin_lock(&pci_bus_lock);
381 list_add_tail(&child->node, &parent->children);
382 spin_unlock(&pci_bus_lock);
383 }
384 return child;
385 }
386
387 static void pci_enable_crs(struct pci_dev *dev)
388 {
389 u16 cap, rpctl;
390 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
391 if (!rpcap)
392 return;
393
394 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
395 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
396 return;
397
398 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
399 rpctl |= PCI_EXP_RTCTL_CRSSVE;
400 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
401 }
402
403 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
404 {
405 struct pci_bus *parent = child->parent;
406
407 /* Attempts to fix that up are really dangerous unless
408 we're going to re-assign all bus numbers. */
409 if (!pcibios_assign_all_busses())
410 return;
411
412 while (parent->parent && parent->subordinate < max) {
413 parent->subordinate = max;
414 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
415 parent = parent->parent;
416 }
417 }
418
419 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
420
421 /*
422 * If it's a bridge, configure it and scan the bus behind it.
423 * For CardBus bridges, we don't scan behind as the devices will
424 * be handled by the bridge driver itself.
425 *
426 * We need to process bridges in two passes -- first we scan those
427 * already configured by the BIOS and after we are done with all of
428 * them, we proceed to assigning numbers to the remaining buses in
429 * order to avoid overlaps between old and new bus numbers.
430 */
431 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
432 {
433 struct pci_bus *child;
434 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
435 u32 buses, i, j = 0;
436 u16 bctl;
437
438 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
439
440 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
441 pci_name(dev), buses & 0xffffff, pass);
442
443 /* Disable MasterAbortMode during probing to avoid reporting
444 of bus errors (in some architectures) */
445 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
446 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
447 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
448
449 pci_enable_crs(dev);
450
451 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
452 unsigned int cmax, busnr;
453 /*
454 * Bus already configured by firmware, process it in the first
455 * pass and just note the configuration.
456 */
457 if (pass)
458 goto out;
459 busnr = (buses >> 8) & 0xFF;
460
461 /*
462 * If we already got to this bus through a different bridge,
463 * ignore it. This can happen with the i450NX chipset.
464 */
465 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
466 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
467 pci_domain_nr(bus), busnr);
468 goto out;
469 }
470
471 child = pci_add_new_bus(bus, dev, busnr);
472 if (!child)
473 goto out;
474 child->primary = buses & 0xFF;
475 child->subordinate = (buses >> 16) & 0xFF;
476 child->bridge_ctl = bctl;
477
478 cmax = pci_scan_child_bus(child);
479 if (cmax > max)
480 max = cmax;
481 if (child->subordinate > max)
482 max = child->subordinate;
483 } else {
484 /*
485 * We need to assign a number to this bus which we always
486 * do in the second pass.
487 */
488 if (!pass) {
489 if (pcibios_assign_all_busses())
490 /* Temporarily disable forwarding of the
491 configuration cycles on all bridges in
492 this bus segment to avoid possible
493 conflicts in the second pass between two
494 bridges programmed with overlapping
495 bus ranges. */
496 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
497 buses & ~0xffffff);
498 goto out;
499 }
500
501 /* Clear errors */
502 pci_write_config_word(dev, PCI_STATUS, 0xffff);
503
504 /* Prevent assigning a bus number that already exists.
505 * This can happen when a bridge is hot-plugged */
506 if (pci_find_bus(pci_domain_nr(bus), max+1))
507 goto out;
508 child = pci_add_new_bus(bus, dev, ++max);
509 buses = (buses & 0xff000000)
510 | ((unsigned int)(child->primary) << 0)
511 | ((unsigned int)(child->secondary) << 8)
512 | ((unsigned int)(child->subordinate) << 16);
513
514 /*
515 * yenta.c forces a secondary latency timer of 176.
516 * Copy that behaviour here.
517 */
518 if (is_cardbus) {
519 buses &= ~0xff000000;
520 buses |= CARDBUS_LATENCY_TIMER << 24;
521 }
522
523 /*
524 * We need to blast all three values with a single write.
525 */
526 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
527
528 if (!is_cardbus) {
529 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
530 /*
531 * Adjust subordinate busnr in parent buses.
532 * We do this before scanning for children because
533 * some devices may not be detected if the bios
534 * was lazy.
535 */
536 pci_fixup_parent_subordinate_busnr(child, max);
537 /* Now we can scan all subordinate buses... */
538 max = pci_scan_child_bus(child);
539 /*
540 * now fix it up again since we have found
541 * the real value of max.
542 */
543 pci_fixup_parent_subordinate_busnr(child, max);
544 } else {
545 /*
546 * For CardBus bridges, we leave 4 bus numbers
547 * as cards with a PCI-to-PCI bridge can be
548 * inserted later.
549 */
550 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
551 struct pci_bus *parent = bus;
552 if (pci_find_bus(pci_domain_nr(bus),
553 max+i+1))
554 break;
555 while (parent->parent) {
556 if ((!pcibios_assign_all_busses()) &&
557 (parent->subordinate > max) &&
558 (parent->subordinate <= max+i)) {
559 j = 1;
560 }
561 parent = parent->parent;
562 }
563 if (j) {
564 /*
565 * Often, there are two cardbus bridges
566 * -- try to leave one valid bus number
567 * for each one.
568 */
569 i /= 2;
570 break;
571 }
572 }
573 max += i;
574 pci_fixup_parent_subordinate_busnr(child, max);
575 }
576 /*
577 * Set the subordinate bus number to its real value.
578 */
579 child->subordinate = max;
580 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
581 }
582
583 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
584
585 while (bus->parent) {
586 if ((child->subordinate > bus->subordinate) ||
587 (child->number > bus->subordinate) ||
588 (child->number < bus->number) ||
589 (child->subordinate < bus->number)) {
590 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) is "
591 "hidden behind%s bridge #%02x (-#%02x)%s\n",
592 child->number, child->subordinate,
593 bus->self->transparent ? " transparent" : " ",
594 bus->number, bus->subordinate,
595 pcibios_assign_all_busses() ? " " :
596 " (try 'pci=assign-busses')");
597 printk(KERN_WARNING "Please report the result to "
598 "linux-kernel to fix this permanently\n");
599 }
600 bus = bus->parent;
601 }
602
603 out:
604 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
605
606 return max;
607 }
608
609 /*
610 * Read interrupt line and base address registers.
611 * The architecture-dependent code can tweak these, of course.
612 */
613 static void pci_read_irq(struct pci_dev *dev)
614 {
615 unsigned char irq;
616
617 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
618 dev->pin = irq;
619 if (irq)
620 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
621 dev->irq = irq;
622 }
623
624 /**
625 * pci_setup_device - fill in class and map information of a device
626 * @dev: the device structure to fill
627 *
628 * Initialize the device structure with information about the device's
629 * vendor,class,memory and IO-space addresses,IRQ lines etc.
630 * Called at initialisation of the PCI subsystem and by CardBus services.
631 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
632 * or CardBus).
633 */
634 static int pci_setup_device(struct pci_dev * dev)
635 {
636 u32 class;
637
638 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
639 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
640
641 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
642 class >>= 8; /* upper 3 bytes */
643 dev->class = class;
644 class >>= 8;
645
646 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
647 dev->vendor, dev->device, class, dev->hdr_type);
648
649 /* "Unknown power state" */
650 dev->current_state = PCI_UNKNOWN;
651
652 /* Early fixups, before probing the BARs */
653 pci_fixup_device(pci_fixup_early, dev);
654 class = dev->class >> 8;
655
656 switch (dev->hdr_type) { /* header type */
657 case PCI_HEADER_TYPE_NORMAL: /* standard header */
658 if (class == PCI_CLASS_BRIDGE_PCI)
659 goto bad;
660 pci_read_irq(dev);
661 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
662 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
663 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
664 break;
665
666 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
667 if (class != PCI_CLASS_BRIDGE_PCI)
668 goto bad;
669 /* The PCI-to-PCI bridge spec requires that subtractive
670 decoding (i.e. transparent) bridge must have programming
671 interface code of 0x01. */
672 pci_read_irq(dev);
673 dev->transparent = ((dev->class & 0xff) == 1);
674 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
675 break;
676
677 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
678 if (class != PCI_CLASS_BRIDGE_CARDBUS)
679 goto bad;
680 pci_read_irq(dev);
681 pci_read_bases(dev, 1, 0);
682 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
683 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
684 break;
685
686 default: /* unknown header */
687 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
688 pci_name(dev), dev->hdr_type);
689 return -1;
690
691 bad:
692 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
693 pci_name(dev), class, dev->hdr_type);
694 dev->class = PCI_CLASS_NOT_DEFINED;
695 }
696
697 /* We found a fine healthy device, go go go... */
698 return 0;
699 }
700
701 /**
702 * pci_release_dev - free a pci device structure when all users of it are finished.
703 * @dev: device that's been disconnected
704 *
705 * Will be called only by the device core when all users of this pci device are
706 * done.
707 */
708 static void pci_release_dev(struct device *dev)
709 {
710 struct pci_dev *pci_dev;
711
712 pci_dev = to_pci_dev(dev);
713 kfree(pci_dev);
714 }
715
716 /**
717 * pci_cfg_space_size - get the configuration space size of the PCI device.
718 * @dev: PCI device
719 *
720 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
721 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
722 * access it. Maybe we don't have a way to generate extended config space
723 * accesses, or the device is behind a reverse Express bridge. So we try
724 * reading the dword at 0x100 which must either be 0 or a valid extended
725 * capability header.
726 */
727 int pci_cfg_space_size(struct pci_dev *dev)
728 {
729 int pos;
730 u32 status;
731
732 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
733 if (!pos) {
734 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
735 if (!pos)
736 goto fail;
737
738 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
739 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
740 goto fail;
741 }
742
743 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
744 goto fail;
745 if (status == 0xffffffff)
746 goto fail;
747
748 return PCI_CFG_SPACE_EXP_SIZE;
749
750 fail:
751 return PCI_CFG_SPACE_SIZE;
752 }
753
754 static void pci_release_bus_bridge_dev(struct device *dev)
755 {
756 kfree(dev);
757 }
758
759 /*
760 * Read the config data for a PCI device, sanity-check it
761 * and fill in the dev structure...
762 */
763 static struct pci_dev * __devinit
764 pci_scan_device(struct pci_bus *bus, int devfn)
765 {
766 struct pci_dev *dev;
767 u32 l;
768 u8 hdr_type;
769 int delay = 1;
770
771 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
772 return NULL;
773
774 /* some broken boards return 0 or ~0 if a slot is empty: */
775 if (l == 0xffffffff || l == 0x00000000 ||
776 l == 0x0000ffff || l == 0xffff0000)
777 return NULL;
778
779 /* Configuration request Retry Status */
780 while (l == 0xffff0001) {
781 msleep(delay);
782 delay *= 2;
783 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
784 return NULL;
785 /* Card hasn't responded in 60 seconds? Must be stuck. */
786 if (delay > 60 * 1000) {
787 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
788 "responding\n", pci_domain_nr(bus),
789 bus->number, PCI_SLOT(devfn),
790 PCI_FUNC(devfn));
791 return NULL;
792 }
793 }
794
795 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
796 return NULL;
797
798 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
799 if (!dev)
800 return NULL;
801
802 dev->bus = bus;
803 dev->sysdata = bus->sysdata;
804 dev->dev.parent = bus->bridge;
805 dev->dev.bus = &pci_bus_type;
806 dev->devfn = devfn;
807 dev->hdr_type = hdr_type & 0x7f;
808 dev->multifunction = !!(hdr_type & 0x80);
809 dev->vendor = l & 0xffff;
810 dev->device = (l >> 16) & 0xffff;
811 dev->cfg_size = pci_cfg_space_size(dev);
812
813 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
814 set this higher, assuming the system even supports it. */
815 dev->dma_mask = 0xffffffff;
816 if (pci_setup_device(dev) < 0) {
817 kfree(dev);
818 return NULL;
819 }
820
821 return dev;
822 }
823
824 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
825 {
826 device_initialize(&dev->dev);
827 dev->dev.release = pci_release_dev;
828 pci_dev_get(dev);
829
830 dev->dev.dma_mask = &dev->dma_mask;
831 dev->dev.coherent_dma_mask = 0xffffffffull;
832
833 /* Fix up broken headers */
834 pci_fixup_device(pci_fixup_header, dev);
835
836 /*
837 * Add the device to our list of discovered devices
838 * and the bus list for fixup functions, etc.
839 */
840 INIT_LIST_HEAD(&dev->global_list);
841 spin_lock(&pci_bus_lock);
842 list_add_tail(&dev->bus_list, &bus->devices);
843 spin_unlock(&pci_bus_lock);
844 }
845
846 struct pci_dev * __devinit
847 pci_scan_single_device(struct pci_bus *bus, int devfn)
848 {
849 struct pci_dev *dev;
850
851 dev = pci_scan_device(bus, devfn);
852 if (!dev)
853 return NULL;
854
855 pci_device_add(dev, bus);
856 pci_scan_msi_device(dev);
857
858 return dev;
859 }
860
861 /**
862 * pci_scan_slot - scan a PCI slot on a bus for devices.
863 * @bus: PCI bus to scan
864 * @devfn: slot number to scan (must have zero function.)
865 *
866 * Scan a PCI slot on the specified PCI bus for devices, adding
867 * discovered devices to the @bus->devices list. New devices
868 * will have an empty dev->global_list head.
869 */
870 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
871 {
872 int func, nr = 0;
873 int scan_all_fns;
874
875 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
876
877 for (func = 0; func < 8; func++, devfn++) {
878 struct pci_dev *dev;
879
880 dev = pci_scan_single_device(bus, devfn);
881 if (dev) {
882 nr++;
883
884 /*
885 * If this is a single function device,
886 * don't scan past the first function.
887 */
888 if (!dev->multifunction) {
889 if (func > 0) {
890 dev->multifunction = 1;
891 } else {
892 break;
893 }
894 }
895 } else {
896 if (func == 0 && !scan_all_fns)
897 break;
898 }
899 }
900 return nr;
901 }
902
903 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
904 {
905 unsigned int devfn, pass, max = bus->secondary;
906 struct pci_dev *dev;
907
908 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
909
910 /* Go find them, Rover! */
911 for (devfn = 0; devfn < 0x100; devfn += 8)
912 pci_scan_slot(bus, devfn);
913
914 /*
915 * After performing arch-dependent fixup of the bus, look behind
916 * all PCI-to-PCI bridges on this bus.
917 */
918 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
919 pcibios_fixup_bus(bus);
920 for (pass=0; pass < 2; pass++)
921 list_for_each_entry(dev, &bus->devices, bus_list) {
922 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
923 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
924 max = pci_scan_bridge(bus, dev, max, pass);
925 }
926
927 /*
928 * We've scanned the bus and so we know all about what's on
929 * the other side of any bridges that may be on this bus plus
930 * any devices.
931 *
932 * Return how far we've got finding sub-buses.
933 */
934 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
935 pci_domain_nr(bus), bus->number, max);
936 return max;
937 }
938
939 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
940 {
941 unsigned int max;
942
943 max = pci_scan_child_bus(bus);
944
945 /*
946 * Make the discovered devices available.
947 */
948 pci_bus_add_devices(bus);
949
950 return max;
951 }
952
953 struct pci_bus * __devinit pci_create_bus(struct device *parent,
954 int bus, struct pci_ops *ops, void *sysdata)
955 {
956 int error;
957 struct pci_bus *b;
958 struct device *dev;
959
960 b = pci_alloc_bus();
961 if (!b)
962 return NULL;
963
964 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
965 if (!dev){
966 kfree(b);
967 return NULL;
968 }
969
970 b->sysdata = sysdata;
971 b->ops = ops;
972
973 if (pci_find_bus(pci_domain_nr(b), bus)) {
974 /* If we already got to this bus through a different bridge, ignore it */
975 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
976 goto err_out;
977 }
978 spin_lock(&pci_bus_lock);
979 list_add_tail(&b->node, &pci_root_buses);
980 spin_unlock(&pci_bus_lock);
981
982 memset(dev, 0, sizeof(*dev));
983 dev->parent = parent;
984 dev->release = pci_release_bus_bridge_dev;
985 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
986 error = device_register(dev);
987 if (error)
988 goto dev_reg_err;
989 b->bridge = get_device(dev);
990
991 b->class_dev.class = &pcibus_class;
992 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
993 error = class_device_register(&b->class_dev);
994 if (error)
995 goto class_dev_reg_err;
996 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
997 if (error)
998 goto class_dev_create_file_err;
999
1000 /* Create legacy_io and legacy_mem files for this bus */
1001 pci_create_legacy_files(b);
1002
1003 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1004 if (error)
1005 goto sys_create_link_err;
1006
1007 b->number = b->secondary = bus;
1008 b->resource[0] = &ioport_resource;
1009 b->resource[1] = &iomem_resource;
1010
1011 return b;
1012
1013 sys_create_link_err:
1014 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1015 class_dev_create_file_err:
1016 class_device_unregister(&b->class_dev);
1017 class_dev_reg_err:
1018 device_unregister(dev);
1019 dev_reg_err:
1020 spin_lock(&pci_bus_lock);
1021 list_del(&b->node);
1022 spin_unlock(&pci_bus_lock);
1023 err_out:
1024 kfree(dev);
1025 kfree(b);
1026 return NULL;
1027 }
1028 EXPORT_SYMBOL_GPL(pci_create_bus);
1029
1030 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1031 int bus, struct pci_ops *ops, void *sysdata)
1032 {
1033 struct pci_bus *b;
1034
1035 b = pci_create_bus(parent, bus, ops, sysdata);
1036 if (b)
1037 b->subordinate = pci_scan_child_bus(b);
1038 return b;
1039 }
1040 EXPORT_SYMBOL(pci_scan_bus_parented);
1041
1042 #ifdef CONFIG_HOTPLUG
1043 EXPORT_SYMBOL(pci_add_new_bus);
1044 EXPORT_SYMBOL(pci_do_scan_bus);
1045 EXPORT_SYMBOL(pci_scan_slot);
1046 EXPORT_SYMBOL(pci_scan_bridge);
1047 EXPORT_SYMBOL(pci_scan_single_device);
1048 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1049 #endif
Linus' kernel tree