drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #ifndef __iwl_trans_int_pcie_h__
  30 #define __iwl_trans_int_pcie_h__
  31
  32 #include <linux/spinlock.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/skbuff.h>
  35
  36 #include "iwl-fh.h"
  37 #include "iwl-csr.h"
  38 #include "iwl-shared.h"
  39 #include "iwl-trans.h"
  40 #include "iwl-debug.h"
  41 #include "iwl-io.h"
  42
  43 struct iwl_tx_queue;
  44 struct iwl_queue;
  45 struct iwl_host_cmd;
  46
  47 /*This file includes the declaration that are internal to the
  48  * trans_pcie layer */
  49
  50 /**
  51  * struct isr_statistics - interrupt statistics
  52  *
  53  */
  54 struct isr_statistics {
  55         u32 hw;
  56         u32 sw;
  57         u32 err_code;
  58         u32 sch;
  59         u32 alive;
  60         u32 rfkill;
  61         u32 ctkill;
  62         u32 wakeup;
  63         u32 rx;
  64         u32 tx;
  65         u32 unhandled;
  66 };
  67
  68 /**
  69  * struct iwl_rx_queue - Rx queue
  70  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
  71  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
  72  * @pool:
  73  * @queue:
  74  * @read: Shared index to newest available Rx buffer
  75  * @write: Shared index to oldest written Rx packet
  76  * @free_count: Number of pre-allocated buffers in rx_free
  77  * @write_actual:
  78  * @rx_free: list of free SKBs for use
  79  * @rx_used: List of Rx buffers with no SKB
  80  * @need_update: flag to indicate we need to update read/write index
  81  * @rb_stts: driver's pointer to receive buffer status
  82  * @rb_stts_dma: bus address of receive buffer status
  83  * @lock:
  84  *
  85  * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
  86  */
  87 struct iwl_rx_queue {
  88         __le32 *bd;
  89         dma_addr_t bd_dma;
  90         struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
  91         struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
  92         u32 read;
  93         u32 write;
  94         u32 free_count;
  95         u32 write_actual;
  96         struct list_head rx_free;
  97         struct list_head rx_used;
  98         int need_update;
  99         struct iwl_rb_status *rb_stts;
 100         dma_addr_t rb_stts_dma;
 101         spinlock_t lock;
 102 };
 103
 104 struct iwl_dma_ptr {
 105         dma_addr_t dma;
 106         void *addr;
 107         size_t size;
 108 };
 109
 110 /**
 111  * struct iwl_trans_pcie - PCIe transport specific data
 112  * @rxq: all the RX queue data
 113  * @rx_replenish: work that will be called when buffers need to be allocated
 114  * @trans: pointer to the generic transport area
 115  * @scd_base_addr: scheduler sram base address in SRAM
 116  * @scd_bc_tbls: pointer to the byte count table of the scheduler
 117  * @kw: keep warm address
 118  */
 119 struct iwl_trans_pcie {
 120         struct iwl_rx_queue rxq;
 121         struct work_struct rx_replenish;
 122         struct iwl_trans *trans;
 123
 124         /* INT ICT Table */
 125         __le32 *ict_tbl;
 126         void *ict_tbl_vir;
 127         dma_addr_t ict_tbl_dma;
 128         dma_addr_t aligned_ict_tbl_dma;
 129         int ict_index;
 130         u32 inta;
 131         bool use_ict;
 132         struct tasklet_struct irq_tasklet;
 133         struct isr_statistics isr_stats;
 134
 135         u32 inta_mask;
 136         u32 scd_base_addr;
 137         struct iwl_dma_ptr scd_bc_tbls;
 138         struct iwl_dma_ptr kw;
 139 };
 140
 141 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
 142         ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
 143
 144 /*****************************************************
 145 * RX
 146 ******************************************************/
 147 void iwl_bg_rx_replenish(struct work_struct *data);
 148 void iwl_irq_tasklet(struct iwl_trans *trans);
 149 void iwlagn_rx_replenish(struct iwl_trans *trans);
 150 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 151                         struct iwl_rx_queue *q);
 152
 153 /*****************************************************
 154 * ICT
 155 ******************************************************/
 156 int iwl_reset_ict(struct iwl_trans *trans);
 157 void iwl_disable_ict(struct iwl_trans *trans);
 158 int iwl_alloc_isr_ict(struct iwl_trans *trans);
 159 void iwl_free_isr_ict(struct iwl_trans *trans);
 160 irqreturn_t iwl_isr_ict(int irq, void *data);
 161
 162 /*****************************************************
 163 * TX / HCMD
 164 ******************************************************/
 165 void iwl_txq_update_write_ptr(struct iwl_trans *trans,
 166                         struct iwl_tx_queue *txq);
 167 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
 168                                  struct iwl_tx_queue *txq,
 169                                  dma_addr_t addr, u16 len, u8 reset);
 170 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
 171 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
 172 int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id,
 173                         u32 flags, u16 len, const void *data);
 174 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
 175 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 176                                            struct iwl_tx_queue *txq,
 177                                            u16 byte_cnt);
 178 int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
 179                                   u16 ssn_idx, u8 tx_fifo);
 180 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
 181 void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
 182                              struct iwl_tx_queue *txq,
 183                              int tx_fifo_id, int scd_retry);
 184 void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
 185                                                 int frame_limit);
 186 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 187         int index);
 188 void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
 189                           struct sk_buff_head *skbs);
 190
 191 /*****************************************************
 192 * Error handling
 193 ******************************************************/
 194 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 195                             char **buf, bool display);
 196 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
 197 void iwl_dump_csr(struct iwl_trans *trans);
 198
 199 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
 200 {
 201         clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
 202
 203         /* disable interrupts from uCode/NIC to host */
 204         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
 205
 206         /* acknowledge/clear/reset any interrupts still pending
 207          * from uCode or flow handler (Rx/Tx DMA) */
 208         iwl_write32(bus(trans), CSR_INT, 0xffffffff);
 209         iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
 210         IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
 211 }
 212
 213 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
 214 {
 215         struct iwl_trans_pcie *trans_pcie =
 216                 IWL_TRANS_GET_PCIE_TRANS(trans);
 217
 218         IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
 219         set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
 220         iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
 221 }
 222
 223 #endif /* __iwl_trans_int_pcie_h__ */