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drm/radeon: Don't generate new fence for page flip.
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c
blobffce85a9116583ee58f6798b33350bdd99fd6e3a
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
72 {
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99 }
100
101 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
102 {
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107
108 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
109
110 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
111 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
112 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
113 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
114 NI_GRPH_PRESCALE_BYPASS);
115 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
116 NI_OVL_PRESCALE_BYPASS);
117 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
118 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
119 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
120
121 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
122
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
126
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
130
131 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
132 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
133
134 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
135 for (i = 0; i < 256; i++) {
136 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
137 (radeon_crtc->lut_r[i] << 20) |
138 (radeon_crtc->lut_g[i] << 10) |
139 (radeon_crtc->lut_b[i] << 0));
140 }
141
142 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
143 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
147 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
148 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
149 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
150 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
151 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
152 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
153 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
154 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
155 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
156 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
157 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
158
159 }
160
161 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
162 {
163 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
164 struct drm_device *dev = crtc->dev;
165 struct radeon_device *rdev = dev->dev_private;
166 int i;
167 uint32_t dac2_cntl;
168
169 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
170 if (radeon_crtc->crtc_id == 0)
171 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
172 else
173 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
174 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
175
176 WREG8(RADEON_PALETTE_INDEX, 0);
177 for (i = 0; i < 256; i++) {
178 WREG32(RADEON_PALETTE_30_DATA,
179 (radeon_crtc->lut_r[i] << 20) |
180 (radeon_crtc->lut_g[i] << 10) |
181 (radeon_crtc->lut_b[i] << 0));
182 }
183 }
184
185 void radeon_crtc_load_lut(struct drm_crtc *crtc)
186 {
187 struct drm_device *dev = crtc->dev;
188 struct radeon_device *rdev = dev->dev_private;
189
190 if (!crtc->enabled)
191 return;
192
193 if (ASIC_IS_DCE5(rdev))
194 dce5_crtc_load_lut(crtc);
195 else if (ASIC_IS_DCE4(rdev))
196 dce4_crtc_load_lut(crtc);
197 else if (ASIC_IS_AVIVO(rdev))
198 avivo_crtc_load_lut(crtc);
199 else
200 legacy_crtc_load_lut(crtc);
201 }
202
203 /** Sets the color ramps on behalf of fbcon */
204 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
205 u16 blue, int regno)
206 {
207 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
208
209 radeon_crtc->lut_r[regno] = red >> 6;
210 radeon_crtc->lut_g[regno] = green >> 6;
211 radeon_crtc->lut_b[regno] = blue >> 6;
212 }
213
214 /** Gets the color ramps on behalf of fbcon */
215 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
216 u16 *blue, int regno)
217 {
218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
219
220 *red = radeon_crtc->lut_r[regno] << 6;
221 *green = radeon_crtc->lut_g[regno] << 6;
222 *blue = radeon_crtc->lut_b[regno] << 6;
223 }
224
225 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
226 u16 *blue, uint32_t start, uint32_t size)
227 {
228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229 int end = (start + size > 256) ? 256 : start + size, i;
230
231 /* userspace palettes are always correct as is */
232 for (i = start; i < end; i++) {
233 radeon_crtc->lut_r[i] = red[i] >> 6;
234 radeon_crtc->lut_g[i] = green[i] >> 6;
235 radeon_crtc->lut_b[i] = blue[i] >> 6;
236 }
237 radeon_crtc_load_lut(crtc);
238 }
239
240 static void radeon_crtc_destroy(struct drm_crtc *crtc)
241 {
242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
243
244 drm_crtc_cleanup(crtc);
245 kfree(radeon_crtc);
246 }
247
248 /*
249 * Handle unpin events outside the interrupt handler proper.
250 */
251 static void radeon_unpin_work_func(struct work_struct *__work)
252 {
253 struct radeon_unpin_work *work =
254 container_of(__work, struct radeon_unpin_work, work);
255 int r;
256
257 /* unpin of the old buffer */
258 r = radeon_bo_reserve(work->old_rbo, false);
259 if (likely(r == 0)) {
260 r = radeon_bo_unpin(work->old_rbo);
261 if (unlikely(r != 0)) {
262 DRM_ERROR("failed to unpin buffer after flip\n");
263 }
264 radeon_bo_unreserve(work->old_rbo);
265 } else
266 DRM_ERROR("failed to reserve buffer after flip\n");
267
268 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
269 kfree(work);
270 }
271
272 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
273 {
274 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
275 struct radeon_unpin_work *work;
276 struct drm_pending_vblank_event *e;
277 struct timeval now;
278 unsigned long flags;
279 u32 update_pending;
280 int vpos, hpos;
281
282 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
283 work = radeon_crtc->unpin_work;
284 if (work == NULL ||
285 (work->fence && !radeon_fence_signaled(work->fence))) {
286 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
287 return;
288 }
289 /* New pageflip, or just completion of a previous one? */
290 if (!radeon_crtc->deferred_flip_completion) {
291 /* do the flip (mmio) */
292 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
293 } else {
294 /* This is just a completion of a flip queued in crtc
295 * at last invocation. Make sure we go directly to
296 * completion routine.
297 */
298 update_pending = 0;
299 radeon_crtc->deferred_flip_completion = 0;
300 }
301
302 /* Has the pageflip already completed in crtc, or is it certain
303 * to complete in this vblank?
304 */
305 if (update_pending &&
306 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
307 &vpos, &hpos)) &&
308 (vpos >=0) &&
309 (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
310 /* crtc didn't flip in this target vblank interval,
311 * but flip is pending in crtc. It will complete it
312 * in next vblank interval, so complete the flip at
313 * next vblank irq.
314 */
315 radeon_crtc->deferred_flip_completion = 1;
316 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
317 return;
318 }
319
320 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
321 radeon_crtc->unpin_work = NULL;
322
323 /* wakeup userspace */
324 if (work->event) {
325 e = work->event;
326 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
327 e->event.tv_sec = now.tv_sec;
328 e->event.tv_usec = now.tv_usec;
329 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
330 wake_up_interruptible(&e->base.file_priv->event_wait);
331 }
332 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
333
334 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
335 radeon_fence_unref(&work->fence);
336 radeon_post_page_flip(work->rdev, work->crtc_id);
337 schedule_work(&work->work);
338 }
339
340 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
341 struct drm_framebuffer *fb,
342 struct drm_pending_vblank_event *event)
343 {
344 struct drm_device *dev = crtc->dev;
345 struct radeon_device *rdev = dev->dev_private;
346 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
347 struct radeon_framebuffer *old_radeon_fb;
348 struct radeon_framebuffer *new_radeon_fb;
349 struct drm_gem_object *obj;
350 struct radeon_bo *rbo;
351 struct radeon_unpin_work *work;
352 unsigned long flags;
353 u32 tiling_flags, pitch_pixels;
354 u64 base;
355 int r;
356
357 work = kzalloc(sizeof *work, GFP_KERNEL);
358 if (work == NULL)
359 return -ENOMEM;
360
361 work->event = event;
362 work->rdev = rdev;
363 work->crtc_id = radeon_crtc->crtc_id;
364 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
365 new_radeon_fb = to_radeon_framebuffer(fb);
366 /* schedule unpin of the old buffer */
367 obj = old_radeon_fb->obj;
368 /* take a reference to the old object */
369 drm_gem_object_reference(obj);
370 rbo = gem_to_radeon_bo(obj);
371 work->old_rbo = rbo;
372 obj = new_radeon_fb->obj;
373 rbo = gem_to_radeon_bo(obj);
374 if (rbo->tbo.sync_obj)
375 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
376 INIT_WORK(&work->work, radeon_unpin_work_func);
377
378 /* We borrow the event spin lock for protecting unpin_work */
379 spin_lock_irqsave(&dev->event_lock, flags);
380 if (radeon_crtc->unpin_work) {
381 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
382 r = -EBUSY;
383 goto unlock_free;
384 }
385 radeon_crtc->unpin_work = work;
386 radeon_crtc->deferred_flip_completion = 0;
387 spin_unlock_irqrestore(&dev->event_lock, flags);
388
389 /* pin the new buffer */
390 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
391 work->old_rbo, rbo);
392
393 r = radeon_bo_reserve(rbo, false);
394 if (unlikely(r != 0)) {
395 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
396 goto pflip_cleanup;
397 }
398 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
399 if (unlikely(r != 0)) {
400 radeon_bo_unreserve(rbo);
401 r = -EINVAL;
402 DRM_ERROR("failed to pin new rbo buffer before flip\n");
403 goto pflip_cleanup;
404 }
405 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
406 radeon_bo_unreserve(rbo);
407
408 if (!ASIC_IS_AVIVO(rdev)) {
409 /* crtc offset is from display base addr not FB location */
410 base -= radeon_crtc->legacy_display_base_addr;
411 pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
412
413 if (tiling_flags & RADEON_TILING_MACRO) {
414 if (ASIC_IS_R300(rdev)) {
415 base &= ~0x7ff;
416 } else {
417 int byteshift = fb->bits_per_pixel >> 4;
418 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
419 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
420 }
421 } else {
422 int offset = crtc->y * pitch_pixels + crtc->x;
423 switch (fb->bits_per_pixel) {
424 case 8:
425 default:
426 offset *= 1;
427 break;
428 case 15:
429 case 16:
430 offset *= 2;
431 break;
432 case 24:
433 offset *= 3;
434 break;
435 case 32:
436 offset *= 4;
437 break;
438 }
439 base += offset;
440 }
441 base &= ~7;
442 }
443
444 spin_lock_irqsave(&dev->event_lock, flags);
445 work->new_crtc_base = base;
446 spin_unlock_irqrestore(&dev->event_lock, flags);
447
448 /* update crtc fb */
449 crtc->fb = fb;
450
451 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
452 if (r) {
453 DRM_ERROR("failed to get vblank before flip\n");
454 goto pflip_cleanup1;
455 }
456
457 /* set the proper interrupt */
458 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
459
460 return 0;
461
462 pflip_cleanup1:
463 r = radeon_bo_reserve(rbo, false);
464 if (unlikely(r != 0)) {
465 DRM_ERROR("failed to reserve new rbo in error path\n");
466 goto pflip_cleanup;
467 }
468 r = radeon_bo_unpin(rbo);
469 if (unlikely(r != 0)) {
470 radeon_bo_unreserve(rbo);
471 r = -EINVAL;
472 DRM_ERROR("failed to unpin new rbo in error path\n");
473 goto pflip_cleanup;
474 }
475 radeon_bo_unreserve(rbo);
476
477 pflip_cleanup:
478 spin_lock_irqsave(&dev->event_lock, flags);
479 radeon_crtc->unpin_work = NULL;
480 unlock_free:
481 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
482 spin_unlock_irqrestore(&dev->event_lock, flags);
483 radeon_fence_unref(&work->fence);
484 kfree(work);
485
486 return r;
487 }
488
489 static const struct drm_crtc_funcs radeon_crtc_funcs = {
490 .cursor_set = radeon_crtc_cursor_set,
491 .cursor_move = radeon_crtc_cursor_move,
492 .gamma_set = radeon_crtc_gamma_set,
493 .set_config = drm_crtc_helper_set_config,
494 .destroy = radeon_crtc_destroy,
495 .page_flip = radeon_crtc_page_flip,
496 };
497
498 static void radeon_crtc_init(struct drm_device *dev, int index)
499 {
500 struct radeon_device *rdev = dev->dev_private;
501 struct radeon_crtc *radeon_crtc;
502 int i;
503
504 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
505 if (radeon_crtc == NULL)
506 return;
507
508 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
509
510 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
511 radeon_crtc->crtc_id = index;
512 rdev->mode_info.crtcs[index] = radeon_crtc;
513
514 #if 0
515 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
516 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
517 radeon_crtc->mode_set.num_connectors = 0;
518 #endif
519
520 for (i = 0; i < 256; i++) {
521 radeon_crtc->lut_r[i] = i << 2;
522 radeon_crtc->lut_g[i] = i << 2;
523 radeon_crtc->lut_b[i] = i << 2;
524 }
525
526 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
527 radeon_atombios_init_crtc(dev, radeon_crtc);
528 else
529 radeon_legacy_init_crtc(dev, radeon_crtc);
530 }
531
532 static const char *encoder_names[36] = {
533 "NONE",
534 "INTERNAL_LVDS",
535 "INTERNAL_TMDS1",
536 "INTERNAL_TMDS2",
537 "INTERNAL_DAC1",
538 "INTERNAL_DAC2",
539 "INTERNAL_SDVOA",
540 "INTERNAL_SDVOB",
541 "SI170B",
542 "CH7303",
543 "CH7301",
544 "INTERNAL_DVO1",
545 "EXTERNAL_SDVOA",
546 "EXTERNAL_SDVOB",
547 "TITFP513",
548 "INTERNAL_LVTM1",
549 "VT1623",
550 "HDMI_SI1930",
551 "HDMI_INTERNAL",
552 "INTERNAL_KLDSCP_TMDS1",
553 "INTERNAL_KLDSCP_DVO1",
554 "INTERNAL_KLDSCP_DAC1",
555 "INTERNAL_KLDSCP_DAC2",
556 "SI178",
557 "MVPU_FPGA",
558 "INTERNAL_DDI",
559 "VT1625",
560 "HDMI_SI1932",
561 "DP_AN9801",
562 "DP_DP501",
563 "INTERNAL_UNIPHY",
564 "INTERNAL_KLDSCP_LVTMA",
565 "INTERNAL_UNIPHY1",
566 "INTERNAL_UNIPHY2",
567 "NUTMEG",
568 "TRAVIS",
569 };
570
571 static const char *connector_names[15] = {
572 "Unknown",
573 "VGA",
574 "DVI-I",
575 "DVI-D",
576 "DVI-A",
577 "Composite",
578 "S-video",
579 "LVDS",
580 "Component",
581 "DIN",
582 "DisplayPort",
583 "HDMI-A",
584 "HDMI-B",
585 "TV",
586 "eDP",
587 };
588
589 static const char *hpd_names[6] = {
590 "HPD1",
591 "HPD2",
592 "HPD3",
593 "HPD4",
594 "HPD5",
595 "HPD6",
596 };
597
598 static void radeon_print_display_setup(struct drm_device *dev)
599 {
600 struct drm_connector *connector;
601 struct radeon_connector *radeon_connector;
602 struct drm_encoder *encoder;
603 struct radeon_encoder *radeon_encoder;
604 uint32_t devices;
605 int i = 0;
606
607 DRM_INFO("Radeon Display Connectors\n");
608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
609 radeon_connector = to_radeon_connector(connector);
610 DRM_INFO("Connector %d:\n", i);
611 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
612 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
613 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
614 if (radeon_connector->ddc_bus) {
615 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
616 radeon_connector->ddc_bus->rec.mask_clk_reg,
617 radeon_connector->ddc_bus->rec.mask_data_reg,
618 radeon_connector->ddc_bus->rec.a_clk_reg,
619 radeon_connector->ddc_bus->rec.a_data_reg,
620 radeon_connector->ddc_bus->rec.en_clk_reg,
621 radeon_connector->ddc_bus->rec.en_data_reg,
622 radeon_connector->ddc_bus->rec.y_clk_reg,
623 radeon_connector->ddc_bus->rec.y_data_reg);
624 if (radeon_connector->router.ddc_valid)
625 DRM_INFO(" DDC Router 0x%x/0x%x\n",
626 radeon_connector->router.ddc_mux_control_pin,
627 radeon_connector->router.ddc_mux_state);
628 if (radeon_connector->router.cd_valid)
629 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
630 radeon_connector->router.cd_mux_control_pin,
631 radeon_connector->router.cd_mux_state);
632 } else {
633 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
634 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
635 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
636 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
637 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
638 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
639 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
640 }
641 DRM_INFO(" Encoders:\n");
642 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
643 radeon_encoder = to_radeon_encoder(encoder);
644 devices = radeon_encoder->devices & radeon_connector->devices;
645 if (devices) {
646 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
647 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
648 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
649 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
650 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
651 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
652 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
653 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
654 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
655 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
656 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
657 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
658 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
659 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
660 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
661 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
662 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
663 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
664 if (devices & ATOM_DEVICE_TV1_SUPPORT)
665 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
666 if (devices & ATOM_DEVICE_CV_SUPPORT)
667 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
668 }
669 }
670 i++;
671 }
672 }
673
674 static bool radeon_setup_enc_conn(struct drm_device *dev)
675 {
676 struct radeon_device *rdev = dev->dev_private;
677 struct drm_connector *drm_connector;
678 bool ret = false;
679
680 if (rdev->bios) {
681 if (rdev->is_atom_bios) {
682 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
683 if (ret == false)
684 ret = radeon_get_atom_connector_info_from_object_table(dev);
685 } else {
686 ret = radeon_get_legacy_connector_info_from_bios(dev);
687 if (ret == false)
688 ret = radeon_get_legacy_connector_info_from_table(dev);
689 }
690 } else {
691 if (!ASIC_IS_AVIVO(rdev))
692 ret = radeon_get_legacy_connector_info_from_table(dev);
693 }
694 if (ret) {
695 radeon_setup_encoder_clones(dev);
696 radeon_print_display_setup(dev);
697 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
698 radeon_ddc_dump(drm_connector);
699 }
700
701 return ret;
702 }
703
704 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
705 {
706 struct drm_device *dev = radeon_connector->base.dev;
707 struct radeon_device *rdev = dev->dev_private;
708 int ret = 0;
709
710 /* on hw with routers, select right port */
711 if (radeon_connector->router.ddc_valid)
712 radeon_router_select_ddc_port(radeon_connector);
713
714 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
715 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
716 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
717 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
718 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
719 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
720 }
721 if (!radeon_connector->ddc_bus)
722 return -1;
723 if (!radeon_connector->edid) {
724 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
725 }
726
727 if (!radeon_connector->edid) {
728 if (rdev->is_atom_bios) {
729 /* some laptops provide a hardcoded edid in rom for LCDs */
730 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
731 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
732 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
733 } else
734 /* some servers provide a hardcoded edid in rom for KVMs */
735 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
736 }
737 if (radeon_connector->edid) {
738 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
739 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
740 return ret;
741 }
742 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
743 return 0;
744 }
745
746 static int radeon_ddc_dump(struct drm_connector *connector)
747 {
748 struct edid *edid;
749 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
750 int ret = 0;
751
752 /* on hw with routers, select right port */
753 if (radeon_connector->router.ddc_valid)
754 radeon_router_select_ddc_port(radeon_connector);
755
756 if (!radeon_connector->ddc_bus)
757 return -1;
758 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
759 if (edid) {
760 kfree(edid);
761 }
762 return ret;
763 }
764
765 /* avivo */
766 static void avivo_get_fb_div(struct radeon_pll *pll,
767 u32 target_clock,
768 u32 post_div,
769 u32 ref_div,
770 u32 *fb_div,
771 u32 *frac_fb_div)
772 {
773 u32 tmp = post_div * ref_div;
774
775 tmp *= target_clock;
776 *fb_div = tmp / pll->reference_freq;
777 *frac_fb_div = tmp % pll->reference_freq;
778
779 if (*fb_div > pll->max_feedback_div)
780 *fb_div = pll->max_feedback_div;
781 else if (*fb_div < pll->min_feedback_div)
782 *fb_div = pll->min_feedback_div;
783 }
784
785 static u32 avivo_get_post_div(struct radeon_pll *pll,
786 u32 target_clock)
787 {
788 u32 vco, post_div, tmp;
789
790 if (pll->flags & RADEON_PLL_USE_POST_DIV)
791 return pll->post_div;
792
793 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
794 if (pll->flags & RADEON_PLL_IS_LCD)
795 vco = pll->lcd_pll_out_min;
796 else
797 vco = pll->pll_out_min;
798 } else {
799 if (pll->flags & RADEON_PLL_IS_LCD)
800 vco = pll->lcd_pll_out_max;
801 else
802 vco = pll->pll_out_max;
803 }
804
805 post_div = vco / target_clock;
806 tmp = vco % target_clock;
807
808 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
809 if (tmp)
810 post_div++;
811 } else {
812 if (!tmp)
813 post_div--;
814 }
815
816 if (post_div > pll->max_post_div)
817 post_div = pll->max_post_div;
818 else if (post_div < pll->min_post_div)
819 post_div = pll->min_post_div;
820
821 return post_div;
822 }
823
824 #define MAX_TOLERANCE 10
825
826 void radeon_compute_pll_avivo(struct radeon_pll *pll,
827 u32 freq,
828 u32 *dot_clock_p,
829 u32 *fb_div_p,
830 u32 *frac_fb_div_p,
831 u32 *ref_div_p,
832 u32 *post_div_p)
833 {
834 u32 target_clock = freq / 10;
835 u32 post_div = avivo_get_post_div(pll, target_clock);
836 u32 ref_div = pll->min_ref_div;
837 u32 fb_div = 0, frac_fb_div = 0, tmp;
838
839 if (pll->flags & RADEON_PLL_USE_REF_DIV)
840 ref_div = pll->reference_div;
841
842 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
843 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
844 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
845 if (frac_fb_div >= 5) {
846 frac_fb_div -= 5;
847 frac_fb_div = frac_fb_div / 10;
848 frac_fb_div++;
849 }
850 if (frac_fb_div >= 10) {
851 fb_div++;
852 frac_fb_div = 0;
853 }
854 } else {
855 while (ref_div <= pll->max_ref_div) {
856 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
857 &fb_div, &frac_fb_div);
858 if (frac_fb_div >= (pll->reference_freq / 2))
859 fb_div++;
860 frac_fb_div = 0;
861 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
862 tmp = (tmp * 10000) / target_clock;
863
864 if (tmp > (10000 + MAX_TOLERANCE))
865 ref_div++;
866 else if (tmp >= (10000 - MAX_TOLERANCE))
867 break;
868 else
869 ref_div++;
870 }
871 }
872
873 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
874 (ref_div * post_div * 10);
875 *fb_div_p = fb_div;
876 *frac_fb_div_p = frac_fb_div;
877 *ref_div_p = ref_div;
878 *post_div_p = post_div;
879 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
880 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
881 }
882
883 /* pre-avivo */
884 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
885 {
886 uint64_t mod;
887
888 n += d / 2;
889
890 mod = do_div(n, d);
891 return n;
892 }
893
894 void radeon_compute_pll_legacy(struct radeon_pll *pll,
895 uint64_t freq,
896 uint32_t *dot_clock_p,
897 uint32_t *fb_div_p,
898 uint32_t *frac_fb_div_p,
899 uint32_t *ref_div_p,
900 uint32_t *post_div_p)
901 {
902 uint32_t min_ref_div = pll->min_ref_div;
903 uint32_t max_ref_div = pll->max_ref_div;
904 uint32_t min_post_div = pll->min_post_div;
905 uint32_t max_post_div = pll->max_post_div;
906 uint32_t min_fractional_feed_div = 0;
907 uint32_t max_fractional_feed_div = 0;
908 uint32_t best_vco = pll->best_vco;
909 uint32_t best_post_div = 1;
910 uint32_t best_ref_div = 1;
911 uint32_t best_feedback_div = 1;
912 uint32_t best_frac_feedback_div = 0;
913 uint32_t best_freq = -1;
914 uint32_t best_error = 0xffffffff;
915 uint32_t best_vco_diff = 1;
916 uint32_t post_div;
917 u32 pll_out_min, pll_out_max;
918
919 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
920 freq = freq * 1000;
921
922 if (pll->flags & RADEON_PLL_IS_LCD) {
923 pll_out_min = pll->lcd_pll_out_min;
924 pll_out_max = pll->lcd_pll_out_max;
925 } else {
926 pll_out_min = pll->pll_out_min;
927 pll_out_max = pll->pll_out_max;
928 }
929
930 if (pll_out_min > 64800)
931 pll_out_min = 64800;
932
933 if (pll->flags & RADEON_PLL_USE_REF_DIV)
934 min_ref_div = max_ref_div = pll->reference_div;
935 else {
936 while (min_ref_div < max_ref_div-1) {
937 uint32_t mid = (min_ref_div + max_ref_div) / 2;
938 uint32_t pll_in = pll->reference_freq / mid;
939 if (pll_in < pll->pll_in_min)
940 max_ref_div = mid;
941 else if (pll_in > pll->pll_in_max)
942 min_ref_div = mid;
943 else
944 break;
945 }
946 }
947
948 if (pll->flags & RADEON_PLL_USE_POST_DIV)
949 min_post_div = max_post_div = pll->post_div;
950
951 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
952 min_fractional_feed_div = pll->min_frac_feedback_div;
953 max_fractional_feed_div = pll->max_frac_feedback_div;
954 }
955
956 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
957 uint32_t ref_div;
958
959 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
960 continue;
961
962 /* legacy radeons only have a few post_divs */
963 if (pll->flags & RADEON_PLL_LEGACY) {
964 if ((post_div == 5) ||
965 (post_div == 7) ||
966 (post_div == 9) ||
967 (post_div == 10) ||
968 (post_div == 11) ||
969 (post_div == 13) ||
970 (post_div == 14) ||
971 (post_div == 15))
972 continue;
973 }
974
975 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
976 uint32_t feedback_div, current_freq = 0, error, vco_diff;
977 uint32_t pll_in = pll->reference_freq / ref_div;
978 uint32_t min_feed_div = pll->min_feedback_div;
979 uint32_t max_feed_div = pll->max_feedback_div + 1;
980
981 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
982 continue;
983
984 while (min_feed_div < max_feed_div) {
985 uint32_t vco;
986 uint32_t min_frac_feed_div = min_fractional_feed_div;
987 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
988 uint32_t frac_feedback_div;
989 uint64_t tmp;
990
991 feedback_div = (min_feed_div + max_feed_div) / 2;
992
993 tmp = (uint64_t)pll->reference_freq * feedback_div;
994 vco = radeon_div(tmp, ref_div);
995
996 if (vco < pll_out_min) {
997 min_feed_div = feedback_div + 1;
998 continue;
999 } else if (vco > pll_out_max) {
1000 max_feed_div = feedback_div;
1001 continue;
1002 }
1003
1004 while (min_frac_feed_div < max_frac_feed_div) {
1005 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1006 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1007 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1008 current_freq = radeon_div(tmp, ref_div * post_div);
1009
1010 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1011 if (freq < current_freq)
1012 error = 0xffffffff;
1013 else
1014 error = freq - current_freq;
1015 } else
1016 error = abs(current_freq - freq);
1017 vco_diff = abs(vco - best_vco);
1018
1019 if ((best_vco == 0 && error < best_error) ||
1020 (best_vco != 0 &&
1021 ((best_error > 100 && error < best_error - 100) ||
1022 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1023 best_post_div = post_div;
1024 best_ref_div = ref_div;
1025 best_feedback_div = feedback_div;
1026 best_frac_feedback_div = frac_feedback_div;
1027 best_freq = current_freq;
1028 best_error = error;
1029 best_vco_diff = vco_diff;
1030 } else if (current_freq == freq) {
1031 if (best_freq == -1) {
1032 best_post_div = post_div;
1033 best_ref_div = ref_div;
1034 best_feedback_div = feedback_div;
1035 best_frac_feedback_div = frac_feedback_div;
1036 best_freq = current_freq;
1037 best_error = error;
1038 best_vco_diff = vco_diff;
1039 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1040 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1041 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1042 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1043 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1044 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1045 best_post_div = post_div;
1046 best_ref_div = ref_div;
1047 best_feedback_div = feedback_div;
1048 best_frac_feedback_div = frac_feedback_div;
1049 best_freq = current_freq;
1050 best_error = error;
1051 best_vco_diff = vco_diff;
1052 }
1053 }
1054 if (current_freq < freq)
1055 min_frac_feed_div = frac_feedback_div + 1;
1056 else
1057 max_frac_feed_div = frac_feedback_div;
1058 }
1059 if (current_freq < freq)
1060 min_feed_div = feedback_div + 1;
1061 else
1062 max_feed_div = feedback_div;
1063 }
1064 }
1065 }
1066
1067 *dot_clock_p = best_freq / 10000;
1068 *fb_div_p = best_feedback_div;
1069 *frac_fb_div_p = best_frac_feedback_div;
1070 *ref_div_p = best_ref_div;
1071 *post_div_p = best_post_div;
1072 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1073 (long long)freq,
1074 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1075 best_ref_div, best_post_div);
1076
1077 }
1078
1079 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1080 {
1081 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1082
1083 if (radeon_fb->obj) {
1084 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1085 }
1086 drm_framebuffer_cleanup(fb);
1087 kfree(radeon_fb);
1088 }
1089
1090 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1091 struct drm_file *file_priv,
1092 unsigned int *handle)
1093 {
1094 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1095
1096 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1097 }
1098
1099 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1100 .destroy = radeon_user_framebuffer_destroy,
1101 .create_handle = radeon_user_framebuffer_create_handle,
1102 };
1103
1104 void
1105 radeon_framebuffer_init(struct drm_device *dev,
1106 struct radeon_framebuffer *rfb,
1107 struct drm_mode_fb_cmd *mode_cmd,
1108 struct drm_gem_object *obj)
1109 {
1110 rfb->obj = obj;
1111 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1112 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1113 }
1114
1115 static struct drm_framebuffer *
1116 radeon_user_framebuffer_create(struct drm_device *dev,
1117 struct drm_file *file_priv,
1118 struct drm_mode_fb_cmd *mode_cmd)
1119 {
1120 struct drm_gem_object *obj;
1121 struct radeon_framebuffer *radeon_fb;
1122
1123 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
1124 if (obj == NULL) {
1125 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1126 "can't create framebuffer\n", mode_cmd->handle);
1127 return ERR_PTR(-ENOENT);
1128 }
1129
1130 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1131 if (radeon_fb == NULL)
1132 return ERR_PTR(-ENOMEM);
1133
1134 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1135
1136 return &radeon_fb->base;
1137 }
1138
1139 static void radeon_output_poll_changed(struct drm_device *dev)
1140 {
1141 struct radeon_device *rdev = dev->dev_private;
1142 radeon_fb_output_poll_changed(rdev);
1143 }
1144
1145 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1146 .fb_create = radeon_user_framebuffer_create,
1147 .output_poll_changed = radeon_output_poll_changed
1148 };
1149
1150 struct drm_prop_enum_list {
1151 int type;
1152 char *name;
1153 };
1154
1155 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1156 { { 0, "driver" },
1157 { 1, "bios" },
1158 };
1159
1160 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1161 { { TV_STD_NTSC, "ntsc" },
1162 { TV_STD_PAL, "pal" },
1163 { TV_STD_PAL_M, "pal-m" },
1164 { TV_STD_PAL_60, "pal-60" },
1165 { TV_STD_NTSC_J, "ntsc-j" },
1166 { TV_STD_SCART_PAL, "scart-pal" },
1167 { TV_STD_PAL_CN, "pal-cn" },
1168 { TV_STD_SECAM, "secam" },
1169 };
1170
1171 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1172 { { UNDERSCAN_OFF, "off" },
1173 { UNDERSCAN_ON, "on" },
1174 { UNDERSCAN_AUTO, "auto" },
1175 };
1176
1177 static int radeon_modeset_create_props(struct radeon_device *rdev)
1178 {
1179 int i, sz;
1180
1181 if (rdev->is_atom_bios) {
1182 rdev->mode_info.coherent_mode_property =
1183 drm_property_create(rdev->ddev,
1184 DRM_MODE_PROP_RANGE,
1185 "coherent", 2);
1186 if (!rdev->mode_info.coherent_mode_property)
1187 return -ENOMEM;
1188
1189 rdev->mode_info.coherent_mode_property->values[0] = 0;
1190 rdev->mode_info.coherent_mode_property->values[1] = 1;
1191 }
1192
1193 if (!ASIC_IS_AVIVO(rdev)) {
1194 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1195 rdev->mode_info.tmds_pll_property =
1196 drm_property_create(rdev->ddev,
1197 DRM_MODE_PROP_ENUM,
1198 "tmds_pll", sz);
1199 for (i = 0; i < sz; i++) {
1200 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1201 i,
1202 radeon_tmds_pll_enum_list[i].type,
1203 radeon_tmds_pll_enum_list[i].name);
1204 }
1205 }
1206
1207 rdev->mode_info.load_detect_property =
1208 drm_property_create(rdev->ddev,
1209 DRM_MODE_PROP_RANGE,
1210 "load detection", 2);
1211 if (!rdev->mode_info.load_detect_property)
1212 return -ENOMEM;
1213 rdev->mode_info.load_detect_property->values[0] = 0;
1214 rdev->mode_info.load_detect_property->values[1] = 1;
1215
1216 drm_mode_create_scaling_mode_property(rdev->ddev);
1217
1218 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1219 rdev->mode_info.tv_std_property =
1220 drm_property_create(rdev->ddev,
1221 DRM_MODE_PROP_ENUM,
1222 "tv standard", sz);
1223 for (i = 0; i < sz; i++) {
1224 drm_property_add_enum(rdev->mode_info.tv_std_property,
1225 i,
1226 radeon_tv_std_enum_list[i].type,
1227 radeon_tv_std_enum_list[i].name);
1228 }
1229
1230 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1231 rdev->mode_info.underscan_property =
1232 drm_property_create(rdev->ddev,
1233 DRM_MODE_PROP_ENUM,
1234 "underscan", sz);
1235 for (i = 0; i < sz; i++) {
1236 drm_property_add_enum(rdev->mode_info.underscan_property,
1237 i,
1238 radeon_underscan_enum_list[i].type,
1239 radeon_underscan_enum_list[i].name);
1240 }
1241
1242 rdev->mode_info.underscan_hborder_property =
1243 drm_property_create(rdev->ddev,
1244 DRM_MODE_PROP_RANGE,
1245 "underscan hborder", 2);
1246 if (!rdev->mode_info.underscan_hborder_property)
1247 return -ENOMEM;
1248 rdev->mode_info.underscan_hborder_property->values[0] = 0;
1249 rdev->mode_info.underscan_hborder_property->values[1] = 128;
1250
1251 rdev->mode_info.underscan_vborder_property =
1252 drm_property_create(rdev->ddev,
1253 DRM_MODE_PROP_RANGE,
1254 "underscan vborder", 2);
1255 if (!rdev->mode_info.underscan_vborder_property)
1256 return -ENOMEM;
1257 rdev->mode_info.underscan_vborder_property->values[0] = 0;
1258 rdev->mode_info.underscan_vborder_property->values[1] = 128;
1259
1260 return 0;
1261 }
1262
1263 void radeon_update_display_priority(struct radeon_device *rdev)
1264 {
1265 /* adjustment options for the display watermarks */
1266 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1267 /* set display priority to high for r3xx, rv515 chips
1268 * this avoids flickering due to underflow to the
1269 * display controllers during heavy acceleration.
1270 * Don't force high on rs4xx igp chips as it seems to
1271 * affect the sound card. See kernel bug 15982.
1272 */
1273 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1274 !(rdev->flags & RADEON_IS_IGP))
1275 rdev->disp_priority = 2;
1276 else
1277 rdev->disp_priority = 0;
1278 } else
1279 rdev->disp_priority = radeon_disp_priority;
1280
1281 }
1282
1283 int radeon_modeset_init(struct radeon_device *rdev)
1284 {
1285 int i;
1286 int ret;
1287
1288 drm_mode_config_init(rdev->ddev);
1289 rdev->mode_info.mode_config_initialized = true;
1290
1291 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1292
1293 if (ASIC_IS_DCE5(rdev)) {
1294 rdev->ddev->mode_config.max_width = 16384;
1295 rdev->ddev->mode_config.max_height = 16384;
1296 } else if (ASIC_IS_AVIVO(rdev)) {
1297 rdev->ddev->mode_config.max_width = 8192;
1298 rdev->ddev->mode_config.max_height = 8192;
1299 } else {
1300 rdev->ddev->mode_config.max_width = 4096;
1301 rdev->ddev->mode_config.max_height = 4096;
1302 }
1303
1304 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1305
1306 ret = radeon_modeset_create_props(rdev);
1307 if (ret) {
1308 return ret;
1309 }
1310
1311 /* init i2c buses */
1312 radeon_i2c_init(rdev);
1313
1314 /* check combios for a valid hardcoded EDID - Sun servers */
1315 if (!rdev->is_atom_bios) {
1316 /* check for hardcoded EDID in BIOS */
1317 radeon_combios_check_hardcoded_edid(rdev);
1318 }
1319
1320 /* allocate crtcs */
1321 for (i = 0; i < rdev->num_crtc; i++) {
1322 radeon_crtc_init(rdev->ddev, i);
1323 }
1324
1325 /* okay we should have all the bios connectors */
1326 ret = radeon_setup_enc_conn(rdev->ddev);
1327 if (!ret) {
1328 return ret;
1329 }
1330
1331 /* init dig PHYs */
1332 if (rdev->is_atom_bios)
1333 radeon_atom_encoder_init(rdev);
1334
1335 /* initialize hpd */
1336 radeon_hpd_init(rdev);
1337
1338 /* Initialize power management */
1339 radeon_pm_init(rdev);
1340
1341 radeon_fbdev_init(rdev);
1342 drm_kms_helper_poll_init(rdev->ddev);
1343
1344 return 0;
1345 }
1346
1347 void radeon_modeset_fini(struct radeon_device *rdev)
1348 {
1349 radeon_fbdev_fini(rdev);
1350 kfree(rdev->mode_info.bios_hardcoded_edid);
1351 radeon_pm_fini(rdev);
1352
1353 if (rdev->mode_info.mode_config_initialized) {
1354 drm_kms_helper_poll_fini(rdev->ddev);
1355 radeon_hpd_fini(rdev);
1356 drm_mode_config_cleanup(rdev->ddev);
1357 rdev->mode_info.mode_config_initialized = false;
1358 }
1359 /* free i2c buses */
1360 radeon_i2c_fini(rdev);
1361 }
1362
1363 static bool is_hdtv_mode(struct drm_display_mode *mode)
1364 {
1365 /* try and guess if this is a tv or a monitor */
1366 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1367 (mode->vdisplay == 576) || /* 576p */
1368 (mode->vdisplay == 720) || /* 720p */
1369 (mode->vdisplay == 1080)) /* 1080p */
1370 return true;
1371 else
1372 return false;
1373 }
1374
1375 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1376 struct drm_display_mode *mode,
1377 struct drm_display_mode *adjusted_mode)
1378 {
1379 struct drm_device *dev = crtc->dev;
1380 struct radeon_device *rdev = dev->dev_private;
1381 struct drm_encoder *encoder;
1382 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1383 struct radeon_encoder *radeon_encoder;
1384 struct drm_connector *connector;
1385 struct radeon_connector *radeon_connector;
1386 bool first = true;
1387 u32 src_v = 1, dst_v = 1;
1388 u32 src_h = 1, dst_h = 1;
1389
1390 radeon_crtc->h_border = 0;
1391 radeon_crtc->v_border = 0;
1392
1393 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1394 if (encoder->crtc != crtc)
1395 continue;
1396 radeon_encoder = to_radeon_encoder(encoder);
1397 connector = radeon_get_connector_for_encoder(encoder);
1398 radeon_connector = to_radeon_connector(connector);
1399
1400 if (first) {
1401 /* set scaling */
1402 if (radeon_encoder->rmx_type == RMX_OFF)
1403 radeon_crtc->rmx_type = RMX_OFF;
1404 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1405 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1406 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1407 else
1408 radeon_crtc->rmx_type = RMX_OFF;
1409 /* copy native mode */
1410 memcpy(&radeon_crtc->native_mode,
1411 &radeon_encoder->native_mode,
1412 sizeof(struct drm_display_mode));
1413 src_v = crtc->mode.vdisplay;
1414 dst_v = radeon_crtc->native_mode.vdisplay;
1415 src_h = crtc->mode.hdisplay;
1416 dst_h = radeon_crtc->native_mode.hdisplay;
1417
1418 /* fix up for overscan on hdmi */
1419 if (ASIC_IS_AVIVO(rdev) &&
1420 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1421 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1422 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1423 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1424 is_hdtv_mode(mode)))) {
1425 if (radeon_encoder->underscan_hborder != 0)
1426 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1427 else
1428 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1429 if (radeon_encoder->underscan_vborder != 0)
1430 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1431 else
1432 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1433 radeon_crtc->rmx_type = RMX_FULL;
1434 src_v = crtc->mode.vdisplay;
1435 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1436 src_h = crtc->mode.hdisplay;
1437 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1438 }
1439 first = false;
1440 } else {
1441 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1442 /* WARNING: Right now this can't happen but
1443 * in the future we need to check that scaling
1444 * are consistent across different encoder
1445 * (ie all encoder can work with the same
1446 * scaling).
1447 */
1448 DRM_ERROR("Scaling not consistent across encoder.\n");
1449 return false;
1450 }
1451 }
1452 }
1453 if (radeon_crtc->rmx_type != RMX_OFF) {
1454 fixed20_12 a, b;
1455 a.full = dfixed_const(src_v);
1456 b.full = dfixed_const(dst_v);
1457 radeon_crtc->vsc.full = dfixed_div(a, b);
1458 a.full = dfixed_const(src_h);
1459 b.full = dfixed_const(dst_h);
1460 radeon_crtc->hsc.full = dfixed_div(a, b);
1461 } else {
1462 radeon_crtc->vsc.full = dfixed_const(1);
1463 radeon_crtc->hsc.full = dfixed_const(1);
1464 }
1465 return true;
1466 }
1467
1468 /*
1469 * Retrieve current video scanout position of crtc on a given gpu.
1470 *
1471 * \param dev Device to query.
1472 * \param crtc Crtc to query.
1473 * \param *vpos Location where vertical scanout position should be stored.
1474 * \param *hpos Location where horizontal scanout position should go.
1475 *
1476 * Returns vpos as a positive number while in active scanout area.
1477 * Returns vpos as a negative number inside vblank, counting the number
1478 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1479 * until start of active scanout / end of vblank."
1480 *
1481 * \return Flags, or'ed together as follows:
1482 *
1483 * DRM_SCANOUTPOS_VALID = Query successful.
1484 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1485 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1486 * this flag means that returned position may be offset by a constant but
1487 * unknown small number of scanlines wrt. real scanout position.
1488 *
1489 */
1490 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1491 {
1492 u32 stat_crtc = 0, vbl = 0, position = 0;
1493 int vbl_start, vbl_end, vtotal, ret = 0;
1494 bool in_vbl = true;
1495
1496 struct radeon_device *rdev = dev->dev_private;
1497
1498 if (ASIC_IS_DCE4(rdev)) {
1499 if (crtc == 0) {
1500 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1501 EVERGREEN_CRTC0_REGISTER_OFFSET);
1502 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1503 EVERGREEN_CRTC0_REGISTER_OFFSET);
1504 ret |= DRM_SCANOUTPOS_VALID;
1505 }
1506 if (crtc == 1) {
1507 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1508 EVERGREEN_CRTC1_REGISTER_OFFSET);
1509 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1510 EVERGREEN_CRTC1_REGISTER_OFFSET);
1511 ret |= DRM_SCANOUTPOS_VALID;
1512 }
1513 if (crtc == 2) {
1514 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1515 EVERGREEN_CRTC2_REGISTER_OFFSET);
1516 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1517 EVERGREEN_CRTC2_REGISTER_OFFSET);
1518 ret |= DRM_SCANOUTPOS_VALID;
1519 }
1520 if (crtc == 3) {
1521 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1522 EVERGREEN_CRTC3_REGISTER_OFFSET);
1523 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1524 EVERGREEN_CRTC3_REGISTER_OFFSET);
1525 ret |= DRM_SCANOUTPOS_VALID;
1526 }
1527 if (crtc == 4) {
1528 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1529 EVERGREEN_CRTC4_REGISTER_OFFSET);
1530 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1531 EVERGREEN_CRTC4_REGISTER_OFFSET);
1532 ret |= DRM_SCANOUTPOS_VALID;
1533 }
1534 if (crtc == 5) {
1535 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1536 EVERGREEN_CRTC5_REGISTER_OFFSET);
1537 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1538 EVERGREEN_CRTC5_REGISTER_OFFSET);
1539 ret |= DRM_SCANOUTPOS_VALID;
1540 }
1541 } else if (ASIC_IS_AVIVO(rdev)) {
1542 if (crtc == 0) {
1543 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1544 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1545 ret |= DRM_SCANOUTPOS_VALID;
1546 }
1547 if (crtc == 1) {
1548 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1549 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1550 ret |= DRM_SCANOUTPOS_VALID;
1551 }
1552 } else {
1553 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1554 if (crtc == 0) {
1555 /* Assume vbl_end == 0, get vbl_start from
1556 * upper 16 bits.
1557 */
1558 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1559 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1560 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1561 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1562 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1563 if (!(stat_crtc & 1))
1564 in_vbl = false;
1565
1566 ret |= DRM_SCANOUTPOS_VALID;
1567 }
1568 if (crtc == 1) {
1569 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1570 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1571 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1572 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1573 if (!(stat_crtc & 1))
1574 in_vbl = false;
1575
1576 ret |= DRM_SCANOUTPOS_VALID;
1577 }
1578 }
1579
1580 /* Decode into vertical and horizontal scanout position. */
1581 *vpos = position & 0x1fff;
1582 *hpos = (position >> 16) & 0x1fff;
1583
1584 /* Valid vblank area boundaries from gpu retrieved? */
1585 if (vbl > 0) {
1586 /* Yes: Decode. */
1587 ret |= DRM_SCANOUTPOS_ACCURATE;
1588 vbl_start = vbl & 0x1fff;
1589 vbl_end = (vbl >> 16) & 0x1fff;
1590 }
1591 else {
1592 /* No: Fake something reasonable which gives at least ok results. */
1593 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1594 vbl_end = 0;
1595 }
1596
1597 /* Test scanout position against vblank region. */
1598 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1599 in_vbl = false;
1600
1601 /* Check if inside vblank area and apply corrective offsets:
1602 * vpos will then be >=0 in video scanout area, but negative
1603 * within vblank area, counting down the number of lines until
1604 * start of scanout.
1605 */
1606
1607 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1608 if (in_vbl && (*vpos >= vbl_start)) {
1609 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1610 *vpos = *vpos - vtotal;
1611 }
1612
1613 /* Correct for shifted end of vbl at vbl_end. */
1614 *vpos = *vpos - vbl_end;
1615
1616 /* In vblank? */
1617 if (in_vbl)
1618 ret |= DRM_SCANOUTPOS_INVBL;
1619
1620 return ret;
1621 }
Linus' kernel tree