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[CPUFREQ] Fix cast warning in pcc driver.
[linux-2.6.git] / drivers / mtd / chips / jedec_probe.c
blob1bec5e1ce6acd00153c084e5bed8c12c4b65161e
1 /*
2 Common Flash Interface probe code.
3 (C) 2000 Red Hat. GPL'd.
4 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5)
5 for the standard this probe goes back to.
6
7 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
8 */
9
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <asm/io.h>
15 #include <asm/byteorder.h>
16 #include <linux/errno.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/map.h>
22 #include <linux/mtd/cfi.h>
23 #include <linux/mtd/gen_probe.h>
24
25 /* Manufacturers */
26 #define MANUFACTURER_AMD 0x0001
27 #define MANUFACTURER_ATMEL 0x001f
28 #define MANUFACTURER_EON 0x001c
29 #define MANUFACTURER_FUJITSU 0x0004
30 #define MANUFACTURER_HYUNDAI 0x00AD
31 #define MANUFACTURER_INTEL 0x0089
32 #define MANUFACTURER_MACRONIX 0x00C2
33 #define MANUFACTURER_NEC 0x0010
34 #define MANUFACTURER_PMC 0x009D
35 #define MANUFACTURER_SHARP 0x00b0
36 #define MANUFACTURER_SST 0x00BF
37 #define MANUFACTURER_ST 0x0020
38 #define MANUFACTURER_TOSHIBA 0x0098
39 #define MANUFACTURER_WINBOND 0x00da
40 #define CONTINUATION_CODE 0x007f
41
42
43 /* AMD */
44 #define AM29DL800BB 0x22CB
45 #define AM29DL800BT 0x224A
46
47 #define AM29F800BB 0x2258
48 #define AM29F800BT 0x22D6
49 #define AM29LV400BB 0x22BA
50 #define AM29LV400BT 0x22B9
51 #define AM29LV800BB 0x225B
52 #define AM29LV800BT 0x22DA
53 #define AM29LV160DT 0x22C4
54 #define AM29LV160DB 0x2249
55 #define AM29F017D 0x003D
56 #define AM29F016D 0x00AD
57 #define AM29F080 0x00D5
58 #define AM29F040 0x00A4
59 #define AM29LV040B 0x004F
60 #define AM29F032B 0x0041
61 #define AM29F002T 0x00B0
62 #define AM29SL800DB 0x226B
63 #define AM29SL800DT 0x22EA
64
65 /* Atmel */
66 #define AT49BV512 0x0003
67 #define AT29LV512 0x003d
68 #define AT49BV16X 0x00C0
69 #define AT49BV16XT 0x00C2
70 #define AT49BV32X 0x00C8
71 #define AT49BV32XT 0x00C9
72
73 /* Eon */
74 #define EN29SL800BB 0x226B
75 #define EN29SL800BT 0x22EA
76
77 /* Fujitsu */
78 #define MBM29F040C 0x00A4
79 #define MBM29F800BA 0x2258
80 #define MBM29LV650UE 0x22D7
81 #define MBM29LV320TE 0x22F6
82 #define MBM29LV320BE 0x22F9
83 #define MBM29LV160TE 0x22C4
84 #define MBM29LV160BE 0x2249
85 #define MBM29LV800BA 0x225B
86 #define MBM29LV800TA 0x22DA
87 #define MBM29LV400TC 0x22B9
88 #define MBM29LV400BC 0x22BA
89
90 /* Hyundai */
91 #define HY29F002T 0x00B0
92
93 /* Intel */
94 #define I28F004B3T 0x00d4
95 #define I28F004B3B 0x00d5
96 #define I28F400B3T 0x8894
97 #define I28F400B3B 0x8895
98 #define I28F008S5 0x00a6
99 #define I28F016S5 0x00a0
100 #define I28F008SA 0x00a2
101 #define I28F008B3T 0x00d2
102 #define I28F008B3B 0x00d3
103 #define I28F800B3T 0x8892
104 #define I28F800B3B 0x8893
105 #define I28F016S3 0x00aa
106 #define I28F016B3T 0x00d0
107 #define I28F016B3B 0x00d1
108 #define I28F160B3T 0x8890
109 #define I28F160B3B 0x8891
110 #define I28F320B3T 0x8896
111 #define I28F320B3B 0x8897
112 #define I28F640B3T 0x8898
113 #define I28F640B3B 0x8899
114 #define I28F640C3B 0x88CD
115 #define I28F160F3T 0x88F3
116 #define I28F160F3B 0x88F4
117 #define I28F160C3T 0x88C2
118 #define I28F160C3B 0x88C3
119 #define I82802AB 0x00ad
120 #define I82802AC 0x00ac
121
122 /* Macronix */
123 #define MX29LV040C 0x004F
124 #define MX29LV160T 0x22C4
125 #define MX29LV160B 0x2249
126 #define MX29F040 0x00A4
127 #define MX29F016 0x00AD
128 #define MX29F002T 0x00B0
129 #define MX29F004T 0x0045
130 #define MX29F004B 0x0046
131
132 /* NEC */
133 #define UPD29F064115 0x221C
134
135 /* PMC */
136 #define PM49FL002 0x006D
137 #define PM49FL004 0x006E
138 #define PM49FL008 0x006A
139
140 /* Sharp */
141 #define LH28F640BF 0x00b0
142
143 /* ST - www.st.com */
144 #define M29F800AB 0x0058
145 #define M29W800DT 0x22D7
146 #define M29W800DB 0x225B
147 #define M29W400DT 0x00EE
148 #define M29W400DB 0x00EF
149 #define M29W160DT 0x22C4
150 #define M29W160DB 0x2249
151 #define M29W040B 0x00E3
152 #define M50FW040 0x002C
153 #define M50FW080 0x002D
154 #define M50FW016 0x002E
155 #define M50LPW080 0x002F
156 #define M50FLW080A 0x0080
157 #define M50FLW080B 0x0081
158 #define PSD4256G6V 0x00e9
159
160 /* SST */
161 #define SST29EE020 0x0010
162 #define SST29LE020 0x0012
163 #define SST29EE512 0x005d
164 #define SST29LE512 0x003d
165 #define SST39LF800 0x2781
166 #define SST39LF160 0x2782
167 #define SST39VF1601 0x234b
168 #define SST39VF3201 0x235b
169 #define SST39LF512 0x00D4
170 #define SST39LF010 0x00D5
171 #define SST39LF020 0x00D6
172 #define SST39LF040 0x00D7
173 #define SST39SF010A 0x00B5
174 #define SST39SF020A 0x00B6
175 #define SST39SF040 0x00B7
176 #define SST49LF004B 0x0060
177 #define SST49LF040B 0x0050
178 #define SST49LF008A 0x005a
179 #define SST49LF030A 0x001C
180 #define SST49LF040A 0x0051
181 #define SST49LF080A 0x005B
182 #define SST36VF3203 0x7354
183
184 /* Toshiba */
185 #define TC58FVT160 0x00C2
186 #define TC58FVB160 0x0043
187 #define TC58FVT321 0x009A
188 #define TC58FVB321 0x009C
189 #define TC58FVT641 0x0093
190 #define TC58FVB641 0x0095
191
192 /* Winbond */
193 #define W49V002A 0x00b0
194
195
196 /*
197 * Unlock address sets for AMD command sets.
198 * Intel command sets use the MTD_UADDR_UNNECESSARY.
199 * Each identifier, except MTD_UADDR_UNNECESSARY, and
200 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
201 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
202 * initialization need not require initializing all of the
203 * unlock addresses for all bit widths.
204 */
205 enum uaddr {
206 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
207 MTD_UADDR_0x0555_0x02AA,
208 MTD_UADDR_0x0555_0x0AAA,
209 MTD_UADDR_0x5555_0x2AAA,
210 MTD_UADDR_0x0AAA_0x0554,
211 MTD_UADDR_0x0AAA_0x0555,
212 MTD_UADDR_0xAAAA_0x5555,
213 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
214 MTD_UADDR_UNNECESSARY, /* Does not require any address */
215 };
216
217
218 struct unlock_addr {
219 uint32_t addr1;
220 uint32_t addr2;
221 };
222
223
224 /*
225 * I don't like the fact that the first entry in unlock_addrs[]
226 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
227 * should not be used. The problem is that structures with
228 * initializers have extra fields initialized to 0. It is _very_
229 * desireable to have the unlock address entries for unsupported
230 * data widths automatically initialized - that means that
231 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
232 * must go unused.
233 */
234 static const struct unlock_addr unlock_addrs[] = {
235 [MTD_UADDR_NOT_SUPPORTED] = {
236 .addr1 = 0xffff,
237 .addr2 = 0xffff
238 },
239
240 [MTD_UADDR_0x0555_0x02AA] = {
241 .addr1 = 0x0555,
242 .addr2 = 0x02aa
243 },
244
245 [MTD_UADDR_0x0555_0x0AAA] = {
246 .addr1 = 0x0555,
247 .addr2 = 0x0aaa
248 },
249
250 [MTD_UADDR_0x5555_0x2AAA] = {
251 .addr1 = 0x5555,
252 .addr2 = 0x2aaa
253 },
254
255 [MTD_UADDR_0x0AAA_0x0554] = {
256 .addr1 = 0x0AAA,
257 .addr2 = 0x0554
258 },
259
260 [MTD_UADDR_0x0AAA_0x0555] = {
261 .addr1 = 0x0AAA,
262 .addr2 = 0x0555
263 },
264
265 [MTD_UADDR_0xAAAA_0x5555] = {
266 .addr1 = 0xaaaa,
267 .addr2 = 0x5555
268 },
269
270 [MTD_UADDR_DONT_CARE] = {
271 .addr1 = 0x0000, /* Doesn't matter which address */
272 .addr2 = 0x0000 /* is used - must be last entry */
273 },
274
275 [MTD_UADDR_UNNECESSARY] = {
276 .addr1 = 0x0000,
277 .addr2 = 0x0000
278 }
279 };
280
281 struct amd_flash_info {
282 const char *name;
283 const uint16_t mfr_id;
284 const uint16_t dev_id;
285 const uint8_t dev_size;
286 const uint8_t nr_regions;
287 const uint16_t cmd_set;
288 const uint32_t regions[6];
289 const uint8_t devtypes; /* Bitmask for x8, x16 etc. */
290 const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */
291 };
292
293 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
294
295 #define SIZE_64KiB 16
296 #define SIZE_128KiB 17
297 #define SIZE_256KiB 18
298 #define SIZE_512KiB 19
299 #define SIZE_1MiB 20
300 #define SIZE_2MiB 21
301 #define SIZE_4MiB 22
302 #define SIZE_8MiB 23
303
304
305 /*
306 * Please keep this list ordered by manufacturer!
307 * Fortunately, the list isn't searched often and so a
308 * slow, linear search isn't so bad.
309 */
310 static const struct amd_flash_info jedec_table[] = {
311 {
312 .mfr_id = MANUFACTURER_AMD,
313 .dev_id = AM29F032B,
314 .name = "AMD AM29F032B",
315 .uaddr = MTD_UADDR_0x0555_0x02AA,
316 .devtypes = CFI_DEVICETYPE_X8,
317 .dev_size = SIZE_4MiB,
318 .cmd_set = P_ID_AMD_STD,
319 .nr_regions = 1,
320 .regions = {
321 ERASEINFO(0x10000,64)
322 }
323 }, {
324 .mfr_id = MANUFACTURER_AMD,
325 .dev_id = AM29LV160DT,
326 .name = "AMD AM29LV160DT",
327 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
328 .uaddr = MTD_UADDR_0x0AAA_0x0555,
329 .dev_size = SIZE_2MiB,
330 .cmd_set = P_ID_AMD_STD,
331 .nr_regions = 4,
332 .regions = {
333 ERASEINFO(0x10000,31),
334 ERASEINFO(0x08000,1),
335 ERASEINFO(0x02000,2),
336 ERASEINFO(0x04000,1)
337 }
338 }, {
339 .mfr_id = MANUFACTURER_AMD,
340 .dev_id = AM29LV160DB,
341 .name = "AMD AM29LV160DB",
342 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
343 .uaddr = MTD_UADDR_0x0AAA_0x0555,
344 .dev_size = SIZE_2MiB,
345 .cmd_set = P_ID_AMD_STD,
346 .nr_regions = 4,
347 .regions = {
348 ERASEINFO(0x04000,1),
349 ERASEINFO(0x02000,2),
350 ERASEINFO(0x08000,1),
351 ERASEINFO(0x10000,31)
352 }
353 }, {
354 .mfr_id = MANUFACTURER_AMD,
355 .dev_id = AM29LV400BB,
356 .name = "AMD AM29LV400BB",
357 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
358 .uaddr = MTD_UADDR_0x0AAA_0x0555,
359 .dev_size = SIZE_512KiB,
360 .cmd_set = P_ID_AMD_STD,
361 .nr_regions = 4,
362 .regions = {
363 ERASEINFO(0x04000,1),
364 ERASEINFO(0x02000,2),
365 ERASEINFO(0x08000,1),
366 ERASEINFO(0x10000,7)
367 }
368 }, {
369 .mfr_id = MANUFACTURER_AMD,
370 .dev_id = AM29LV400BT,
371 .name = "AMD AM29LV400BT",
372 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
373 .uaddr = MTD_UADDR_0x0AAA_0x0555,
374 .dev_size = SIZE_512KiB,
375 .cmd_set = P_ID_AMD_STD,
376 .nr_regions = 4,
377 .regions = {
378 ERASEINFO(0x10000,7),
379 ERASEINFO(0x08000,1),
380 ERASEINFO(0x02000,2),
381 ERASEINFO(0x04000,1)
382 }
383 }, {
384 .mfr_id = MANUFACTURER_AMD,
385 .dev_id = AM29LV800BB,
386 .name = "AMD AM29LV800BB",
387 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
388 .uaddr = MTD_UADDR_0x0AAA_0x0555,
389 .dev_size = SIZE_1MiB,
390 .cmd_set = P_ID_AMD_STD,
391 .nr_regions = 4,
392 .regions = {
393 ERASEINFO(0x04000,1),
394 ERASEINFO(0x02000,2),
395 ERASEINFO(0x08000,1),
396 ERASEINFO(0x10000,15),
397 }
398 }, {
399 /* add DL */
400 .mfr_id = MANUFACTURER_AMD,
401 .dev_id = AM29DL800BB,
402 .name = "AMD AM29DL800BB",
403 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
404 .uaddr = MTD_UADDR_0x0AAA_0x0555,
405 .dev_size = SIZE_1MiB,
406 .cmd_set = P_ID_AMD_STD,
407 .nr_regions = 6,
408 .regions = {
409 ERASEINFO(0x04000,1),
410 ERASEINFO(0x08000,1),
411 ERASEINFO(0x02000,4),
412 ERASEINFO(0x08000,1),
413 ERASEINFO(0x04000,1),
414 ERASEINFO(0x10000,14)
415 }
416 }, {
417 .mfr_id = MANUFACTURER_AMD,
418 .dev_id = AM29DL800BT,
419 .name = "AMD AM29DL800BT",
420 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
421 .uaddr = MTD_UADDR_0x0AAA_0x0555,
422 .dev_size = SIZE_1MiB,
423 .cmd_set = P_ID_AMD_STD,
424 .nr_regions = 6,
425 .regions = {
426 ERASEINFO(0x10000,14),
427 ERASEINFO(0x04000,1),
428 ERASEINFO(0x08000,1),
429 ERASEINFO(0x02000,4),
430 ERASEINFO(0x08000,1),
431 ERASEINFO(0x04000,1)
432 }
433 }, {
434 .mfr_id = MANUFACTURER_AMD,
435 .dev_id = AM29F800BB,
436 .name = "AMD AM29F800BB",
437 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
438 .uaddr = MTD_UADDR_0x0AAA_0x0555,
439 .dev_size = SIZE_1MiB,
440 .cmd_set = P_ID_AMD_STD,
441 .nr_regions = 4,
442 .regions = {
443 ERASEINFO(0x04000,1),
444 ERASEINFO(0x02000,2),
445 ERASEINFO(0x08000,1),
446 ERASEINFO(0x10000,15),
447 }
448 }, {
449 .mfr_id = MANUFACTURER_AMD,
450 .dev_id = AM29LV800BT,
451 .name = "AMD AM29LV800BT",
452 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
453 .uaddr = MTD_UADDR_0x0AAA_0x0555,
454 .dev_size = SIZE_1MiB,
455 .cmd_set = P_ID_AMD_STD,
456 .nr_regions = 4,
457 .regions = {
458 ERASEINFO(0x10000,15),
459 ERASEINFO(0x08000,1),
460 ERASEINFO(0x02000,2),
461 ERASEINFO(0x04000,1)
462 }
463 }, {
464 .mfr_id = MANUFACTURER_AMD,
465 .dev_id = AM29F800BT,
466 .name = "AMD AM29F800BT",
467 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
468 .uaddr = MTD_UADDR_0x0AAA_0x0555,
469 .dev_size = SIZE_1MiB,
470 .cmd_set = P_ID_AMD_STD,
471 .nr_regions = 4,
472 .regions = {
473 ERASEINFO(0x10000,15),
474 ERASEINFO(0x08000,1),
475 ERASEINFO(0x02000,2),
476 ERASEINFO(0x04000,1)
477 }
478 }, {
479 .mfr_id = MANUFACTURER_AMD,
480 .dev_id = AM29F017D,
481 .name = "AMD AM29F017D",
482 .devtypes = CFI_DEVICETYPE_X8,
483 .uaddr = MTD_UADDR_DONT_CARE,
484 .dev_size = SIZE_2MiB,
485 .cmd_set = P_ID_AMD_STD,
486 .nr_regions = 1,
487 .regions = {
488 ERASEINFO(0x10000,32),
489 }
490 }, {
491 .mfr_id = MANUFACTURER_AMD,
492 .dev_id = AM29F016D,
493 .name = "AMD AM29F016D",
494 .devtypes = CFI_DEVICETYPE_X8,
495 .uaddr = MTD_UADDR_0x0555_0x02AA,
496 .dev_size = SIZE_2MiB,
497 .cmd_set = P_ID_AMD_STD,
498 .nr_regions = 1,
499 .regions = {
500 ERASEINFO(0x10000,32),
501 }
502 }, {
503 .mfr_id = MANUFACTURER_AMD,
504 .dev_id = AM29F080,
505 .name = "AMD AM29F080",
506 .devtypes = CFI_DEVICETYPE_X8,
507 .uaddr = MTD_UADDR_0x0555_0x02AA,
508 .dev_size = SIZE_1MiB,
509 .cmd_set = P_ID_AMD_STD,
510 .nr_regions = 1,
511 .regions = {
512 ERASEINFO(0x10000,16),
513 }
514 }, {
515 .mfr_id = MANUFACTURER_AMD,
516 .dev_id = AM29F040,
517 .name = "AMD AM29F040",
518 .devtypes = CFI_DEVICETYPE_X8,
519 .uaddr = MTD_UADDR_0x0555_0x02AA,
520 .dev_size = SIZE_512KiB,
521 .cmd_set = P_ID_AMD_STD,
522 .nr_regions = 1,
523 .regions = {
524 ERASEINFO(0x10000,8),
525 }
526 }, {
527 .mfr_id = MANUFACTURER_AMD,
528 .dev_id = AM29LV040B,
529 .name = "AMD AM29LV040B",
530 .devtypes = CFI_DEVICETYPE_X8,
531 .uaddr = MTD_UADDR_0x0555_0x02AA,
532 .dev_size = SIZE_512KiB,
533 .cmd_set = P_ID_AMD_STD,
534 .nr_regions = 1,
535 .regions = {
536 ERASEINFO(0x10000,8),
537 }
538 }, {
539 .mfr_id = MANUFACTURER_AMD,
540 .dev_id = AM29F002T,
541 .name = "AMD AM29F002T",
542 .devtypes = CFI_DEVICETYPE_X8,
543 .uaddr = MTD_UADDR_0x0555_0x02AA,
544 .dev_size = SIZE_256KiB,
545 .cmd_set = P_ID_AMD_STD,
546 .nr_regions = 4,
547 .regions = {
548 ERASEINFO(0x10000,3),
549 ERASEINFO(0x08000,1),
550 ERASEINFO(0x02000,2),
551 ERASEINFO(0x04000,1),
552 }
553 }, {
554 .mfr_id = MANUFACTURER_AMD,
555 .dev_id = AM29SL800DT,
556 .name = "AMD AM29SL800DT",
557 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
558 .uaddr = MTD_UADDR_0x0AAA_0x0555,
559 .dev_size = SIZE_1MiB,
560 .cmd_set = P_ID_AMD_STD,
561 .nr_regions = 4,
562 .regions = {
563 ERASEINFO(0x10000,15),
564 ERASEINFO(0x08000,1),
565 ERASEINFO(0x02000,2),
566 ERASEINFO(0x04000,1),
567 }
568 }, {
569 .mfr_id = MANUFACTURER_AMD,
570 .dev_id = AM29SL800DB,
571 .name = "AMD AM29SL800DB",
572 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
573 .uaddr = MTD_UADDR_0x0AAA_0x0555,
574 .dev_size = SIZE_1MiB,
575 .cmd_set = P_ID_AMD_STD,
576 .nr_regions = 4,
577 .regions = {
578 ERASEINFO(0x04000,1),
579 ERASEINFO(0x02000,2),
580 ERASEINFO(0x08000,1),
581 ERASEINFO(0x10000,15),
582 }
583 }, {
584 .mfr_id = MANUFACTURER_ATMEL,
585 .dev_id = AT49BV512,
586 .name = "Atmel AT49BV512",
587 .devtypes = CFI_DEVICETYPE_X8,
588 .uaddr = MTD_UADDR_0x5555_0x2AAA,
589 .dev_size = SIZE_64KiB,
590 .cmd_set = P_ID_AMD_STD,
591 .nr_regions = 1,
592 .regions = {
593 ERASEINFO(0x10000,1)
594 }
595 }, {
596 .mfr_id = MANUFACTURER_ATMEL,
597 .dev_id = AT29LV512,
598 .name = "Atmel AT29LV512",
599 .devtypes = CFI_DEVICETYPE_X8,
600 .uaddr = MTD_UADDR_0x5555_0x2AAA,
601 .dev_size = SIZE_64KiB,
602 .cmd_set = P_ID_AMD_STD,
603 .nr_regions = 1,
604 .regions = {
605 ERASEINFO(0x80,256),
606 ERASEINFO(0x80,256)
607 }
608 }, {
609 .mfr_id = MANUFACTURER_ATMEL,
610 .dev_id = AT49BV16X,
611 .name = "Atmel AT49BV16X",
612 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
613 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
614 .dev_size = SIZE_2MiB,
615 .cmd_set = P_ID_AMD_STD,
616 .nr_regions = 2,
617 .regions = {
618 ERASEINFO(0x02000,8),
619 ERASEINFO(0x10000,31)
620 }
621 }, {
622 .mfr_id = MANUFACTURER_ATMEL,
623 .dev_id = AT49BV16XT,
624 .name = "Atmel AT49BV16XT",
625 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
626 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
627 .dev_size = SIZE_2MiB,
628 .cmd_set = P_ID_AMD_STD,
629 .nr_regions = 2,
630 .regions = {
631 ERASEINFO(0x10000,31),
632 ERASEINFO(0x02000,8)
633 }
634 }, {
635 .mfr_id = MANUFACTURER_ATMEL,
636 .dev_id = AT49BV32X,
637 .name = "Atmel AT49BV32X",
638 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
639 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
640 .dev_size = SIZE_4MiB,
641 .cmd_set = P_ID_AMD_STD,
642 .nr_regions = 2,
643 .regions = {
644 ERASEINFO(0x02000,8),
645 ERASEINFO(0x10000,63)
646 }
647 }, {
648 .mfr_id = MANUFACTURER_ATMEL,
649 .dev_id = AT49BV32XT,
650 .name = "Atmel AT49BV32XT",
651 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
652 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
653 .dev_size = SIZE_4MiB,
654 .cmd_set = P_ID_AMD_STD,
655 .nr_regions = 2,
656 .regions = {
657 ERASEINFO(0x10000,63),
658 ERASEINFO(0x02000,8)
659 }
660 }, {
661 .mfr_id = MANUFACTURER_EON,
662 .dev_id = EN29SL800BT,
663 .name = "Eon EN29SL800BT",
664 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
665 .uaddr = MTD_UADDR_0x0AAA_0x0555,
666 .dev_size = SIZE_1MiB,
667 .cmd_set = P_ID_AMD_STD,
668 .nr_regions = 4,
669 .regions = {
670 ERASEINFO(0x10000,15),
671 ERASEINFO(0x08000,1),
672 ERASEINFO(0x02000,2),
673 ERASEINFO(0x04000,1),
674 }
675 }, {
676 .mfr_id = MANUFACTURER_EON,
677 .dev_id = EN29SL800BB,
678 .name = "Eon EN29SL800BB",
679 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
680 .uaddr = MTD_UADDR_0x0AAA_0x0555,
681 .dev_size = SIZE_1MiB,
682 .cmd_set = P_ID_AMD_STD,
683 .nr_regions = 4,
684 .regions = {
685 ERASEINFO(0x04000,1),
686 ERASEINFO(0x02000,2),
687 ERASEINFO(0x08000,1),
688 ERASEINFO(0x10000,15),
689 }
690 }, {
691 .mfr_id = MANUFACTURER_FUJITSU,
692 .dev_id = MBM29F040C,
693 .name = "Fujitsu MBM29F040C",
694 .devtypes = CFI_DEVICETYPE_X8,
695 .uaddr = MTD_UADDR_0x0AAA_0x0555,
696 .dev_size = SIZE_512KiB,
697 .cmd_set = P_ID_AMD_STD,
698 .nr_regions = 1,
699 .regions = {
700 ERASEINFO(0x10000,8)
701 }
702 }, {
703 .mfr_id = MANUFACTURER_FUJITSU,
704 .dev_id = MBM29F800BA,
705 .name = "Fujitsu MBM29F800BA",
706 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
707 .uaddr = MTD_UADDR_0x0AAA_0x0555,
708 .dev_size = SIZE_1MiB,
709 .cmd_set = P_ID_AMD_STD,
710 .nr_regions = 4,
711 .regions = {
712 ERASEINFO(0x04000,1),
713 ERASEINFO(0x02000,2),
714 ERASEINFO(0x08000,1),
715 ERASEINFO(0x10000,15),
716 }
717 }, {
718 .mfr_id = MANUFACTURER_FUJITSU,
719 .dev_id = MBM29LV650UE,
720 .name = "Fujitsu MBM29LV650UE",
721 .devtypes = CFI_DEVICETYPE_X8,
722 .uaddr = MTD_UADDR_DONT_CARE,
723 .dev_size = SIZE_8MiB,
724 .cmd_set = P_ID_AMD_STD,
725 .nr_regions = 1,
726 .regions = {
727 ERASEINFO(0x10000,128)
728 }
729 }, {
730 .mfr_id = MANUFACTURER_FUJITSU,
731 .dev_id = MBM29LV320TE,
732 .name = "Fujitsu MBM29LV320TE",
733 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
734 .uaddr = MTD_UADDR_0x0AAA_0x0555,
735 .dev_size = SIZE_4MiB,
736 .cmd_set = P_ID_AMD_STD,
737 .nr_regions = 2,
738 .regions = {
739 ERASEINFO(0x10000,63),
740 ERASEINFO(0x02000,8)
741 }
742 }, {
743 .mfr_id = MANUFACTURER_FUJITSU,
744 .dev_id = MBM29LV320BE,
745 .name = "Fujitsu MBM29LV320BE",
746 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
747 .uaddr = MTD_UADDR_0x0AAA_0x0555,
748 .dev_size = SIZE_4MiB,
749 .cmd_set = P_ID_AMD_STD,
750 .nr_regions = 2,
751 .regions = {
752 ERASEINFO(0x02000,8),
753 ERASEINFO(0x10000,63)
754 }
755 }, {
756 .mfr_id = MANUFACTURER_FUJITSU,
757 .dev_id = MBM29LV160TE,
758 .name = "Fujitsu MBM29LV160TE",
759 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
760 .uaddr = MTD_UADDR_0x0AAA_0x0555,
761 .dev_size = SIZE_2MiB,
762 .cmd_set = P_ID_AMD_STD,
763 .nr_regions = 4,
764 .regions = {
765 ERASEINFO(0x10000,31),
766 ERASEINFO(0x08000,1),
767 ERASEINFO(0x02000,2),
768 ERASEINFO(0x04000,1)
769 }
770 }, {
771 .mfr_id = MANUFACTURER_FUJITSU,
772 .dev_id = MBM29LV160BE,
773 .name = "Fujitsu MBM29LV160BE",
774 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
775 .uaddr = MTD_UADDR_0x0AAA_0x0555,
776 .dev_size = SIZE_2MiB,
777 .cmd_set = P_ID_AMD_STD,
778 .nr_regions = 4,
779 .regions = {
780 ERASEINFO(0x04000,1),
781 ERASEINFO(0x02000,2),
782 ERASEINFO(0x08000,1),
783 ERASEINFO(0x10000,31)
784 }
785 }, {
786 .mfr_id = MANUFACTURER_FUJITSU,
787 .dev_id = MBM29LV800BA,
788 .name = "Fujitsu MBM29LV800BA",
789 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
790 .uaddr = MTD_UADDR_0x0AAA_0x0555,
791 .dev_size = SIZE_1MiB,
792 .cmd_set = P_ID_AMD_STD,
793 .nr_regions = 4,
794 .regions = {
795 ERASEINFO(0x04000,1),
796 ERASEINFO(0x02000,2),
797 ERASEINFO(0x08000,1),
798 ERASEINFO(0x10000,15)
799 }
800 }, {
801 .mfr_id = MANUFACTURER_FUJITSU,
802 .dev_id = MBM29LV800TA,
803 .name = "Fujitsu MBM29LV800TA",
804 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
805 .uaddr = MTD_UADDR_0x0AAA_0x0555,
806 .dev_size = SIZE_1MiB,
807 .cmd_set = P_ID_AMD_STD,
808 .nr_regions = 4,
809 .regions = {
810 ERASEINFO(0x10000,15),
811 ERASEINFO(0x08000,1),
812 ERASEINFO(0x02000,2),
813 ERASEINFO(0x04000,1)
814 }
815 }, {
816 .mfr_id = MANUFACTURER_FUJITSU,
817 .dev_id = MBM29LV400BC,
818 .name = "Fujitsu MBM29LV400BC",
819 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
820 .uaddr = MTD_UADDR_0x0AAA_0x0555,
821 .dev_size = SIZE_512KiB,
822 .cmd_set = P_ID_AMD_STD,
823 .nr_regions = 4,
824 .regions = {
825 ERASEINFO(0x04000,1),
826 ERASEINFO(0x02000,2),
827 ERASEINFO(0x08000,1),
828 ERASEINFO(0x10000,7)
829 }
830 }, {
831 .mfr_id = MANUFACTURER_FUJITSU,
832 .dev_id = MBM29LV400TC,
833 .name = "Fujitsu MBM29LV400TC",
834 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
835 .uaddr = MTD_UADDR_0x0AAA_0x0555,
836 .dev_size = SIZE_512KiB,
837 .cmd_set = P_ID_AMD_STD,
838 .nr_regions = 4,
839 .regions = {
840 ERASEINFO(0x10000,7),
841 ERASEINFO(0x08000,1),
842 ERASEINFO(0x02000,2),
843 ERASEINFO(0x04000,1)
844 }
845 }, {
846 .mfr_id = MANUFACTURER_HYUNDAI,
847 .dev_id = HY29F002T,
848 .name = "Hyundai HY29F002T",
849 .devtypes = CFI_DEVICETYPE_X8,
850 .uaddr = MTD_UADDR_0x0555_0x02AA,
851 .dev_size = SIZE_256KiB,
852 .cmd_set = P_ID_AMD_STD,
853 .nr_regions = 4,
854 .regions = {
855 ERASEINFO(0x10000,3),
856 ERASEINFO(0x08000,1),
857 ERASEINFO(0x02000,2),
858 ERASEINFO(0x04000,1),
859 }
860 }, {
861 .mfr_id = MANUFACTURER_INTEL,
862 .dev_id = I28F004B3B,
863 .name = "Intel 28F004B3B",
864 .devtypes = CFI_DEVICETYPE_X8,
865 .uaddr = MTD_UADDR_UNNECESSARY,
866 .dev_size = SIZE_512KiB,
867 .cmd_set = P_ID_INTEL_STD,
868 .nr_regions = 2,
869 .regions = {
870 ERASEINFO(0x02000, 8),
871 ERASEINFO(0x10000, 7),
872 }
873 }, {
874 .mfr_id = MANUFACTURER_INTEL,
875 .dev_id = I28F004B3T,
876 .name = "Intel 28F004B3T",
877 .devtypes = CFI_DEVICETYPE_X8,
878 .uaddr = MTD_UADDR_UNNECESSARY,
879 .dev_size = SIZE_512KiB,
880 .cmd_set = P_ID_INTEL_STD,
881 .nr_regions = 2,
882 .regions = {
883 ERASEINFO(0x10000, 7),
884 ERASEINFO(0x02000, 8),
885 }
886 }, {
887 .mfr_id = MANUFACTURER_INTEL,
888 .dev_id = I28F400B3B,
889 .name = "Intel 28F400B3B",
890 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
891 .uaddr = MTD_UADDR_UNNECESSARY,
892 .dev_size = SIZE_512KiB,
893 .cmd_set = P_ID_INTEL_STD,
894 .nr_regions = 2,
895 .regions = {
896 ERASEINFO(0x02000, 8),
897 ERASEINFO(0x10000, 7),
898 }
899 }, {
900 .mfr_id = MANUFACTURER_INTEL,
901 .dev_id = I28F400B3T,
902 .name = "Intel 28F400B3T",
903 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
904 .uaddr = MTD_UADDR_UNNECESSARY,
905 .dev_size = SIZE_512KiB,
906 .cmd_set = P_ID_INTEL_STD,
907 .nr_regions = 2,
908 .regions = {
909 ERASEINFO(0x10000, 7),
910 ERASEINFO(0x02000, 8),
911 }
912 }, {
913 .mfr_id = MANUFACTURER_INTEL,
914 .dev_id = I28F008B3B,
915 .name = "Intel 28F008B3B",
916 .devtypes = CFI_DEVICETYPE_X8,
917 .uaddr = MTD_UADDR_UNNECESSARY,
918 .dev_size = SIZE_1MiB,
919 .cmd_set = P_ID_INTEL_STD,
920 .nr_regions = 2,
921 .regions = {
922 ERASEINFO(0x02000, 8),
923 ERASEINFO(0x10000, 15),
924 }
925 }, {
926 .mfr_id = MANUFACTURER_INTEL,
927 .dev_id = I28F008B3T,
928 .name = "Intel 28F008B3T",
929 .devtypes = CFI_DEVICETYPE_X8,
930 .uaddr = MTD_UADDR_UNNECESSARY,
931 .dev_size = SIZE_1MiB,
932 .cmd_set = P_ID_INTEL_STD,
933 .nr_regions = 2,
934 .regions = {
935 ERASEINFO(0x10000, 15),
936 ERASEINFO(0x02000, 8),
937 }
938 }, {
939 .mfr_id = MANUFACTURER_INTEL,
940 .dev_id = I28F008S5,
941 .name = "Intel 28F008S5",
942 .devtypes = CFI_DEVICETYPE_X8,
943 .uaddr = MTD_UADDR_UNNECESSARY,
944 .dev_size = SIZE_1MiB,
945 .cmd_set = P_ID_INTEL_EXT,
946 .nr_regions = 1,
947 .regions = {
948 ERASEINFO(0x10000,16),
949 }
950 }, {
951 .mfr_id = MANUFACTURER_INTEL,
952 .dev_id = I28F016S5,
953 .name = "Intel 28F016S5",
954 .devtypes = CFI_DEVICETYPE_X8,
955 .uaddr = MTD_UADDR_UNNECESSARY,
956 .dev_size = SIZE_2MiB,
957 .cmd_set = P_ID_INTEL_EXT,
958 .nr_regions = 1,
959 .regions = {
960 ERASEINFO(0x10000,32),
961 }
962 }, {
963 .mfr_id = MANUFACTURER_INTEL,
964 .dev_id = I28F008SA,
965 .name = "Intel 28F008SA",
966 .devtypes = CFI_DEVICETYPE_X8,
967 .uaddr = MTD_UADDR_UNNECESSARY,
968 .dev_size = SIZE_1MiB,
969 .cmd_set = P_ID_INTEL_STD,
970 .nr_regions = 1,
971 .regions = {
972 ERASEINFO(0x10000, 16),
973 }
974 }, {
975 .mfr_id = MANUFACTURER_INTEL,
976 .dev_id = I28F800B3B,
977 .name = "Intel 28F800B3B",
978 .devtypes = CFI_DEVICETYPE_X16,
979 .uaddr = MTD_UADDR_UNNECESSARY,
980 .dev_size = SIZE_1MiB,
981 .cmd_set = P_ID_INTEL_STD,
982 .nr_regions = 2,
983 .regions = {
984 ERASEINFO(0x02000, 8),
985 ERASEINFO(0x10000, 15),
986 }
987 }, {
988 .mfr_id = MANUFACTURER_INTEL,
989 .dev_id = I28F800B3T,
990 .name = "Intel 28F800B3T",
991 .devtypes = CFI_DEVICETYPE_X16,
992 .uaddr = MTD_UADDR_UNNECESSARY,
993 .dev_size = SIZE_1MiB,
994 .cmd_set = P_ID_INTEL_STD,
995 .nr_regions = 2,
996 .regions = {
997 ERASEINFO(0x10000, 15),
998 ERASEINFO(0x02000, 8),
999 }
1000 }, {
1001 .mfr_id = MANUFACTURER_INTEL,
1002 .dev_id = I28F016B3B,
1003 .name = "Intel 28F016B3B",
1004 .devtypes = CFI_DEVICETYPE_X8,
1005 .uaddr = MTD_UADDR_UNNECESSARY,
1006 .dev_size = SIZE_2MiB,
1007 .cmd_set = P_ID_INTEL_STD,
1008 .nr_regions = 2,
1009 .regions = {
1010 ERASEINFO(0x02000, 8),
1011 ERASEINFO(0x10000, 31),
1012 }
1013 }, {
1014 .mfr_id = MANUFACTURER_INTEL,
1015 .dev_id = I28F016S3,
1016 .name = "Intel I28F016S3",
1017 .devtypes = CFI_DEVICETYPE_X8,
1018 .uaddr = MTD_UADDR_UNNECESSARY,
1019 .dev_size = SIZE_2MiB,
1020 .cmd_set = P_ID_INTEL_STD,
1021 .nr_regions = 1,
1022 .regions = {
1023 ERASEINFO(0x10000, 32),
1024 }
1025 }, {
1026 .mfr_id = MANUFACTURER_INTEL,
1027 .dev_id = I28F016B3T,
1028 .name = "Intel 28F016B3T",
1029 .devtypes = CFI_DEVICETYPE_X8,
1030 .uaddr = MTD_UADDR_UNNECESSARY,
1031 .dev_size = SIZE_2MiB,
1032 .cmd_set = P_ID_INTEL_STD,
1033 .nr_regions = 2,
1034 .regions = {
1035 ERASEINFO(0x10000, 31),
1036 ERASEINFO(0x02000, 8),
1037 }
1038 }, {
1039 .mfr_id = MANUFACTURER_INTEL,
1040 .dev_id = I28F160B3B,
1041 .name = "Intel 28F160B3B",
1042 .devtypes = CFI_DEVICETYPE_X16,
1043 .uaddr = MTD_UADDR_UNNECESSARY,
1044 .dev_size = SIZE_2MiB,
1045 .cmd_set = P_ID_INTEL_STD,
1046 .nr_regions = 2,
1047 .regions = {
1048 ERASEINFO(0x02000, 8),
1049 ERASEINFO(0x10000, 31),
1050 }
1051 }, {
1052 .mfr_id = MANUFACTURER_INTEL,
1053 .dev_id = I28F160B3T,
1054 .name = "Intel 28F160B3T",
1055 .devtypes = CFI_DEVICETYPE_X16,
1056 .uaddr = MTD_UADDR_UNNECESSARY,
1057 .dev_size = SIZE_2MiB,
1058 .cmd_set = P_ID_INTEL_STD,
1059 .nr_regions = 2,
1060 .regions = {
1061 ERASEINFO(0x10000, 31),
1062 ERASEINFO(0x02000, 8),
1063 }
1064 }, {
1065 .mfr_id = MANUFACTURER_INTEL,
1066 .dev_id = I28F320B3B,
1067 .name = "Intel 28F320B3B",
1068 .devtypes = CFI_DEVICETYPE_X16,
1069 .uaddr = MTD_UADDR_UNNECESSARY,
1070 .dev_size = SIZE_4MiB,
1071 .cmd_set = P_ID_INTEL_STD,
1072 .nr_regions = 2,
1073 .regions = {
1074 ERASEINFO(0x02000, 8),
1075 ERASEINFO(0x10000, 63),
1076 }
1077 }, {
1078 .mfr_id = MANUFACTURER_INTEL,
1079 .dev_id = I28F320B3T,
1080 .name = "Intel 28F320B3T",
1081 .devtypes = CFI_DEVICETYPE_X16,
1082 .uaddr = MTD_UADDR_UNNECESSARY,
1083 .dev_size = SIZE_4MiB,
1084 .cmd_set = P_ID_INTEL_STD,
1085 .nr_regions = 2,
1086 .regions = {
1087 ERASEINFO(0x10000, 63),
1088 ERASEINFO(0x02000, 8),
1089 }
1090 }, {
1091 .mfr_id = MANUFACTURER_INTEL,
1092 .dev_id = I28F640B3B,
1093 .name = "Intel 28F640B3B",
1094 .devtypes = CFI_DEVICETYPE_X16,
1095 .uaddr = MTD_UADDR_UNNECESSARY,
1096 .dev_size = SIZE_8MiB,
1097 .cmd_set = P_ID_INTEL_STD,
1098 .nr_regions = 2,
1099 .regions = {
1100 ERASEINFO(0x02000, 8),
1101 ERASEINFO(0x10000, 127),
1102 }
1103 }, {
1104 .mfr_id = MANUFACTURER_INTEL,
1105 .dev_id = I28F640B3T,
1106 .name = "Intel 28F640B3T",
1107 .devtypes = CFI_DEVICETYPE_X16,
1108 .uaddr = MTD_UADDR_UNNECESSARY,
1109 .dev_size = SIZE_8MiB,
1110 .cmd_set = P_ID_INTEL_STD,
1111 .nr_regions = 2,
1112 .regions = {
1113 ERASEINFO(0x10000, 127),
1114 ERASEINFO(0x02000, 8),
1115 }
1116 }, {
1117 .mfr_id = MANUFACTURER_INTEL,
1118 .dev_id = I28F640C3B,
1119 .name = "Intel 28F640C3B",
1120 .devtypes = CFI_DEVICETYPE_X16,
1121 .uaddr = MTD_UADDR_UNNECESSARY,
1122 .dev_size = SIZE_8MiB,
1123 .cmd_set = P_ID_INTEL_STD,
1124 .nr_regions = 2,
1125 .regions = {
1126 ERASEINFO(0x02000, 8),
1127 ERASEINFO(0x10000, 127),
1128 }
1129 }, {
1130 .mfr_id = MANUFACTURER_INTEL,
1131 .dev_id = I82802AB,
1132 .name = "Intel 82802AB",
1133 .devtypes = CFI_DEVICETYPE_X8,
1134 .uaddr = MTD_UADDR_UNNECESSARY,
1135 .dev_size = SIZE_512KiB,
1136 .cmd_set = P_ID_INTEL_EXT,
1137 .nr_regions = 1,
1138 .regions = {
1139 ERASEINFO(0x10000,8),
1140 }
1141 }, {
1142 .mfr_id = MANUFACTURER_INTEL,
1143 .dev_id = I82802AC,
1144 .name = "Intel 82802AC",
1145 .devtypes = CFI_DEVICETYPE_X8,
1146 .uaddr = MTD_UADDR_UNNECESSARY,
1147 .dev_size = SIZE_1MiB,
1148 .cmd_set = P_ID_INTEL_EXT,
1149 .nr_regions = 1,
1150 .regions = {
1151 ERASEINFO(0x10000,16),
1152 }
1153 }, {
1154 .mfr_id = MANUFACTURER_MACRONIX,
1155 .dev_id = MX29LV040C,
1156 .name = "Macronix MX29LV040C",
1157 .devtypes = CFI_DEVICETYPE_X8,
1158 .uaddr = MTD_UADDR_0x0555_0x02AA,
1159 .dev_size = SIZE_512KiB,
1160 .cmd_set = P_ID_AMD_STD,
1161 .nr_regions = 1,
1162 .regions = {
1163 ERASEINFO(0x10000,8),
1164 }
1165 }, {
1166 .mfr_id = MANUFACTURER_MACRONIX,
1167 .dev_id = MX29LV160T,
1168 .name = "MXIC MX29LV160T",
1169 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1170 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1171 .dev_size = SIZE_2MiB,
1172 .cmd_set = P_ID_AMD_STD,
1173 .nr_regions = 4,
1174 .regions = {
1175 ERASEINFO(0x10000,31),
1176 ERASEINFO(0x08000,1),
1177 ERASEINFO(0x02000,2),
1178 ERASEINFO(0x04000,1)
1179 }
1180 }, {
1181 .mfr_id = MANUFACTURER_NEC,
1182 .dev_id = UPD29F064115,
1183 .name = "NEC uPD29F064115",
1184 .devtypes = CFI_DEVICETYPE_X16,
1185 .uaddr = MTD_UADDR_0xAAAA_0x5555,
1186 .dev_size = SIZE_8MiB,
1187 .cmd_set = P_ID_AMD_STD,
1188 .nr_regions = 3,
1189 .regions = {
1190 ERASEINFO(0x2000,8),
1191 ERASEINFO(0x10000,126),
1192 ERASEINFO(0x2000,8),
1193 }
1194 }, {
1195 .mfr_id = MANUFACTURER_MACRONIX,
1196 .dev_id = MX29LV160B,
1197 .name = "MXIC MX29LV160B",
1198 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1199 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1200 .dev_size = SIZE_2MiB,
1201 .cmd_set = P_ID_AMD_STD,
1202 .nr_regions = 4,
1203 .regions = {
1204 ERASEINFO(0x04000,1),
1205 ERASEINFO(0x02000,2),
1206 ERASEINFO(0x08000,1),
1207 ERASEINFO(0x10000,31)
1208 }
1209 }, {
1210 .mfr_id = MANUFACTURER_MACRONIX,
1211 .dev_id = MX29F040,
1212 .name = "Macronix MX29F040",
1213 .devtypes = CFI_DEVICETYPE_X8,
1214 .uaddr = MTD_UADDR_0x0555_0x02AA,
1215 .dev_size = SIZE_512KiB,
1216 .cmd_set = P_ID_AMD_STD,
1217 .nr_regions = 1,
1218 .regions = {
1219 ERASEINFO(0x10000,8),
1220 }
1221 }, {
1222 .mfr_id = MANUFACTURER_MACRONIX,
1223 .dev_id = MX29F016,
1224 .name = "Macronix MX29F016",
1225 .devtypes = CFI_DEVICETYPE_X8,
1226 .uaddr = MTD_UADDR_0x0555_0x02AA,
1227 .dev_size = SIZE_2MiB,
1228 .cmd_set = P_ID_AMD_STD,
1229 .nr_regions = 1,
1230 .regions = {
1231 ERASEINFO(0x10000,32),
1232 }
1233 }, {
1234 .mfr_id = MANUFACTURER_MACRONIX,
1235 .dev_id = MX29F004T,
1236 .name = "Macronix MX29F004T",
1237 .devtypes = CFI_DEVICETYPE_X8,
1238 .uaddr = MTD_UADDR_0x0555_0x02AA,
1239 .dev_size = SIZE_512KiB,
1240 .cmd_set = P_ID_AMD_STD,
1241 .nr_regions = 4,
1242 .regions = {
1243 ERASEINFO(0x10000,7),
1244 ERASEINFO(0x08000,1),
1245 ERASEINFO(0x02000,2),
1246 ERASEINFO(0x04000,1),
1247 }
1248 }, {
1249 .mfr_id = MANUFACTURER_MACRONIX,
1250 .dev_id = MX29F004B,
1251 .name = "Macronix MX29F004B",
1252 .devtypes = CFI_DEVICETYPE_X8,
1253 .uaddr = MTD_UADDR_0x0555_0x02AA,
1254 .dev_size = SIZE_512KiB,
1255 .cmd_set = P_ID_AMD_STD,
1256 .nr_regions = 4,
1257 .regions = {
1258 ERASEINFO(0x04000,1),
1259 ERASEINFO(0x02000,2),
1260 ERASEINFO(0x08000,1),
1261 ERASEINFO(0x10000,7),
1262 }
1263 }, {
1264 .mfr_id = MANUFACTURER_MACRONIX,
1265 .dev_id = MX29F002T,
1266 .name = "Macronix MX29F002T",
1267 .devtypes = CFI_DEVICETYPE_X8,
1268 .uaddr = MTD_UADDR_0x0555_0x02AA,
1269 .dev_size = SIZE_256KiB,
1270 .cmd_set = P_ID_AMD_STD,
1271 .nr_regions = 4,
1272 .regions = {
1273 ERASEINFO(0x10000,3),
1274 ERASEINFO(0x08000,1),
1275 ERASEINFO(0x02000,2),
1276 ERASEINFO(0x04000,1),
1277 }
1278 }, {
1279 .mfr_id = MANUFACTURER_PMC,
1280 .dev_id = PM49FL002,
1281 .name = "PMC Pm49FL002",
1282 .devtypes = CFI_DEVICETYPE_X8,
1283 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1284 .dev_size = SIZE_256KiB,
1285 .cmd_set = P_ID_AMD_STD,
1286 .nr_regions = 1,
1287 .regions = {
1288 ERASEINFO( 0x01000, 64 )
1289 }
1290 }, {
1291 .mfr_id = MANUFACTURER_PMC,
1292 .dev_id = PM49FL004,
1293 .name = "PMC Pm49FL004",
1294 .devtypes = CFI_DEVICETYPE_X8,
1295 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1296 .dev_size = SIZE_512KiB,
1297 .cmd_set = P_ID_AMD_STD,
1298 .nr_regions = 1,
1299 .regions = {
1300 ERASEINFO( 0x01000, 128 )
1301 }
1302 }, {
1303 .mfr_id = MANUFACTURER_PMC,
1304 .dev_id = PM49FL008,
1305 .name = "PMC Pm49FL008",
1306 .devtypes = CFI_DEVICETYPE_X8,
1307 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1308 .dev_size = SIZE_1MiB,
1309 .cmd_set = P_ID_AMD_STD,
1310 .nr_regions = 1,
1311 .regions = {
1312 ERASEINFO( 0x01000, 256 )
1313 }
1314 }, {
1315 .mfr_id = MANUFACTURER_SHARP,
1316 .dev_id = LH28F640BF,
1317 .name = "LH28F640BF",
1318 .devtypes = CFI_DEVICETYPE_X8,
1319 .uaddr = MTD_UADDR_UNNECESSARY,
1320 .dev_size = SIZE_4MiB,
1321 .cmd_set = P_ID_INTEL_STD,
1322 .nr_regions = 1,
1323 .regions = {
1324 ERASEINFO(0x40000,16),
1325 }
1326 }, {
1327 .mfr_id = MANUFACTURER_SST,
1328 .dev_id = SST39LF512,
1329 .name = "SST 39LF512",
1330 .devtypes = CFI_DEVICETYPE_X8,
1331 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1332 .dev_size = SIZE_64KiB,
1333 .cmd_set = P_ID_AMD_STD,
1334 .nr_regions = 1,
1335 .regions = {
1336 ERASEINFO(0x01000,16),
1337 }
1338 }, {
1339 .mfr_id = MANUFACTURER_SST,
1340 .dev_id = SST39LF010,
1341 .name = "SST 39LF010",
1342 .devtypes = CFI_DEVICETYPE_X8,
1343 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1344 .dev_size = SIZE_128KiB,
1345 .cmd_set = P_ID_AMD_STD,
1346 .nr_regions = 1,
1347 .regions = {
1348 ERASEINFO(0x01000,32),
1349 }
1350 }, {
1351 .mfr_id = MANUFACTURER_SST,
1352 .dev_id = SST29EE020,
1353 .name = "SST 29EE020",
1354 .devtypes = CFI_DEVICETYPE_X8,
1355 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1356 .dev_size = SIZE_256KiB,
1357 .cmd_set = P_ID_SST_PAGE,
1358 .nr_regions = 1,
1359 .regions = {ERASEINFO(0x01000,64),
1360 }
1361 }, {
1362 .mfr_id = MANUFACTURER_SST,
1363 .dev_id = SST29LE020,
1364 .name = "SST 29LE020",
1365 .devtypes = CFI_DEVICETYPE_X8,
1366 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1367 .dev_size = SIZE_256KiB,
1368 .cmd_set = P_ID_SST_PAGE,
1369 .nr_regions = 1,
1370 .regions = {ERASEINFO(0x01000,64),
1371 }
1372 }, {
1373 .mfr_id = MANUFACTURER_SST,
1374 .dev_id = SST39LF020,
1375 .name = "SST 39LF020",
1376 .devtypes = CFI_DEVICETYPE_X8,
1377 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1378 .dev_size = SIZE_256KiB,
1379 .cmd_set = P_ID_AMD_STD,
1380 .nr_regions = 1,
1381 .regions = {
1382 ERASEINFO(0x01000,64),
1383 }
1384 }, {
1385 .mfr_id = MANUFACTURER_SST,
1386 .dev_id = SST39LF040,
1387 .name = "SST 39LF040",
1388 .devtypes = CFI_DEVICETYPE_X8,
1389 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1390 .dev_size = SIZE_512KiB,
1391 .cmd_set = P_ID_AMD_STD,
1392 .nr_regions = 1,
1393 .regions = {
1394 ERASEINFO(0x01000,128),
1395 }
1396 }, {
1397 .mfr_id = MANUFACTURER_SST,
1398 .dev_id = SST39SF010A,
1399 .name = "SST 39SF010A",
1400 .devtypes = CFI_DEVICETYPE_X8,
1401 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1402 .dev_size = SIZE_128KiB,
1403 .cmd_set = P_ID_AMD_STD,
1404 .nr_regions = 1,
1405 .regions = {
1406 ERASEINFO(0x01000,32),
1407 }
1408 }, {
1409 .mfr_id = MANUFACTURER_SST,
1410 .dev_id = SST39SF020A,
1411 .name = "SST 39SF020A",
1412 .devtypes = CFI_DEVICETYPE_X8,
1413 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1414 .dev_size = SIZE_256KiB,
1415 .cmd_set = P_ID_AMD_STD,
1416 .nr_regions = 1,
1417 .regions = {
1418 ERASEINFO(0x01000,64),
1419 }
1420 }, {
1421 .mfr_id = MANUFACTURER_SST,
1422 .dev_id = SST39SF040,
1423 .name = "SST 39SF040",
1424 .devtypes = CFI_DEVICETYPE_X8,
1425 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1426 .dev_size = SIZE_512KiB,
1427 .cmd_set = P_ID_AMD_STD,
1428 .nr_regions = 1,
1429 .regions = {
1430 ERASEINFO(0x01000,128),
1431 }
1432 }, {
1433 .mfr_id = MANUFACTURER_SST,
1434 .dev_id = SST49LF040B,
1435 .name = "SST 49LF040B",
1436 .devtypes = CFI_DEVICETYPE_X8,
1437 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1438 .dev_size = SIZE_512KiB,
1439 .cmd_set = P_ID_AMD_STD,
1440 .nr_regions = 1,
1441 .regions = {
1442 ERASEINFO(0x01000,128),
1443 }
1444 }, {
1445
1446 .mfr_id = MANUFACTURER_SST,
1447 .dev_id = SST49LF004B,
1448 .name = "SST 49LF004B",
1449 .devtypes = CFI_DEVICETYPE_X8,
1450 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1451 .dev_size = SIZE_512KiB,
1452 .cmd_set = P_ID_AMD_STD,
1453 .nr_regions = 1,
1454 .regions = {
1455 ERASEINFO(0x01000,128),
1456 }
1457 }, {
1458 .mfr_id = MANUFACTURER_SST,
1459 .dev_id = SST49LF008A,
1460 .name = "SST 49LF008A",
1461 .devtypes = CFI_DEVICETYPE_X8,
1462 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1463 .dev_size = SIZE_1MiB,
1464 .cmd_set = P_ID_AMD_STD,
1465 .nr_regions = 1,
1466 .regions = {
1467 ERASEINFO(0x01000,256),
1468 }
1469 }, {
1470 .mfr_id = MANUFACTURER_SST,
1471 .dev_id = SST49LF030A,
1472 .name = "SST 49LF030A",
1473 .devtypes = CFI_DEVICETYPE_X8,
1474 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1475 .dev_size = SIZE_512KiB,
1476 .cmd_set = P_ID_AMD_STD,
1477 .nr_regions = 1,
1478 .regions = {
1479 ERASEINFO(0x01000,96),
1480 }
1481 }, {
1482 .mfr_id = MANUFACTURER_SST,
1483 .dev_id = SST49LF040A,
1484 .name = "SST 49LF040A",
1485 .devtypes = CFI_DEVICETYPE_X8,
1486 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1487 .dev_size = SIZE_512KiB,
1488 .cmd_set = P_ID_AMD_STD,
1489 .nr_regions = 1,
1490 .regions = {
1491 ERASEINFO(0x01000,128),
1492 }
1493 }, {
1494 .mfr_id = MANUFACTURER_SST,
1495 .dev_id = SST49LF080A,
1496 .name = "SST 49LF080A",
1497 .devtypes = CFI_DEVICETYPE_X8,
1498 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1499 .dev_size = SIZE_1MiB,
1500 .cmd_set = P_ID_AMD_STD,
1501 .nr_regions = 1,
1502 .regions = {
1503 ERASEINFO(0x01000,256),
1504 }
1505 }, {
1506 .mfr_id = MANUFACTURER_SST, /* should be CFI */
1507 .dev_id = SST39LF160,
1508 .name = "SST 39LF160",
1509 .devtypes = CFI_DEVICETYPE_X16,
1510 .uaddr = MTD_UADDR_0xAAAA_0x5555,
1511 .dev_size = SIZE_2MiB,
1512 .cmd_set = P_ID_AMD_STD,
1513 .nr_regions = 2,
1514 .regions = {
1515 ERASEINFO(0x1000,256),
1516 ERASEINFO(0x1000,256)
1517 }
1518 }, {
1519 .mfr_id = MANUFACTURER_SST, /* should be CFI */
1520 .dev_id = SST39VF1601,
1521 .name = "SST 39VF1601",
1522 .devtypes = CFI_DEVICETYPE_X16,
1523 .uaddr = MTD_UADDR_0xAAAA_0x5555,
1524 .dev_size = SIZE_2MiB,
1525 .cmd_set = P_ID_AMD_STD,
1526 .nr_regions = 2,
1527 .regions = {
1528 ERASEINFO(0x1000,256),
1529 ERASEINFO(0x1000,256)
1530 }
1531 }, {
1532 .mfr_id = MANUFACTURER_SST, /* should be CFI */
1533 .dev_id = SST39VF3201,
1534 .name = "SST 39VF3201",
1535 .devtypes = CFI_DEVICETYPE_X16,
1536 .uaddr = MTD_UADDR_0xAAAA_0x5555,
1537 .dev_size = SIZE_4MiB,
1538 .cmd_set = P_ID_AMD_STD,
1539 .nr_regions = 4,
1540 .regions = {
1541 ERASEINFO(0x1000,256),
1542 ERASEINFO(0x1000,256),
1543 ERASEINFO(0x1000,256),
1544 ERASEINFO(0x1000,256)
1545 }
1546 }, {
1547 .mfr_id = MANUFACTURER_SST,
1548 .dev_id = SST36VF3203,
1549 .name = "SST 36VF3203",
1550 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1551 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1552 .dev_size = SIZE_4MiB,
1553 .cmd_set = P_ID_AMD_STD,
1554 .nr_regions = 1,
1555 .regions = {
1556 ERASEINFO(0x10000,64),
1557 }
1558 }, {
1559 .mfr_id = MANUFACTURER_ST,
1560 .dev_id = M29F800AB,
1561 .name = "ST M29F800AB",
1562 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1563 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1564 .dev_size = SIZE_1MiB,
1565 .cmd_set = P_ID_AMD_STD,
1566 .nr_regions = 4,
1567 .regions = {
1568 ERASEINFO(0x04000,1),
1569 ERASEINFO(0x02000,2),
1570 ERASEINFO(0x08000,1),
1571 ERASEINFO(0x10000,15),
1572 }
1573 }, {
1574 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1575 .dev_id = M29W800DT,
1576 .name = "ST M29W800DT",
1577 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1578 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1579 .dev_size = SIZE_1MiB,
1580 .cmd_set = P_ID_AMD_STD,
1581 .nr_regions = 4,
1582 .regions = {
1583 ERASEINFO(0x10000,15),
1584 ERASEINFO(0x08000,1),
1585 ERASEINFO(0x02000,2),
1586 ERASEINFO(0x04000,1)
1587 }
1588 }, {
1589 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1590 .dev_id = M29W800DB,
1591 .name = "ST M29W800DB",
1592 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1593 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1594 .dev_size = SIZE_1MiB,
1595 .cmd_set = P_ID_AMD_STD,
1596 .nr_regions = 4,
1597 .regions = {
1598 ERASEINFO(0x04000,1),
1599 ERASEINFO(0x02000,2),
1600 ERASEINFO(0x08000,1),
1601 ERASEINFO(0x10000,15)
1602 }
1603 }, {
1604 .mfr_id = MANUFACTURER_ST,
1605 .dev_id = M29W400DT,
1606 .name = "ST M29W400DT",
1607 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1608 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1609 .dev_size = SIZE_512KiB,
1610 .cmd_set = P_ID_AMD_STD,
1611 .nr_regions = 4,
1612 .regions = {
1613 ERASEINFO(0x04000,7),
1614 ERASEINFO(0x02000,1),
1615 ERASEINFO(0x08000,2),
1616 ERASEINFO(0x10000,1)
1617 }
1618 }, {
1619 .mfr_id = MANUFACTURER_ST,
1620 .dev_id = M29W400DB,
1621 .name = "ST M29W400DB",
1622 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1623 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1624 .dev_size = SIZE_512KiB,
1625 .cmd_set = P_ID_AMD_STD,
1626 .nr_regions = 4,
1627 .regions = {
1628 ERASEINFO(0x04000,1),
1629 ERASEINFO(0x02000,2),
1630 ERASEINFO(0x08000,1),
1631 ERASEINFO(0x10000,7)
1632 }
1633 }, {
1634 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1635 .dev_id = M29W160DT,
1636 .name = "ST M29W160DT",
1637 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1638 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
1639 .dev_size = SIZE_2MiB,
1640 .cmd_set = P_ID_AMD_STD,
1641 .nr_regions = 4,
1642 .regions = {
1643 ERASEINFO(0x10000,31),
1644 ERASEINFO(0x08000,1),
1645 ERASEINFO(0x02000,2),
1646 ERASEINFO(0x04000,1)
1647 }
1648 }, {
1649 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1650 .dev_id = M29W160DB,
1651 .name = "ST M29W160DB",
1652 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1653 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
1654 .dev_size = SIZE_2MiB,
1655 .cmd_set = P_ID_AMD_STD,
1656 .nr_regions = 4,
1657 .regions = {
1658 ERASEINFO(0x04000,1),
1659 ERASEINFO(0x02000,2),
1660 ERASEINFO(0x08000,1),
1661 ERASEINFO(0x10000,31)
1662 }
1663 }, {
1664 .mfr_id = MANUFACTURER_ST,
1665 .dev_id = M29W040B,
1666 .name = "ST M29W040B",
1667 .devtypes = CFI_DEVICETYPE_X8,
1668 .uaddr = MTD_UADDR_0x0555_0x02AA,
1669 .dev_size = SIZE_512KiB,
1670 .cmd_set = P_ID_AMD_STD,
1671 .nr_regions = 1,
1672 .regions = {
1673 ERASEINFO(0x10000,8),
1674 }
1675 }, {
1676 .mfr_id = MANUFACTURER_ST,
1677 .dev_id = M50FW040,
1678 .name = "ST M50FW040",
1679 .devtypes = CFI_DEVICETYPE_X8,
1680 .uaddr = MTD_UADDR_UNNECESSARY,
1681 .dev_size = SIZE_512KiB,
1682 .cmd_set = P_ID_INTEL_EXT,
1683 .nr_regions = 1,
1684 .regions = {
1685 ERASEINFO(0x10000,8),
1686 }
1687 }, {
1688 .mfr_id = MANUFACTURER_ST,
1689 .dev_id = M50FW080,
1690 .name = "ST M50FW080",
1691 .devtypes = CFI_DEVICETYPE_X8,
1692 .uaddr = MTD_UADDR_UNNECESSARY,
1693 .dev_size = SIZE_1MiB,
1694 .cmd_set = P_ID_INTEL_EXT,
1695 .nr_regions = 1,
1696 .regions = {
1697 ERASEINFO(0x10000,16),
1698 }
1699 }, {
1700 .mfr_id = MANUFACTURER_ST,
1701 .dev_id = M50FW016,
1702 .name = "ST M50FW016",
1703 .devtypes = CFI_DEVICETYPE_X8,
1704 .uaddr = MTD_UADDR_UNNECESSARY,
1705 .dev_size = SIZE_2MiB,
1706 .cmd_set = P_ID_INTEL_EXT,
1707 .nr_regions = 1,
1708 .regions = {
1709 ERASEINFO(0x10000,32),
1710 }
1711 }, {
1712 .mfr_id = MANUFACTURER_ST,
1713 .dev_id = M50LPW080,
1714 .name = "ST M50LPW080",
1715 .devtypes = CFI_DEVICETYPE_X8,
1716 .uaddr = MTD_UADDR_UNNECESSARY,
1717 .dev_size = SIZE_1MiB,
1718 .cmd_set = P_ID_INTEL_EXT,
1719 .nr_regions = 1,
1720 .regions = {
1721 ERASEINFO(0x10000,16),
1722 },
1723 }, {
1724 .mfr_id = MANUFACTURER_ST,
1725 .dev_id = M50FLW080A,
1726 .name = "ST M50FLW080A",
1727 .devtypes = CFI_DEVICETYPE_X8,
1728 .uaddr = MTD_UADDR_UNNECESSARY,
1729 .dev_size = SIZE_1MiB,
1730 .cmd_set = P_ID_INTEL_EXT,
1731 .nr_regions = 4,
1732 .regions = {
1733 ERASEINFO(0x1000,16),
1734 ERASEINFO(0x10000,13),
1735 ERASEINFO(0x1000,16),
1736 ERASEINFO(0x1000,16),
1737 }
1738 }, {
1739 .mfr_id = MANUFACTURER_ST,
1740 .dev_id = M50FLW080B,
1741 .name = "ST M50FLW080B",
1742 .devtypes = CFI_DEVICETYPE_X8,
1743 .uaddr = MTD_UADDR_UNNECESSARY,
1744 .dev_size = SIZE_1MiB,
1745 .cmd_set = P_ID_INTEL_EXT,
1746 .nr_regions = 4,
1747 .regions = {
1748 ERASEINFO(0x1000,16),
1749 ERASEINFO(0x1000,16),
1750 ERASEINFO(0x10000,13),
1751 ERASEINFO(0x1000,16),
1752 }
1753 }, {
1754 .mfr_id = 0xff00 | MANUFACTURER_ST,
1755 .dev_id = 0xff00 | PSD4256G6V,
1756 .name = "ST PSD4256G6V",
1757 .devtypes = CFI_DEVICETYPE_X16,
1758 .uaddr = MTD_UADDR_0x0AAA_0x0554,
1759 .dev_size = SIZE_1MiB,
1760 .cmd_set = P_ID_AMD_STD,
1761 .nr_regions = 1,
1762 .regions = {
1763 ERASEINFO(0x10000,16),
1764 }
1765 }, {
1766 .mfr_id = MANUFACTURER_TOSHIBA,
1767 .dev_id = TC58FVT160,
1768 .name = "Toshiba TC58FVT160",
1769 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1770 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1771 .dev_size = SIZE_2MiB,
1772 .cmd_set = P_ID_AMD_STD,
1773 .nr_regions = 4,
1774 .regions = {
1775 ERASEINFO(0x10000,31),
1776 ERASEINFO(0x08000,1),
1777 ERASEINFO(0x02000,2),
1778 ERASEINFO(0x04000,1)
1779 }
1780 }, {
1781 .mfr_id = MANUFACTURER_TOSHIBA,
1782 .dev_id = TC58FVB160,
1783 .name = "Toshiba TC58FVB160",
1784 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1785 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1786 .dev_size = SIZE_2MiB,
1787 .cmd_set = P_ID_AMD_STD,
1788 .nr_regions = 4,
1789 .regions = {
1790 ERASEINFO(0x04000,1),
1791 ERASEINFO(0x02000,2),
1792 ERASEINFO(0x08000,1),
1793 ERASEINFO(0x10000,31)
1794 }
1795 }, {
1796 .mfr_id = MANUFACTURER_TOSHIBA,
1797 .dev_id = TC58FVB321,
1798 .name = "Toshiba TC58FVB321",
1799 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1800 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1801 .dev_size = SIZE_4MiB,
1802 .cmd_set = P_ID_AMD_STD,
1803 .nr_regions = 2,
1804 .regions = {
1805 ERASEINFO(0x02000,8),
1806 ERASEINFO(0x10000,63)
1807 }
1808 }, {
1809 .mfr_id = MANUFACTURER_TOSHIBA,
1810 .dev_id = TC58FVT321,
1811 .name = "Toshiba TC58FVT321",
1812 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1813 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1814 .dev_size = SIZE_4MiB,
1815 .cmd_set = P_ID_AMD_STD,
1816 .nr_regions = 2,
1817 .regions = {
1818 ERASEINFO(0x10000,63),
1819 ERASEINFO(0x02000,8)
1820 }
1821 }, {
1822 .mfr_id = MANUFACTURER_TOSHIBA,
1823 .dev_id = TC58FVB641,
1824 .name = "Toshiba TC58FVB641",
1825 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1826 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1827 .dev_size = SIZE_8MiB,
1828 .cmd_set = P_ID_AMD_STD,
1829 .nr_regions = 2,
1830 .regions = {
1831 ERASEINFO(0x02000,8),
1832 ERASEINFO(0x10000,127)
1833 }
1834 }, {
1835 .mfr_id = MANUFACTURER_TOSHIBA,
1836 .dev_id = TC58FVT641,
1837 .name = "Toshiba TC58FVT641",
1838 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1839 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1840 .dev_size = SIZE_8MiB,
1841 .cmd_set = P_ID_AMD_STD,
1842 .nr_regions = 2,
1843 .regions = {
1844 ERASEINFO(0x10000,127),
1845 ERASEINFO(0x02000,8)
1846 }
1847 }, {
1848 .mfr_id = MANUFACTURER_WINBOND,
1849 .dev_id = W49V002A,
1850 .name = "Winbond W49V002A",
1851 .devtypes = CFI_DEVICETYPE_X8,
1852 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1853 .dev_size = SIZE_256KiB,
1854 .cmd_set = P_ID_AMD_STD,
1855 .nr_regions = 4,
1856 .regions = {
1857 ERASEINFO(0x10000, 3),
1858 ERASEINFO(0x08000, 1),
1859 ERASEINFO(0x02000, 2),
1860 ERASEINFO(0x04000, 1),
1861 }
1862 }
1863 };
1864
1865 static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base,
1866 struct cfi_private *cfi)
1867 {
1868 map_word result;
1869 unsigned long mask;
1870 int bank = 0;
1871
1872 /* According to JEDEC "Standard Manufacturer's Identification Code"
1873 * (http://www.jedec.org/download/search/jep106W.pdf)
1874 * several first banks can contain 0x7f instead of actual ID
1875 */
1876 do {
1877 uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi);
1878 mask = (1 << (cfi->device_type * 8)) - 1;
1879 result = map_read(map, base + ofs);
1880 bank++;
1881 } while ((result.x[0] & mask) == CONTINUATION_CODE);
1882
1883 return result.x[0] & mask;
1884 }
1885
1886 static inline u32 jedec_read_id(struct map_info *map, uint32_t base,
1887 struct cfi_private *cfi)
1888 {
1889 map_word result;
1890 unsigned long mask;
1891 u32 ofs = cfi_build_cmd_addr(1, map, cfi);
1892 mask = (1 << (cfi->device_type * 8)) -1;
1893 result = map_read(map, base + ofs);
1894 return result.x[0] & mask;
1895 }
1896
1897 static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)
1898 {
1899 /* Reset */
1900
1901 /* after checking the datasheets for SST, MACRONIX and ATMEL
1902 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset
1903 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at
1904 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
1905 * as they will ignore the writes and dont care what address
1906 * the F0 is written to */
1907 if (cfi->addr_unlock1) {
1908 DEBUG( MTD_DEBUG_LEVEL3,
1909 "reset unlock called %x %x \n",
1910 cfi->addr_unlock1,cfi->addr_unlock2);
1911 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1912 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
1913 }
1914
1915 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1916 /* Some misdesigned Intel chips do not respond for 0xF0 for a reset,
1917 * so ensure we're in read mode. Send both the Intel and the AMD command
1918 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
1919 * this should be safe.
1920 */
1921 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
1922 /* FIXME - should have reset delay before continuing */
1923 }
1924
1925
1926 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1927 {
1928 int i,num_erase_regions;
1929 uint8_t uaddr;
1930
1931 if (! (jedec_table[index].devtypes & p_cfi->device_type)) {
1932 DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n",
1933 jedec_table[index].name, 4 * (1<<p_cfi->device_type));
1934 return 0;
1935 }
1936
1937 printk(KERN_INFO "Found: %s\n",jedec_table[index].name);
1938
1939 num_erase_regions = jedec_table[index].nr_regions;
1940
1941 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
1942 if (!p_cfi->cfiq) {
1943 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
1944 return 0;
1945 }
1946
1947 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident));
1948
1949 p_cfi->cfiq->P_ID = jedec_table[index].cmd_set;
1950 p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions;
1951 p_cfi->cfiq->DevSize = jedec_table[index].dev_size;
1952 p_cfi->cfi_mode = CFI_MODE_JEDEC;
1953
1954 for (i=0; i<num_erase_regions; i++){
1955 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i];
1956 }
1957 p_cfi->cmdset_priv = NULL;
1958
1959 /* This may be redundant for some cases, but it doesn't hurt */
1960 p_cfi->mfr = jedec_table[index].mfr_id;
1961 p_cfi->id = jedec_table[index].dev_id;
1962
1963 uaddr = jedec_table[index].uaddr;
1964
1965 /* The table has unlock addresses in _bytes_, and we try not to let
1966 our brains explode when we see the datasheets talking about address
1967 lines numbered from A-1 to A18. The CFI table has unlock addresses
1968 in device-words according to the mode the device is connected in */
1969 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type;
1970 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type;
1971
1972 return 1; /* ok */
1973 }
1974
1975
1976 /*
1977 * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing
1978 * the mapped address, unlock addresses, and proper chip ID. This function
1979 * attempts to minimize errors. It is doubtfull that this probe will ever
1980 * be perfect - consequently there should be some module parameters that
1981 * could be manually specified to force the chip info.
1982 */
1983 static inline int jedec_match( uint32_t base,
1984 struct map_info *map,
1985 struct cfi_private *cfi,
1986 const struct amd_flash_info *finfo )
1987 {
1988 int rc = 0; /* failure until all tests pass */
1989 u32 mfr, id;
1990 uint8_t uaddr;
1991
1992 /*
1993 * The IDs must match. For X16 and X32 devices operating in
1994 * a lower width ( X8 or X16 ), the device ID's are usually just
1995 * the lower byte(s) of the larger device ID for wider mode. If
1996 * a part is found that doesn't fit this assumption (device id for
1997 * smaller width mode is completely unrealated to full-width mode)
1998 * then the jedec_table[] will have to be augmented with the IDs
1999 * for different widths.
2000 */
2001 switch (cfi->device_type) {
2002 case CFI_DEVICETYPE_X8:
2003 mfr = (uint8_t)finfo->mfr_id;
2004 id = (uint8_t)finfo->dev_id;
2005
2006 /* bjd: it seems that if we do this, we can end up
2007 * detecting 16bit flashes as an 8bit device, even though
2008 * there aren't.
2009 */
2010 if (finfo->dev_id > 0xff) {
2011 DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n",
2012 __func__);
2013 goto match_done;
2014 }
2015 break;
2016 case CFI_DEVICETYPE_X16:
2017 mfr = (uint16_t)finfo->mfr_id;
2018 id = (uint16_t)finfo->dev_id;
2019 break;
2020 case CFI_DEVICETYPE_X32:
2021 mfr = (uint16_t)finfo->mfr_id;
2022 id = (uint32_t)finfo->dev_id;
2023 break;
2024 default:
2025 printk(KERN_WARNING
2026 "MTD %s(): Unsupported device type %d\n",
2027 __func__, cfi->device_type);
2028 goto match_done;
2029 }
2030 if ( cfi->mfr != mfr || cfi->id != id ) {
2031 goto match_done;
2032 }
2033
2034 /* the part size must fit in the memory window */
2035 DEBUG( MTD_DEBUG_LEVEL3,
2036 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
2037 __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) );
2038 if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) {
2039 DEBUG( MTD_DEBUG_LEVEL3,
2040 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
2041 __func__, finfo->mfr_id, finfo->dev_id,
2042 1 << finfo->dev_size );
2043 goto match_done;
2044 }
2045
2046 if (! (finfo->devtypes & cfi->device_type))
2047 goto match_done;
2048
2049 uaddr = finfo->uaddr;
2050
2051 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
2052 __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
2053 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
2054 && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 ||
2055 unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) {
2056 DEBUG( MTD_DEBUG_LEVEL3,
2057 "MTD %s(): 0x%.4x 0x%.4x did not match\n",
2058 __func__,
2059 unlock_addrs[uaddr].addr1,
2060 unlock_addrs[uaddr].addr2);
2061 goto match_done;
2062 }
2063
2064 /*
2065 * Make sure the ID's dissappear when the device is taken out of
2066 * ID mode. The only time this should fail when it should succeed
2067 * is when the ID's are written as data to the same
2068 * addresses. For this rare and unfortunate case the chip
2069 * cannot be probed correctly.
2070 * FIXME - write a driver that takes all of the chip info as
2071 * module parameters, doesn't probe but forces a load.
2072 */
2073 DEBUG( MTD_DEBUG_LEVEL3,
2074 "MTD %s(): check ID's disappear when not in ID mode\n",
2075 __func__ );
2076 jedec_reset( base, map, cfi );
2077 mfr = jedec_read_mfr( map, base, cfi );
2078 id = jedec_read_id( map, base, cfi );
2079 if ( mfr == cfi->mfr && id == cfi->id ) {
2080 DEBUG( MTD_DEBUG_LEVEL3,
2081 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n"
2082 "You might need to manually specify JEDEC parameters.\n",
2083 __func__, cfi->mfr, cfi->id );
2084 goto match_done;
2085 }
2086
2087 /* all tests passed - mark as success */
2088 rc = 1;
2089
2090 /*
2091 * Put the device back in ID mode - only need to do this if we
2092 * were truly frobbing a real device.
2093 */
2094 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ );
2095 if (cfi->addr_unlock1) {
2096 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2097 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
2098 }
2099 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2100 /* FIXME - should have a delay before continuing */
2101
2102 match_done:
2103 return rc;
2104 }
2105
2106
2107 static int jedec_probe_chip(struct map_info *map, __u32 base,
2108 unsigned long *chip_map, struct cfi_private *cfi)
2109 {
2110 int i;
2111 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
2112 u32 probe_offset1, probe_offset2;
2113
2114 retry:
2115 if (!cfi->numchips) {
2116 uaddr_idx++;
2117
2118 if (MTD_UADDR_UNNECESSARY == uaddr_idx)
2119 return 0;
2120
2121 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type;
2122 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type;
2123 }
2124
2125 /* Make certain we aren't probing past the end of map */
2126 if (base >= map->size) {
2127 printk(KERN_NOTICE
2128 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n",
2129 base, map->size -1);
2130 return 0;
2131
2132 }
2133 /* Ensure the unlock addresses we try stay inside the map */
2134 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi);
2135 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi);
2136 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
2137 ((base + probe_offset2 + map_bankwidth(map)) >= map->size))
2138 goto retry;
2139
2140 /* Reset */
2141 jedec_reset(base, map, cfi);
2142
2143 /* Autoselect Mode */
2144 if(cfi->addr_unlock1) {
2145 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2146 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
2147 }
2148 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2149 /* FIXME - should have a delay before continuing */
2150
2151 if (!cfi->numchips) {
2152 /* This is the first time we're called. Set up the CFI
2153 stuff accordingly and return */
2154
2155 cfi->mfr = jedec_read_mfr(map, base, cfi);
2156 cfi->id = jedec_read_id(map, base, cfi);
2157 DEBUG(MTD_DEBUG_LEVEL3,
2158 "Search for id:(%02x %02x) interleave(%d) type(%d)\n",
2159 cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type);
2160 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
2161 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) {
2162 DEBUG( MTD_DEBUG_LEVEL3,
2163 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n",
2164 __func__, cfi->mfr, cfi->id,
2165 cfi->addr_unlock1, cfi->addr_unlock2 );
2166 if (!cfi_jedec_setup(cfi, i))
2167 return 0;
2168 goto ok_out;
2169 }
2170 }
2171 goto retry;
2172 } else {
2173 uint16_t mfr;
2174 uint16_t id;
2175
2176 /* Make sure it is a chip of the same manufacturer and id */
2177 mfr = jedec_read_mfr(map, base, cfi);
2178 id = jedec_read_id(map, base, cfi);
2179
2180 if ((mfr != cfi->mfr) || (id != cfi->id)) {
2181 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n",
2182 map->name, mfr, id, base);
2183 jedec_reset(base, map, cfi);
2184 return 0;
2185 }
2186 }
2187
2188 /* Check each previous chip locations to see if it's an alias */
2189 for (i=0; i < (base >> cfi->chipshift); i++) {
2190 unsigned long start;
2191 if(!test_bit(i, chip_map)) {
2192 continue; /* Skip location; no valid chip at this address */
2193 }
2194 start = i << cfi->chipshift;
2195 if (jedec_read_mfr(map, start, cfi) == cfi->mfr &&
2196 jedec_read_id(map, start, cfi) == cfi->id) {
2197 /* Eep. This chip also looks like it's in autoselect mode.
2198 Is it an alias for the new one? */
2199 jedec_reset(start, map, cfi);
2200
2201 /* If the device IDs go away, it's an alias */
2202 if (jedec_read_mfr(map, base, cfi) != cfi->mfr ||
2203 jedec_read_id(map, base, cfi) != cfi->id) {
2204 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2205 map->name, base, start);
2206 return 0;
2207 }
2208
2209 /* Yes, it's actually got the device IDs as data. Most
2210 * unfortunate. Stick the new chip in read mode
2211 * too and if it's the same, assume it's an alias. */
2212 /* FIXME: Use other modes to do a proper check */
2213 jedec_reset(base, map, cfi);
2214 if (jedec_read_mfr(map, base, cfi) == cfi->mfr &&
2215 jedec_read_id(map, base, cfi) == cfi->id) {
2216 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2217 map->name, base, start);
2218 return 0;
2219 }
2220 }
2221 }
2222
2223 /* OK, if we got to here, then none of the previous chips appear to
2224 be aliases for the current one. */
2225 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
2226 cfi->numchips++;
2227
2228 ok_out:
2229 /* Put it back into Read Mode */
2230 jedec_reset(base, map, cfi);
2231
2232 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
2233 map->name, cfi_interleave(cfi), cfi->device_type*8, base,
2234 map->bankwidth*8);
2235
2236 return 1;
2237 }
2238
2239 static struct chip_probe jedec_chip_probe = {
2240 .name = "JEDEC",
2241 .probe_chip = jedec_probe_chip
2242 };
2243
2244 static struct mtd_info *jedec_probe(struct map_info *map)
2245 {
2246 /*
2247 * Just use the generic probe stuff to call our CFI-specific
2248 * chip_probe routine in all the possible permutations, etc.
2249 */
2250 return mtd_do_chip_probe(map, &jedec_chip_probe);
2251 }
2252
2253 static struct mtd_chip_driver jedec_chipdrv = {
2254 .probe = jedec_probe,
2255 .name = "jedec_probe",
2256 .module = THIS_MODULE
2257 };
2258
2259 static int __init jedec_probe_init(void)
2260 {
2261 register_mtd_chip_driver(&jedec_chipdrv);
2262 return 0;
2263 }
2264
2265 static void __exit jedec_probe_exit(void)
2266 {
2267 unregister_mtd_chip_driver(&jedec_chipdrv);
2268 }
2269
2270 module_init(jedec_probe_init);
2271 module_exit(jedec_probe_exit);
2272
2273 MODULE_LICENSE("GPL");
2274 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al.");
2275 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips");
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