2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
27 #include <linux/slab.h>
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
42 static void nouveau_stub_takedown(struct drm_device
*dev
) {}
43 static int nouveau_stub_init(struct drm_device
*dev
) { return 0; }
45 static int nouveau_init_engine_ptrs(struct drm_device
*dev
)
47 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
48 struct nouveau_engine
*engine
= &dev_priv
->engine
;
50 switch (dev_priv
->chipset
& 0xf0) {
52 engine
->instmem
.init
= nv04_instmem_init
;
53 engine
->instmem
.takedown
= nv04_instmem_takedown
;
54 engine
->instmem
.suspend
= nv04_instmem_suspend
;
55 engine
->instmem
.resume
= nv04_instmem_resume
;
56 engine
->instmem
.populate
= nv04_instmem_populate
;
57 engine
->instmem
.clear
= nv04_instmem_clear
;
58 engine
->instmem
.bind
= nv04_instmem_bind
;
59 engine
->instmem
.unbind
= nv04_instmem_unbind
;
60 engine
->instmem
.flush
= nv04_instmem_flush
;
61 engine
->mc
.init
= nv04_mc_init
;
62 engine
->mc
.takedown
= nv04_mc_takedown
;
63 engine
->timer
.init
= nv04_timer_init
;
64 engine
->timer
.read
= nv04_timer_read
;
65 engine
->timer
.takedown
= nv04_timer_takedown
;
66 engine
->fb
.init
= nv04_fb_init
;
67 engine
->fb
.takedown
= nv04_fb_takedown
;
68 engine
->graph
.grclass
= nv04_graph_grclass
;
69 engine
->graph
.init
= nv04_graph_init
;
70 engine
->graph
.takedown
= nv04_graph_takedown
;
71 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
72 engine
->graph
.channel
= nv04_graph_channel
;
73 engine
->graph
.create_context
= nv04_graph_create_context
;
74 engine
->graph
.destroy_context
= nv04_graph_destroy_context
;
75 engine
->graph
.load_context
= nv04_graph_load_context
;
76 engine
->graph
.unload_context
= nv04_graph_unload_context
;
77 engine
->fifo
.channels
= 16;
78 engine
->fifo
.init
= nv04_fifo_init
;
79 engine
->fifo
.takedown
= nouveau_stub_takedown
;
80 engine
->fifo
.disable
= nv04_fifo_disable
;
81 engine
->fifo
.enable
= nv04_fifo_enable
;
82 engine
->fifo
.reassign
= nv04_fifo_reassign
;
83 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
84 engine
->fifo
.channel_id
= nv04_fifo_channel_id
;
85 engine
->fifo
.create_context
= nv04_fifo_create_context
;
86 engine
->fifo
.destroy_context
= nv04_fifo_destroy_context
;
87 engine
->fifo
.load_context
= nv04_fifo_load_context
;
88 engine
->fifo
.unload_context
= nv04_fifo_unload_context
;
89 engine
->display
.early_init
= nv04_display_early_init
;
90 engine
->display
.late_takedown
= nv04_display_late_takedown
;
91 engine
->display
.create
= nv04_display_create
;
92 engine
->display
.init
= nv04_display_init
;
93 engine
->display
.destroy
= nv04_display_destroy
;
94 engine
->gpio
.init
= nouveau_stub_init
;
95 engine
->gpio
.takedown
= nouveau_stub_takedown
;
96 engine
->gpio
.get
= NULL
;
97 engine
->gpio
.set
= NULL
;
98 engine
->gpio
.irq_enable
= NULL
;
99 engine
->pm
.clock_get
= nv04_pm_clock_get
;
100 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
101 engine
->pm
.clock_set
= nv04_pm_clock_set
;
104 engine
->instmem
.init
= nv04_instmem_init
;
105 engine
->instmem
.takedown
= nv04_instmem_takedown
;
106 engine
->instmem
.suspend
= nv04_instmem_suspend
;
107 engine
->instmem
.resume
= nv04_instmem_resume
;
108 engine
->instmem
.populate
= nv04_instmem_populate
;
109 engine
->instmem
.clear
= nv04_instmem_clear
;
110 engine
->instmem
.bind
= nv04_instmem_bind
;
111 engine
->instmem
.unbind
= nv04_instmem_unbind
;
112 engine
->instmem
.flush
= nv04_instmem_flush
;
113 engine
->mc
.init
= nv04_mc_init
;
114 engine
->mc
.takedown
= nv04_mc_takedown
;
115 engine
->timer
.init
= nv04_timer_init
;
116 engine
->timer
.read
= nv04_timer_read
;
117 engine
->timer
.takedown
= nv04_timer_takedown
;
118 engine
->fb
.init
= nv10_fb_init
;
119 engine
->fb
.takedown
= nv10_fb_takedown
;
120 engine
->fb
.set_region_tiling
= nv10_fb_set_region_tiling
;
121 engine
->graph
.grclass
= nv10_graph_grclass
;
122 engine
->graph
.init
= nv10_graph_init
;
123 engine
->graph
.takedown
= nv10_graph_takedown
;
124 engine
->graph
.channel
= nv10_graph_channel
;
125 engine
->graph
.create_context
= nv10_graph_create_context
;
126 engine
->graph
.destroy_context
= nv10_graph_destroy_context
;
127 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
128 engine
->graph
.load_context
= nv10_graph_load_context
;
129 engine
->graph
.unload_context
= nv10_graph_unload_context
;
130 engine
->graph
.set_region_tiling
= nv10_graph_set_region_tiling
;
131 engine
->fifo
.channels
= 32;
132 engine
->fifo
.init
= nv10_fifo_init
;
133 engine
->fifo
.takedown
= nouveau_stub_takedown
;
134 engine
->fifo
.disable
= nv04_fifo_disable
;
135 engine
->fifo
.enable
= nv04_fifo_enable
;
136 engine
->fifo
.reassign
= nv04_fifo_reassign
;
137 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
138 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
139 engine
->fifo
.create_context
= nv10_fifo_create_context
;
140 engine
->fifo
.destroy_context
= nv10_fifo_destroy_context
;
141 engine
->fifo
.load_context
= nv10_fifo_load_context
;
142 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
143 engine
->display
.early_init
= nv04_display_early_init
;
144 engine
->display
.late_takedown
= nv04_display_late_takedown
;
145 engine
->display
.create
= nv04_display_create
;
146 engine
->display
.init
= nv04_display_init
;
147 engine
->display
.destroy
= nv04_display_destroy
;
148 engine
->gpio
.init
= nouveau_stub_init
;
149 engine
->gpio
.takedown
= nouveau_stub_takedown
;
150 engine
->gpio
.get
= nv10_gpio_get
;
151 engine
->gpio
.set
= nv10_gpio_set
;
152 engine
->gpio
.irq_enable
= NULL
;
153 engine
->pm
.clock_get
= nv04_pm_clock_get
;
154 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
155 engine
->pm
.clock_set
= nv04_pm_clock_set
;
158 engine
->instmem
.init
= nv04_instmem_init
;
159 engine
->instmem
.takedown
= nv04_instmem_takedown
;
160 engine
->instmem
.suspend
= nv04_instmem_suspend
;
161 engine
->instmem
.resume
= nv04_instmem_resume
;
162 engine
->instmem
.populate
= nv04_instmem_populate
;
163 engine
->instmem
.clear
= nv04_instmem_clear
;
164 engine
->instmem
.bind
= nv04_instmem_bind
;
165 engine
->instmem
.unbind
= nv04_instmem_unbind
;
166 engine
->instmem
.flush
= nv04_instmem_flush
;
167 engine
->mc
.init
= nv04_mc_init
;
168 engine
->mc
.takedown
= nv04_mc_takedown
;
169 engine
->timer
.init
= nv04_timer_init
;
170 engine
->timer
.read
= nv04_timer_read
;
171 engine
->timer
.takedown
= nv04_timer_takedown
;
172 engine
->fb
.init
= nv10_fb_init
;
173 engine
->fb
.takedown
= nv10_fb_takedown
;
174 engine
->fb
.set_region_tiling
= nv10_fb_set_region_tiling
;
175 engine
->graph
.grclass
= nv20_graph_grclass
;
176 engine
->graph
.init
= nv20_graph_init
;
177 engine
->graph
.takedown
= nv20_graph_takedown
;
178 engine
->graph
.channel
= nv10_graph_channel
;
179 engine
->graph
.create_context
= nv20_graph_create_context
;
180 engine
->graph
.destroy_context
= nv20_graph_destroy_context
;
181 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
182 engine
->graph
.load_context
= nv20_graph_load_context
;
183 engine
->graph
.unload_context
= nv20_graph_unload_context
;
184 engine
->graph
.set_region_tiling
= nv20_graph_set_region_tiling
;
185 engine
->fifo
.channels
= 32;
186 engine
->fifo
.init
= nv10_fifo_init
;
187 engine
->fifo
.takedown
= nouveau_stub_takedown
;
188 engine
->fifo
.disable
= nv04_fifo_disable
;
189 engine
->fifo
.enable
= nv04_fifo_enable
;
190 engine
->fifo
.reassign
= nv04_fifo_reassign
;
191 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
192 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
193 engine
->fifo
.create_context
= nv10_fifo_create_context
;
194 engine
->fifo
.destroy_context
= nv10_fifo_destroy_context
;
195 engine
->fifo
.load_context
= nv10_fifo_load_context
;
196 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
197 engine
->display
.early_init
= nv04_display_early_init
;
198 engine
->display
.late_takedown
= nv04_display_late_takedown
;
199 engine
->display
.create
= nv04_display_create
;
200 engine
->display
.init
= nv04_display_init
;
201 engine
->display
.destroy
= nv04_display_destroy
;
202 engine
->gpio
.init
= nouveau_stub_init
;
203 engine
->gpio
.takedown
= nouveau_stub_takedown
;
204 engine
->gpio
.get
= nv10_gpio_get
;
205 engine
->gpio
.set
= nv10_gpio_set
;
206 engine
->gpio
.irq_enable
= NULL
;
207 engine
->pm
.clock_get
= nv04_pm_clock_get
;
208 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
209 engine
->pm
.clock_set
= nv04_pm_clock_set
;
212 engine
->instmem
.init
= nv04_instmem_init
;
213 engine
->instmem
.takedown
= nv04_instmem_takedown
;
214 engine
->instmem
.suspend
= nv04_instmem_suspend
;
215 engine
->instmem
.resume
= nv04_instmem_resume
;
216 engine
->instmem
.populate
= nv04_instmem_populate
;
217 engine
->instmem
.clear
= nv04_instmem_clear
;
218 engine
->instmem
.bind
= nv04_instmem_bind
;
219 engine
->instmem
.unbind
= nv04_instmem_unbind
;
220 engine
->instmem
.flush
= nv04_instmem_flush
;
221 engine
->mc
.init
= nv04_mc_init
;
222 engine
->mc
.takedown
= nv04_mc_takedown
;
223 engine
->timer
.init
= nv04_timer_init
;
224 engine
->timer
.read
= nv04_timer_read
;
225 engine
->timer
.takedown
= nv04_timer_takedown
;
226 engine
->fb
.init
= nv30_fb_init
;
227 engine
->fb
.takedown
= nv30_fb_takedown
;
228 engine
->fb
.set_region_tiling
= nv10_fb_set_region_tiling
;
229 engine
->graph
.grclass
= nv30_graph_grclass
;
230 engine
->graph
.init
= nv30_graph_init
;
231 engine
->graph
.takedown
= nv20_graph_takedown
;
232 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
233 engine
->graph
.channel
= nv10_graph_channel
;
234 engine
->graph
.create_context
= nv20_graph_create_context
;
235 engine
->graph
.destroy_context
= nv20_graph_destroy_context
;
236 engine
->graph
.load_context
= nv20_graph_load_context
;
237 engine
->graph
.unload_context
= nv20_graph_unload_context
;
238 engine
->graph
.set_region_tiling
= nv20_graph_set_region_tiling
;
239 engine
->fifo
.channels
= 32;
240 engine
->fifo
.init
= nv10_fifo_init
;
241 engine
->fifo
.takedown
= nouveau_stub_takedown
;
242 engine
->fifo
.disable
= nv04_fifo_disable
;
243 engine
->fifo
.enable
= nv04_fifo_enable
;
244 engine
->fifo
.reassign
= nv04_fifo_reassign
;
245 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
246 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
247 engine
->fifo
.create_context
= nv10_fifo_create_context
;
248 engine
->fifo
.destroy_context
= nv10_fifo_destroy_context
;
249 engine
->fifo
.load_context
= nv10_fifo_load_context
;
250 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
251 engine
->display
.early_init
= nv04_display_early_init
;
252 engine
->display
.late_takedown
= nv04_display_late_takedown
;
253 engine
->display
.create
= nv04_display_create
;
254 engine
->display
.init
= nv04_display_init
;
255 engine
->display
.destroy
= nv04_display_destroy
;
256 engine
->gpio
.init
= nouveau_stub_init
;
257 engine
->gpio
.takedown
= nouveau_stub_takedown
;
258 engine
->gpio
.get
= nv10_gpio_get
;
259 engine
->gpio
.set
= nv10_gpio_set
;
260 engine
->gpio
.irq_enable
= NULL
;
261 engine
->pm
.clock_get
= nv04_pm_clock_get
;
262 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
263 engine
->pm
.clock_set
= nv04_pm_clock_set
;
264 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
265 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
269 engine
->instmem
.init
= nv04_instmem_init
;
270 engine
->instmem
.takedown
= nv04_instmem_takedown
;
271 engine
->instmem
.suspend
= nv04_instmem_suspend
;
272 engine
->instmem
.resume
= nv04_instmem_resume
;
273 engine
->instmem
.populate
= nv04_instmem_populate
;
274 engine
->instmem
.clear
= nv04_instmem_clear
;
275 engine
->instmem
.bind
= nv04_instmem_bind
;
276 engine
->instmem
.unbind
= nv04_instmem_unbind
;
277 engine
->instmem
.flush
= nv04_instmem_flush
;
278 engine
->mc
.init
= nv40_mc_init
;
279 engine
->mc
.takedown
= nv40_mc_takedown
;
280 engine
->timer
.init
= nv04_timer_init
;
281 engine
->timer
.read
= nv04_timer_read
;
282 engine
->timer
.takedown
= nv04_timer_takedown
;
283 engine
->fb
.init
= nv40_fb_init
;
284 engine
->fb
.takedown
= nv40_fb_takedown
;
285 engine
->fb
.set_region_tiling
= nv40_fb_set_region_tiling
;
286 engine
->graph
.grclass
= nv40_graph_grclass
;
287 engine
->graph
.init
= nv40_graph_init
;
288 engine
->graph
.takedown
= nv40_graph_takedown
;
289 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
290 engine
->graph
.channel
= nv40_graph_channel
;
291 engine
->graph
.create_context
= nv40_graph_create_context
;
292 engine
->graph
.destroy_context
= nv40_graph_destroy_context
;
293 engine
->graph
.load_context
= nv40_graph_load_context
;
294 engine
->graph
.unload_context
= nv40_graph_unload_context
;
295 engine
->graph
.set_region_tiling
= nv40_graph_set_region_tiling
;
296 engine
->fifo
.channels
= 32;
297 engine
->fifo
.init
= nv40_fifo_init
;
298 engine
->fifo
.takedown
= nouveau_stub_takedown
;
299 engine
->fifo
.disable
= nv04_fifo_disable
;
300 engine
->fifo
.enable
= nv04_fifo_enable
;
301 engine
->fifo
.reassign
= nv04_fifo_reassign
;
302 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
303 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
304 engine
->fifo
.create_context
= nv40_fifo_create_context
;
305 engine
->fifo
.destroy_context
= nv40_fifo_destroy_context
;
306 engine
->fifo
.load_context
= nv40_fifo_load_context
;
307 engine
->fifo
.unload_context
= nv40_fifo_unload_context
;
308 engine
->display
.early_init
= nv04_display_early_init
;
309 engine
->display
.late_takedown
= nv04_display_late_takedown
;
310 engine
->display
.create
= nv04_display_create
;
311 engine
->display
.init
= nv04_display_init
;
312 engine
->display
.destroy
= nv04_display_destroy
;
313 engine
->gpio
.init
= nouveau_stub_init
;
314 engine
->gpio
.takedown
= nouveau_stub_takedown
;
315 engine
->gpio
.get
= nv10_gpio_get
;
316 engine
->gpio
.set
= nv10_gpio_set
;
317 engine
->gpio
.irq_enable
= NULL
;
318 engine
->pm
.clock_get
= nv04_pm_clock_get
;
319 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
320 engine
->pm
.clock_set
= nv04_pm_clock_set
;
321 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
322 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
323 engine
->pm
.temp_get
= nv40_temp_get
;
326 case 0x80: /* gotta love NVIDIA's consistency.. */
329 engine
->instmem
.init
= nv50_instmem_init
;
330 engine
->instmem
.takedown
= nv50_instmem_takedown
;
331 engine
->instmem
.suspend
= nv50_instmem_suspend
;
332 engine
->instmem
.resume
= nv50_instmem_resume
;
333 engine
->instmem
.populate
= nv50_instmem_populate
;
334 engine
->instmem
.clear
= nv50_instmem_clear
;
335 engine
->instmem
.bind
= nv50_instmem_bind
;
336 engine
->instmem
.unbind
= nv50_instmem_unbind
;
337 if (dev_priv
->chipset
== 0x50)
338 engine
->instmem
.flush
= nv50_instmem_flush
;
340 engine
->instmem
.flush
= nv84_instmem_flush
;
341 engine
->mc
.init
= nv50_mc_init
;
342 engine
->mc
.takedown
= nv50_mc_takedown
;
343 engine
->timer
.init
= nv04_timer_init
;
344 engine
->timer
.read
= nv04_timer_read
;
345 engine
->timer
.takedown
= nv04_timer_takedown
;
346 engine
->fb
.init
= nv50_fb_init
;
347 engine
->fb
.takedown
= nv50_fb_takedown
;
348 engine
->graph
.grclass
= nv50_graph_grclass
;
349 engine
->graph
.init
= nv50_graph_init
;
350 engine
->graph
.takedown
= nv50_graph_takedown
;
351 engine
->graph
.fifo_access
= nv50_graph_fifo_access
;
352 engine
->graph
.channel
= nv50_graph_channel
;
353 engine
->graph
.create_context
= nv50_graph_create_context
;
354 engine
->graph
.destroy_context
= nv50_graph_destroy_context
;
355 engine
->graph
.load_context
= nv50_graph_load_context
;
356 engine
->graph
.unload_context
= nv50_graph_unload_context
;
357 engine
->fifo
.channels
= 128;
358 engine
->fifo
.init
= nv50_fifo_init
;
359 engine
->fifo
.takedown
= nv50_fifo_takedown
;
360 engine
->fifo
.disable
= nv04_fifo_disable
;
361 engine
->fifo
.enable
= nv04_fifo_enable
;
362 engine
->fifo
.reassign
= nv04_fifo_reassign
;
363 engine
->fifo
.channel_id
= nv50_fifo_channel_id
;
364 engine
->fifo
.create_context
= nv50_fifo_create_context
;
365 engine
->fifo
.destroy_context
= nv50_fifo_destroy_context
;
366 engine
->fifo
.load_context
= nv50_fifo_load_context
;
367 engine
->fifo
.unload_context
= nv50_fifo_unload_context
;
368 engine
->display
.early_init
= nv50_display_early_init
;
369 engine
->display
.late_takedown
= nv50_display_late_takedown
;
370 engine
->display
.create
= nv50_display_create
;
371 engine
->display
.init
= nv50_display_init
;
372 engine
->display
.destroy
= nv50_display_destroy
;
373 engine
->gpio
.init
= nv50_gpio_init
;
374 engine
->gpio
.takedown
= nouveau_stub_takedown
;
375 engine
->gpio
.get
= nv50_gpio_get
;
376 engine
->gpio
.set
= nv50_gpio_set
;
377 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
378 switch (dev_priv
->chipset
) {
383 engine
->pm
.clock_get
= nva3_pm_clock_get
;
384 engine
->pm
.clock_pre
= nva3_pm_clock_pre
;
385 engine
->pm
.clock_set
= nva3_pm_clock_set
;
388 engine
->pm
.clock_get
= nv50_pm_clock_get
;
389 engine
->pm
.clock_pre
= nv50_pm_clock_pre
;
390 engine
->pm
.clock_set
= nv50_pm_clock_set
;
393 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
394 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
395 if (dev_priv
->chipset
>= 0x84)
396 engine
->pm
.temp_get
= nv84_temp_get
;
398 engine
->pm
.temp_get
= nv40_temp_get
;
401 engine
->instmem
.init
= nvc0_instmem_init
;
402 engine
->instmem
.takedown
= nvc0_instmem_takedown
;
403 engine
->instmem
.suspend
= nvc0_instmem_suspend
;
404 engine
->instmem
.resume
= nvc0_instmem_resume
;
405 engine
->instmem
.populate
= nvc0_instmem_populate
;
406 engine
->instmem
.clear
= nvc0_instmem_clear
;
407 engine
->instmem
.bind
= nvc0_instmem_bind
;
408 engine
->instmem
.unbind
= nvc0_instmem_unbind
;
409 engine
->instmem
.flush
= nvc0_instmem_flush
;
410 engine
->mc
.init
= nv50_mc_init
;
411 engine
->mc
.takedown
= nv50_mc_takedown
;
412 engine
->timer
.init
= nv04_timer_init
;
413 engine
->timer
.read
= nv04_timer_read
;
414 engine
->timer
.takedown
= nv04_timer_takedown
;
415 engine
->fb
.init
= nvc0_fb_init
;
416 engine
->fb
.takedown
= nvc0_fb_takedown
;
417 engine
->graph
.grclass
= NULL
; //nvc0_graph_grclass;
418 engine
->graph
.init
= nvc0_graph_init
;
419 engine
->graph
.takedown
= nvc0_graph_takedown
;
420 engine
->graph
.fifo_access
= nvc0_graph_fifo_access
;
421 engine
->graph
.channel
= nvc0_graph_channel
;
422 engine
->graph
.create_context
= nvc0_graph_create_context
;
423 engine
->graph
.destroy_context
= nvc0_graph_destroy_context
;
424 engine
->graph
.load_context
= nvc0_graph_load_context
;
425 engine
->graph
.unload_context
= nvc0_graph_unload_context
;
426 engine
->fifo
.channels
= 128;
427 engine
->fifo
.init
= nvc0_fifo_init
;
428 engine
->fifo
.takedown
= nvc0_fifo_takedown
;
429 engine
->fifo
.disable
= nvc0_fifo_disable
;
430 engine
->fifo
.enable
= nvc0_fifo_enable
;
431 engine
->fifo
.reassign
= nvc0_fifo_reassign
;
432 engine
->fifo
.channel_id
= nvc0_fifo_channel_id
;
433 engine
->fifo
.create_context
= nvc0_fifo_create_context
;
434 engine
->fifo
.destroy_context
= nvc0_fifo_destroy_context
;
435 engine
->fifo
.load_context
= nvc0_fifo_load_context
;
436 engine
->fifo
.unload_context
= nvc0_fifo_unload_context
;
437 engine
->display
.early_init
= nv50_display_early_init
;
438 engine
->display
.late_takedown
= nv50_display_late_takedown
;
439 engine
->display
.create
= nv50_display_create
;
440 engine
->display
.init
= nv50_display_init
;
441 engine
->display
.destroy
= nv50_display_destroy
;
442 engine
->gpio
.init
= nv50_gpio_init
;
443 engine
->gpio
.takedown
= nouveau_stub_takedown
;
444 engine
->gpio
.get
= nv50_gpio_get
;
445 engine
->gpio
.set
= nv50_gpio_set
;
446 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
449 NV_ERROR(dev
, "NV%02x unsupported\n", dev_priv
->chipset
);
457 nouveau_vga_set_decode(void *priv
, bool state
)
459 struct drm_device
*dev
= priv
;
460 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
462 if (dev_priv
->chipset
>= 0x40)
463 nv_wr32(dev
, 0x88054, state
);
465 nv_wr32(dev
, 0x1854, state
);
468 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
469 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
471 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
475 nouveau_card_init_channel(struct drm_device
*dev
)
477 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
478 struct nouveau_gpuobj
*gpuobj
= NULL
;
481 ret
= nouveau_channel_alloc(dev
, &dev_priv
->channel
,
482 (struct drm_file
*)-2, NvDmaFB
, NvDmaTT
);
486 ret
= nouveau_gpuobj_dma_new(dev_priv
->channel
, NV_CLASS_DMA_IN_MEMORY
,
487 0, dev_priv
->vram_size
,
488 NV_DMA_ACCESS_RW
, NV_DMA_TARGET_VIDMEM
,
493 ret
= nouveau_ramht_insert(dev_priv
->channel
, NvDmaVRAM
, gpuobj
);
494 nouveau_gpuobj_ref(NULL
, &gpuobj
);
498 ret
= nouveau_gpuobj_gart_dma_new(dev_priv
->channel
, 0,
499 dev_priv
->gart_info
.aper_size
,
500 NV_DMA_ACCESS_RW
, &gpuobj
, NULL
);
504 ret
= nouveau_ramht_insert(dev_priv
->channel
, NvDmaGART
, gpuobj
);
505 nouveau_gpuobj_ref(NULL
, &gpuobj
);
512 nouveau_channel_free(dev_priv
->channel
);
513 dev_priv
->channel
= NULL
;
517 static void nouveau_switcheroo_set_state(struct pci_dev
*pdev
,
518 enum vga_switcheroo_state state
)
520 struct drm_device
*dev
= pci_get_drvdata(pdev
);
521 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
522 if (state
== VGA_SWITCHEROO_ON
) {
523 printk(KERN_ERR
"VGA switcheroo: switched nouveau on\n");
524 nouveau_pci_resume(pdev
);
525 drm_kms_helper_poll_enable(dev
);
527 printk(KERN_ERR
"VGA switcheroo: switched nouveau off\n");
528 drm_kms_helper_poll_disable(dev
);
529 nouveau_pci_suspend(pdev
, pmm
);
533 static bool nouveau_switcheroo_can_switch(struct pci_dev
*pdev
)
535 struct drm_device
*dev
= pci_get_drvdata(pdev
);
538 spin_lock(&dev
->count_lock
);
539 can_switch
= (dev
->open_count
== 0);
540 spin_unlock(&dev
->count_lock
);
545 nouveau_card_init(struct drm_device
*dev
)
547 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
548 struct nouveau_engine
*engine
;
551 vga_client_register(dev
->pdev
, dev
, NULL
, nouveau_vga_set_decode
);
552 vga_switcheroo_register_client(dev
->pdev
, nouveau_switcheroo_set_state
,
553 nouveau_switcheroo_can_switch
);
555 /* Initialise internal driver API hooks */
556 ret
= nouveau_init_engine_ptrs(dev
);
559 engine
= &dev_priv
->engine
;
560 spin_lock_init(&dev_priv
->context_switch_lock
);
562 /* Make the CRTCs and I2C buses accessible */
563 ret
= engine
->display
.early_init(dev
);
567 /* Parse BIOS tables / Run init tables if card not POSTed */
568 ret
= nouveau_bios_init(dev
);
570 goto out_display_early
;
572 nouveau_pm_init(dev
);
574 ret
= nouveau_mem_vram_init(dev
);
578 ret
= nouveau_gpuobj_init(dev
);
582 ret
= engine
->instmem
.init(dev
);
586 ret
= nouveau_mem_gart_init(dev
);
591 ret
= engine
->mc
.init(dev
);
596 ret
= engine
->gpio
.init(dev
);
601 ret
= engine
->timer
.init(dev
);
606 ret
= engine
->fb
.init(dev
);
611 engine
->graph
.accel_blocked
= true;
614 ret
= engine
->graph
.init(dev
);
619 ret
= engine
->fifo
.init(dev
);
624 ret
= engine
->display
.create(dev
);
628 /* this call irq_preinstall, register irq handler and
629 * call irq_postinstall
631 ret
= drm_irq_install(dev
);
635 ret
= drm_vblank_init(dev
, 0);
639 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
641 if (!engine
->graph
.accel_blocked
) {
642 ret
= nouveau_card_init_channel(dev
);
647 ret
= nouveau_backlight_init(dev
);
649 NV_ERROR(dev
, "Error %d registering backlight\n", ret
);
651 nouveau_fbcon_init(dev
);
652 drm_kms_helper_poll_init(dev
);
656 drm_irq_uninstall(dev
);
658 engine
->display
.destroy(dev
);
660 if (!nouveau_noaccel
)
661 engine
->fifo
.takedown(dev
);
663 if (!nouveau_noaccel
)
664 engine
->graph
.takedown(dev
);
666 engine
->fb
.takedown(dev
);
668 engine
->timer
.takedown(dev
);
670 engine
->gpio
.takedown(dev
);
672 engine
->mc
.takedown(dev
);
674 nouveau_mem_gart_fini(dev
);
676 engine
->instmem
.takedown(dev
);
678 nouveau_gpuobj_takedown(dev
);
680 nouveau_mem_vram_fini(dev
);
682 nouveau_pm_fini(dev
);
683 nouveau_bios_takedown(dev
);
685 engine
->display
.late_takedown(dev
);
687 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
691 static void nouveau_card_takedown(struct drm_device
*dev
)
693 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
694 struct nouveau_engine
*engine
= &dev_priv
->engine
;
696 nouveau_backlight_exit(dev
);
698 if (dev_priv
->channel
) {
699 nouveau_channel_free(dev_priv
->channel
);
700 dev_priv
->channel
= NULL
;
703 if (!nouveau_noaccel
) {
704 engine
->fifo
.takedown(dev
);
705 engine
->graph
.takedown(dev
);
707 engine
->fb
.takedown(dev
);
708 engine
->timer
.takedown(dev
);
709 engine
->gpio
.takedown(dev
);
710 engine
->mc
.takedown(dev
);
711 engine
->display
.late_takedown(dev
);
713 mutex_lock(&dev
->struct_mutex
);
714 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_VRAM
);
715 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_TT
);
716 mutex_unlock(&dev
->struct_mutex
);
717 nouveau_mem_gart_fini(dev
);
719 engine
->instmem
.takedown(dev
);
720 nouveau_gpuobj_takedown(dev
);
721 nouveau_mem_vram_fini(dev
);
723 drm_irq_uninstall(dev
);
725 nouveau_pm_fini(dev
);
726 nouveau_bios_takedown(dev
);
728 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
731 /* here a client dies, release the stuff that was allocated for its
733 void nouveau_preclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
735 nouveau_channel_cleanup(dev
, file_priv
);
738 /* first module load, setup the mmio/fb mapping */
739 /* KMS: we need mmio at load time, not when the first drm client opens. */
740 int nouveau_firstopen(struct drm_device
*dev
)
745 /* if we have an OF card, copy vbios to RAMIN */
746 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device
*dev
)
748 #if defined(__powerpc__)
750 const uint32_t *bios
;
751 struct device_node
*dn
= pci_device_to_OF_node(dev
->pdev
);
753 NV_INFO(dev
, "Unable to get the OF node\n");
757 bios
= of_get_property(dn
, "NVDA,BMP", &size
);
759 for (i
= 0; i
< size
; i
+= 4)
760 nv_wi32(dev
, i
, bios
[i
/4]);
761 NV_INFO(dev
, "OF bios successfully copied (%d bytes)\n", size
);
763 NV_INFO(dev
, "Unable to get the OF bios\n");
768 static struct apertures_struct
*nouveau_get_apertures(struct drm_device
*dev
)
770 struct pci_dev
*pdev
= dev
->pdev
;
771 struct apertures_struct
*aper
= alloc_apertures(3);
775 aper
->ranges
[0].base
= pci_resource_start(pdev
, 1);
776 aper
->ranges
[0].size
= pci_resource_len(pdev
, 1);
779 if (pci_resource_len(pdev
, 2)) {
780 aper
->ranges
[aper
->count
].base
= pci_resource_start(pdev
, 2);
781 aper
->ranges
[aper
->count
].size
= pci_resource_len(pdev
, 2);
785 if (pci_resource_len(pdev
, 3)) {
786 aper
->ranges
[aper
->count
].base
= pci_resource_start(pdev
, 3);
787 aper
->ranges
[aper
->count
].size
= pci_resource_len(pdev
, 3);
794 static int nouveau_remove_conflicting_drivers(struct drm_device
*dev
)
796 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
797 bool primary
= false;
798 dev_priv
->apertures
= nouveau_get_apertures(dev
);
799 if (!dev_priv
->apertures
)
803 primary
= dev
->pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
806 remove_conflicting_framebuffers(dev_priv
->apertures
, "nouveaufb", primary
);
810 int nouveau_load(struct drm_device
*dev
, unsigned long flags
)
812 struct drm_nouveau_private
*dev_priv
;
814 resource_size_t mmio_start_offs
;
817 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
822 dev
->dev_private
= dev_priv
;
825 dev_priv
->flags
= flags
& NOUVEAU_FLAGS
;
827 NV_DEBUG(dev
, "vendor: 0x%X device: 0x%X class: 0x%X\n",
828 dev
->pci_vendor
, dev
->pci_device
, dev
->pdev
->class);
830 dev_priv
->wq
= create_workqueue("nouveau");
836 /* resource 0 is mmio regs */
837 /* resource 1 is linear FB */
838 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
839 /* resource 6 is bios */
841 /* map the mmio regs */
842 mmio_start_offs
= pci_resource_start(dev
->pdev
, 0);
843 dev_priv
->mmio
= ioremap(mmio_start_offs
, 0x00800000);
844 if (!dev_priv
->mmio
) {
845 NV_ERROR(dev
, "Unable to initialize the mmio mapping. "
846 "Please report your setup to " DRIVER_EMAIL
"\n");
850 NV_DEBUG(dev
, "regs mapped ok at 0x%llx\n",
851 (unsigned long long)mmio_start_offs
);
854 /* Put the card in BE mode if it's not */
855 if (nv_rd32(dev
, NV03_PMC_BOOT_1
))
856 nv_wr32(dev
, NV03_PMC_BOOT_1
, 0x00000001);
861 /* Time to determine the card architecture */
862 reg0
= nv_rd32(dev
, NV03_PMC_BOOT_0
);
864 /* We're dealing with >=NV10 */
865 if ((reg0
& 0x0f000000) > 0) {
866 /* Bit 27-20 contain the architecture in hex */
867 dev_priv
->chipset
= (reg0
& 0xff00000) >> 20;
869 } else if ((reg0
& 0xff00fff0) == 0x20004000) {
870 if (reg0
& 0x00f00000)
871 dev_priv
->chipset
= 0x05;
873 dev_priv
->chipset
= 0x04;
875 dev_priv
->chipset
= 0xff;
877 switch (dev_priv
->chipset
& 0xf0) {
882 dev_priv
->card_type
= dev_priv
->chipset
& 0xf0;
886 dev_priv
->card_type
= NV_40
;
892 dev_priv
->card_type
= NV_50
;
895 dev_priv
->card_type
= NV_C0
;
898 NV_INFO(dev
, "Unsupported chipset 0x%08x\n", reg0
);
903 NV_INFO(dev
, "Detected an NV%2x generation card (0x%08x)\n",
904 dev_priv
->card_type
, reg0
);
906 ret
= nouveau_remove_conflicting_drivers(dev
);
910 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
911 if (dev_priv
->card_type
>= NV_40
) {
913 if (pci_resource_len(dev
->pdev
, ramin_bar
) == 0)
916 dev_priv
->ramin_size
= pci_resource_len(dev
->pdev
, ramin_bar
);
918 ioremap(pci_resource_start(dev
->pdev
, ramin_bar
),
919 dev_priv
->ramin_size
);
920 if (!dev_priv
->ramin
) {
921 NV_ERROR(dev
, "Failed to PRAMIN BAR");
926 dev_priv
->ramin_size
= 1 * 1024 * 1024;
927 dev_priv
->ramin
= ioremap(mmio_start_offs
+ NV_RAMIN
,
928 dev_priv
->ramin_size
);
929 if (!dev_priv
->ramin
) {
930 NV_ERROR(dev
, "Failed to map BAR0 PRAMIN.\n");
936 nouveau_OF_copy_vbios_to_ramin(dev
);
939 if (dev
->pci_device
== 0x01a0)
940 dev_priv
->flags
|= NV_NFORCE
;
941 else if (dev
->pci_device
== 0x01f0)
942 dev_priv
->flags
|= NV_NFORCE2
;
944 /* For kernel modesetting, init card now and bring up fbcon */
945 ret
= nouveau_card_init(dev
);
952 iounmap(dev_priv
->ramin
);
954 iounmap(dev_priv
->mmio
);
956 destroy_workqueue(dev_priv
->wq
);
959 dev
->dev_private
= NULL
;
964 void nouveau_lastclose(struct drm_device
*dev
)
968 int nouveau_unload(struct drm_device
*dev
)
970 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
971 struct nouveau_engine
*engine
= &dev_priv
->engine
;
973 drm_kms_helper_poll_fini(dev
);
974 nouveau_fbcon_fini(dev
);
975 engine
->display
.destroy(dev
);
976 nouveau_card_takedown(dev
);
978 iounmap(dev_priv
->mmio
);
979 iounmap(dev_priv
->ramin
);
982 dev
->dev_private
= NULL
;
986 int nouveau_ioctl_getparam(struct drm_device
*dev
, void *data
,
987 struct drm_file
*file_priv
)
989 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
990 struct drm_nouveau_getparam
*getparam
= data
;
992 switch (getparam
->param
) {
993 case NOUVEAU_GETPARAM_CHIPSET_ID
:
994 getparam
->value
= dev_priv
->chipset
;
996 case NOUVEAU_GETPARAM_PCI_VENDOR
:
997 getparam
->value
= dev
->pci_vendor
;
999 case NOUVEAU_GETPARAM_PCI_DEVICE
:
1000 getparam
->value
= dev
->pci_device
;
1002 case NOUVEAU_GETPARAM_BUS_TYPE
:
1003 if (drm_device_is_agp(dev
))
1004 getparam
->value
= NV_AGP
;
1005 else if (drm_device_is_pcie(dev
))
1006 getparam
->value
= NV_PCIE
;
1008 getparam
->value
= NV_PCI
;
1010 case NOUVEAU_GETPARAM_FB_PHYSICAL
:
1011 getparam
->value
= dev_priv
->fb_phys
;
1013 case NOUVEAU_GETPARAM_AGP_PHYSICAL
:
1014 getparam
->value
= dev_priv
->gart_info
.aper_base
;
1016 case NOUVEAU_GETPARAM_PCI_PHYSICAL
:
1018 getparam
->value
= (unsigned long)dev
->sg
->virtual;
1020 NV_ERROR(dev
, "Requested PCIGART address, "
1021 "while no PCIGART was created\n");
1025 case NOUVEAU_GETPARAM_FB_SIZE
:
1026 getparam
->value
= dev_priv
->fb_available_size
;
1028 case NOUVEAU_GETPARAM_AGP_SIZE
:
1029 getparam
->value
= dev_priv
->gart_info
.aper_size
;
1031 case NOUVEAU_GETPARAM_VM_VRAM_BASE
:
1032 getparam
->value
= dev_priv
->vm_vram_base
;
1034 case NOUVEAU_GETPARAM_PTIMER_TIME
:
1035 getparam
->value
= dev_priv
->engine
.timer
.read(dev
);
1037 case NOUVEAU_GETPARAM_GRAPH_UNITS
:
1038 /* NV40 and NV50 versions are quite different, but register
1039 * address is the same. User is supposed to know the card
1040 * family anyway... */
1041 if (dev_priv
->chipset
>= 0x40) {
1042 getparam
->value
= nv_rd32(dev
, NV40_PMC_GRAPH_UNITS
);
1047 NV_ERROR(dev
, "unknown parameter %lld\n", getparam
->param
);
1055 nouveau_ioctl_setparam(struct drm_device
*dev
, void *data
,
1056 struct drm_file
*file_priv
)
1058 struct drm_nouveau_setparam
*setparam
= data
;
1060 switch (setparam
->param
) {
1062 NV_ERROR(dev
, "unknown parameter %lld\n", setparam
->param
);
1069 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1070 bool nouveau_wait_until(struct drm_device
*dev
, uint64_t timeout
,
1071 uint32_t reg
, uint32_t mask
, uint32_t val
)
1073 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1074 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
1075 uint64_t start
= ptimer
->read(dev
);
1078 if ((nv_rd32(dev
, reg
) & mask
) == val
)
1080 } while (ptimer
->read(dev
) - start
< timeout
);
1085 /* Waits for PGRAPH to go completely idle */
1086 bool nouveau_wait_for_idle(struct drm_device
*dev
)
1088 if (!nv_wait(dev
, NV04_PGRAPH_STATUS
, 0xffffffff, 0x00000000)) {
1089 NV_ERROR(dev
, "PGRAPH idle timed out with status 0x%08x\n",
1090 nv_rd32(dev
, NV04_PGRAPH_STATUS
));