drm: tegra: remove redundant tegra2_tmds_config entry
[linux-2.6.git] / arch / arm / mach-imx / mach-mx51_babbage.c
blobd9a84ca2199ac2391463787b66e6661542e6e064
1 /*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c.h>
16 #include <linux/gpio.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/input.h>
20 #include <linux/spi/flash.h>
21 #include <linux/spi/spi.h>
23 #include <asm/setup.h>
24 #include <asm/mach-types.h>
25 #include <asm/mach/arch.h>
26 #include <asm/mach/time.h>
28 #include "common.h"
29 #include "devices-imx51.h"
30 #include "cpu_op-mx51.h"
31 #include "hardware.h"
32 #include "iomux-mx51.h"
34 #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
35 #define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
36 #define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
37 #define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
38 #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
39 #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
40 #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
41 #define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
42 #define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
44 /* USB_CTRL_1 */
45 #define MX51_USB_CTRL_1_OFFSET 0x10
46 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48 #define MX51_USB_PLLDIV_12_MHZ 0x00
49 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
50 #define MX51_USB_PLL_DIV_24_MHZ 0x02
52 static struct gpio_keys_button babbage_buttons[] = {
54 .gpio = BABBAGE_POWER_KEY,
55 .code = BTN_0,
56 .desc = "PWR",
57 .active_low = 1,
58 .wakeup = 1,
62 static const struct gpio_keys_platform_data imx_button_data __initconst = {
63 .buttons = babbage_buttons,
64 .nbuttons = ARRAY_SIZE(babbage_buttons),
67 static iomux_v3_cfg_t mx51babbage_pads[] = {
68 /* UART1 */
69 MX51_PAD_UART1_RXD__UART1_RXD,
70 MX51_PAD_UART1_TXD__UART1_TXD,
71 MX51_PAD_UART1_RTS__UART1_RTS,
72 MX51_PAD_UART1_CTS__UART1_CTS,
74 /* UART2 */
75 MX51_PAD_UART2_RXD__UART2_RXD,
76 MX51_PAD_UART2_TXD__UART2_TXD,
78 /* UART3 */
79 MX51_PAD_EIM_D25__UART3_RXD,
80 MX51_PAD_EIM_D26__UART3_TXD,
81 MX51_PAD_EIM_D27__UART3_RTS,
82 MX51_PAD_EIM_D24__UART3_CTS,
84 /* I2C1 */
85 MX51_PAD_EIM_D16__I2C1_SDA,
86 MX51_PAD_EIM_D19__I2C1_SCL,
88 /* I2C2 */
89 MX51_PAD_KEY_COL4__I2C2_SCL,
90 MX51_PAD_KEY_COL5__I2C2_SDA,
92 /* HSI2C */
93 MX51_PAD_I2C1_CLK__I2C1_CLK,
94 MX51_PAD_I2C1_DAT__I2C1_DAT,
96 /* USB HOST1 */
97 MX51_PAD_USBH1_CLK__USBH1_CLK,
98 MX51_PAD_USBH1_DIR__USBH1_DIR,
99 MX51_PAD_USBH1_NXT__USBH1_NXT,
100 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
101 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
102 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
103 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
104 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
105 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
106 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
107 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
109 /* USB HUB reset line*/
110 MX51_PAD_GPIO1_7__GPIO1_7,
112 /* USB PHY reset line */
113 MX51_PAD_EIM_D21__GPIO2_5,
115 /* FEC */
116 MX51_PAD_EIM_EB2__FEC_MDIO,
117 MX51_PAD_EIM_EB3__FEC_RDATA1,
118 MX51_PAD_EIM_CS2__FEC_RDATA2,
119 MX51_PAD_EIM_CS3__FEC_RDATA3,
120 MX51_PAD_EIM_CS4__FEC_RX_ER,
121 MX51_PAD_EIM_CS5__FEC_CRS,
122 MX51_PAD_NANDF_RB2__FEC_COL,
123 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
124 MX51_PAD_NANDF_D9__FEC_RDATA0,
125 MX51_PAD_NANDF_D8__FEC_TDATA0,
126 MX51_PAD_NANDF_CS2__FEC_TX_ER,
127 MX51_PAD_NANDF_CS3__FEC_MDC,
128 MX51_PAD_NANDF_CS4__FEC_TDATA1,
129 MX51_PAD_NANDF_CS5__FEC_TDATA2,
130 MX51_PAD_NANDF_CS6__FEC_TDATA3,
131 MX51_PAD_NANDF_CS7__FEC_TX_EN,
132 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
134 /* FEC PHY reset line */
135 MX51_PAD_EIM_A20__GPIO2_14,
137 /* SD 1 */
138 MX51_PAD_SD1_CMD__SD1_CMD,
139 MX51_PAD_SD1_CLK__SD1_CLK,
140 MX51_PAD_SD1_DATA0__SD1_DATA0,
141 MX51_PAD_SD1_DATA1__SD1_DATA1,
142 MX51_PAD_SD1_DATA2__SD1_DATA2,
143 MX51_PAD_SD1_DATA3__SD1_DATA3,
144 /* CD/WP from controller */
145 MX51_PAD_GPIO1_0__SD1_CD,
146 MX51_PAD_GPIO1_1__SD1_WP,
148 /* SD 2 */
149 MX51_PAD_SD2_CMD__SD2_CMD,
150 MX51_PAD_SD2_CLK__SD2_CLK,
151 MX51_PAD_SD2_DATA0__SD2_DATA0,
152 MX51_PAD_SD2_DATA1__SD2_DATA1,
153 MX51_PAD_SD2_DATA2__SD2_DATA2,
154 MX51_PAD_SD2_DATA3__SD2_DATA3,
155 /* CD/WP gpio */
156 MX51_PAD_GPIO1_6__GPIO1_6,
157 MX51_PAD_GPIO1_5__GPIO1_5,
159 /* eCSPI1 */
160 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
161 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
162 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
163 MX51_PAD_CSPI1_SS0__GPIO4_24,
164 MX51_PAD_CSPI1_SS1__GPIO4_25,
166 /* Audio */
167 MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
168 MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
169 MX51_PAD_AUD3_BB_CK__AUD3_TXC,
170 MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
173 /* Serial ports */
174 static const struct imxuart_platform_data uart_pdata __initconst = {
175 .flags = IMXUART_HAVE_RTSCTS,
178 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
179 .bitrate = 100000,
182 static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
183 .bitrate = 400000,
186 static struct gpio mx51_babbage_usbh1_gpios[] = {
187 { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
188 { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
191 static int gpio_usbh1_active(void)
193 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
194 int ret;
196 /* Set USBH1_STP to GPIO and toggle it */
197 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
198 ret = gpio_request_array(mx51_babbage_usbh1_gpios,
199 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
201 if (ret) {
202 pr_debug("failed to get USBH1 pins: %d\n", ret);
203 return ret;
206 msleep(100);
207 gpio_set_value(BABBAGE_USBH1_STP, 1);
208 gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
209 gpio_free_array(mx51_babbage_usbh1_gpios,
210 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
211 return 0;
214 static inline void babbage_usbhub_reset(void)
216 int ret;
218 /* Reset USB hub */
219 ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
220 GPIOF_OUT_INIT_LOW, "GPIO1_7");
221 if (ret) {
222 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
223 return;
226 msleep(2);
227 /* Deassert reset */
228 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
231 static inline void babbage_fec_reset(void)
233 int ret;
235 /* reset FEC PHY */
236 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
237 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
238 if (ret) {
239 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
240 return;
242 msleep(1);
243 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
246 /* This function is board specific as the bit mask for the plldiv will also
247 be different for other Freescale SoCs, thus a common bitmask is not
248 possible and cannot get place in /plat-mxc/ehci.c.*/
249 static int initialize_otg_port(struct platform_device *pdev)
251 u32 v;
252 void __iomem *usb_base;
253 void __iomem *usbother_base;
255 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
256 if (!usb_base)
257 return -ENOMEM;
258 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
260 /* Set the PHY clock to 19.2MHz */
261 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
262 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
263 v |= MX51_USB_PLL_DIV_19_2_MHZ;
264 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
265 iounmap(usb_base);
267 mdelay(10);
269 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
272 static int initialize_usbh1_port(struct platform_device *pdev)
274 u32 v;
275 void __iomem *usb_base;
276 void __iomem *usbother_base;
278 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
279 if (!usb_base)
280 return -ENOMEM;
281 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
283 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
284 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
285 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
286 iounmap(usb_base);
288 mdelay(10);
290 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
291 MXC_EHCI_ITC_NO_THRESHOLD);
294 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
295 .init = initialize_otg_port,
296 .portsc = MXC_EHCI_UTMI_16BIT,
299 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
300 .operating_mode = FSL_USB2_DR_DEVICE,
301 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
304 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
305 .init = initialize_usbh1_port,
306 .portsc = MXC_EHCI_MODE_ULPI,
309 static bool otg_mode_host __initdata;
311 static int __init babbage_otg_mode(char *options)
313 if (!strcmp(options, "host"))
314 otg_mode_host = true;
315 else if (!strcmp(options, "device"))
316 otg_mode_host = false;
317 else
318 pr_info("otg_mode neither \"host\" nor \"device\". "
319 "Defaulting to device\n");
320 return 1;
322 __setup("otg_mode=", babbage_otg_mode);
324 static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
326 .modalias = "mtd_dataflash",
327 .max_speed_hz = 25000000,
328 .bus_num = 0,
329 .chip_select = 1,
330 .mode = SPI_MODE_0,
331 .platform_data = NULL,
335 static int mx51_babbage_spi_cs[] = {
336 BABBAGE_ECSPI1_CS0,
337 BABBAGE_ECSPI1_CS1,
340 static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
341 .chipselect = mx51_babbage_spi_cs,
342 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
345 static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
346 .cd_type = ESDHC_CD_CONTROLLER,
347 .wp_type = ESDHC_WP_CONTROLLER,
350 static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
351 .cd_gpio = BABBAGE_SD2_CD,
352 .wp_gpio = BABBAGE_SD2_WP,
353 .cd_type = ESDHC_CD_GPIO,
354 .wp_type = ESDHC_WP_GPIO,
357 void __init imx51_babbage_common_init(void)
359 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
360 ARRAY_SIZE(mx51babbage_pads));
364 * Board specific initialization.
366 static void __init mx51_babbage_init(void)
368 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
369 iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
370 PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);
372 imx51_soc_init();
374 #if defined(CONFIG_CPU_FREQ_IMX)
375 get_cpu_op = mx51_get_cpu_op;
376 #endif
377 imx51_babbage_common_init();
379 imx51_add_imx_uart(0, &uart_pdata);
380 imx51_add_imx_uart(1, NULL);
381 imx51_add_imx_uart(2, &uart_pdata);
383 babbage_fec_reset();
384 imx51_add_fec(NULL);
386 /* Set the PAD settings for the pwr key. */
387 mxc_iomux_v3_setup_pad(power_key);
388 imx_add_gpio_keys(&imx_button_data);
390 imx51_add_imx_i2c(0, &babbage_i2c_data);
391 imx51_add_imx_i2c(1, &babbage_i2c_data);
392 imx51_add_hsi2c(&babbage_hsi2c_data);
394 if (otg_mode_host)
395 imx51_add_mxc_ehci_otg(&dr_utmi_config);
396 else {
397 initialize_otg_port(NULL);
398 imx51_add_fsl_usb2_udc(&usb_pdata);
401 gpio_usbh1_active();
402 imx51_add_mxc_ehci_hs(1, &usbh1_config);
403 /* setback USBH1_STP to be function */
404 mxc_iomux_v3_setup_pad(usbh1stp);
405 babbage_usbhub_reset();
407 imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
408 imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
410 spi_register_board_info(mx51_babbage_spi_board_info,
411 ARRAY_SIZE(mx51_babbage_spi_board_info));
412 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
413 imx51_add_imx2_wdt(0);
416 static void __init mx51_babbage_timer_init(void)
418 mx51_clocks_init(32768, 24000000, 22579200, 0);
421 static struct sys_timer mx51_babbage_timer = {
422 .init = mx51_babbage_timer_init,
425 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
426 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
427 .atag_offset = 0x100,
428 .map_io = mx51_map_io,
429 .init_early = imx51_init_early,
430 .init_irq = mx51_init_irq,
431 .handle_irq = imx51_handle_irq,
432 .timer = &mx51_babbage_timer,
433 .init_machine = mx51_babbage_init,
434 .init_late = imx51_init_late,
435 .restart = mxc_restart,
436 MACHINE_END