arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/smp_scu.h>
  26
  27 #include <plat/cpu.h>
  28 #include <plat/pm.h>
  29 #include <plat/pll.h>
  30 #include <plat/regs-srom.h>
  31
  32 #include <mach/regs-irq.h>
  33 #include <mach/regs-gpio.h>
  34 #include <mach/regs-clock.h>
  35 #include <mach/regs-pmu.h>
  36 #include <mach/pm-core.h>
  37 #include <mach/pmu.h>
  38
  39 static struct sleep_save exynos4_set_clksrc[] = {
  40         { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
  41         { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
  42         { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
  43         { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
  44         { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
  45         { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
  46         { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
  47         { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
  48         { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
  49 };
  50
  51 static struct sleep_save exynos4210_set_clksrc[] = {
  52         { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
  53 };
  54
  55 static struct sleep_save exynos4_epll_save[] = {
  56         SAVE_ITEM(EXYNOS4_EPLL_CON0),
  57         SAVE_ITEM(EXYNOS4_EPLL_CON1),
  58 };
  59
  60 static struct sleep_save exynos4_vpll_save[] = {
  61         SAVE_ITEM(EXYNOS4_VPLL_CON0),
  62         SAVE_ITEM(EXYNOS4_VPLL_CON1),
  63 };
  64
  65 static struct sleep_save exynos5_sys_save[] = {
  66         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  67 };
  68
  69 static struct sleep_save exynos_core_save[] = {
  70         /* SROM side */
  71         SAVE_ITEM(S5P_SROM_BW),
  72         SAVE_ITEM(S5P_SROM_BC0),
  73         SAVE_ITEM(S5P_SROM_BC1),
  74         SAVE_ITEM(S5P_SROM_BC2),
  75         SAVE_ITEM(S5P_SROM_BC3),
  76 };
  77
  78
  79 /* For Cortex-A9 Diagnostic and Power control register */
  80 static unsigned int save_arm_register[2];
  81
  82 static int exynos_cpu_suspend(unsigned long arg)
  83 {
  84 #ifdef CONFIG_CACHE_L2X0
  85         outer_flush_all();
  86 #endif
  87
  88         if (soc_is_exynos5250())
  89                 flush_cache_all();
  90
  91         /* issue the standby signal into the pm unit. */
  92         cpu_do_idle();
  93
  94         /* we should never get past here */
  95         panic("sleep resumed to originator?");
  96 }
  97
  98 static void exynos_pm_prepare(void)
  99 {
 100         unsigned int tmp;
 101
 102         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 103
 104         if (!soc_is_exynos5250()) {
 105                 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
 106                 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 107         } else {
 108                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 109                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 110                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 111                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 112                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 113         }
 114
 115         /* Set value of power down register for sleep mode */
 116
 117         exynos_sys_powerdown_conf(SYS_SLEEP);
 118         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 119
 120         /* ensure at least INFORM0 has the resume address */
 121
 122         __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
 123
 124         /* Before enter central sequence mode, clock src register have to set */
 125
 126         if (!soc_is_exynos5250())
 127                 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
 128
 129         if (soc_is_exynos4210())
 130                 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
 131
 132 }
 133
 134 static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
 135 {
 136         pm_cpu_prep = exynos_pm_prepare;
 137         pm_cpu_sleep = exynos_cpu_suspend;
 138
 139         return 0;
 140 }
 141
 142 static unsigned long pll_base_rate;
 143
 144 static void exynos4_restore_pll(void)
 145 {
 146         unsigned long pll_con, locktime, lockcnt;
 147         unsigned long pll_in_rate;
 148         unsigned int p_div, epll_wait = 0, vpll_wait = 0;
 149
 150         if (pll_base_rate == 0)
 151                 return;
 152
 153         pll_in_rate = pll_base_rate;
 154
 155         /* EPLL */
 156         pll_con = exynos4_epll_save[0].val;
 157
 158         if (pll_con & (1 << 31)) {
 159                 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
 160                 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
 161
 162                 pll_in_rate /= 1000000;
 163
 164                 locktime = (3000 / pll_in_rate) * p_div;
 165                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 166
 167                 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
 168
 169                 s3c_pm_do_restore_core(exynos4_epll_save,
 170                                         ARRAY_SIZE(exynos4_epll_save));
 171                 epll_wait = 1;
 172         }
 173
 174         pll_in_rate = pll_base_rate;
 175
 176         /* VPLL */
 177         pll_con = exynos4_vpll_save[0].val;
 178
 179         if (pll_con & (1 << 31)) {
 180                 pll_in_rate /= 1000000;
 181                 /* 750us */
 182                 locktime = 750;
 183                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 184
 185                 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
 186
 187                 s3c_pm_do_restore_core(exynos4_vpll_save,
 188                                         ARRAY_SIZE(exynos4_vpll_save));
 189                 vpll_wait = 1;
 190         }
 191
 192         /* Wait PLL locking */
 193
 194         do {
 195                 if (epll_wait) {
 196                         pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
 197                         if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
 198                                 epll_wait = 0;
 199                 }
 200
 201                 if (vpll_wait) {
 202                         pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
 203                         if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
 204                                 vpll_wait = 0;
 205                 }
 206         } while (epll_wait || vpll_wait);
 207 }
 208
 209 static struct subsys_interface exynos_pm_interface = {
 210         .name           = "exynos_pm",
 211         .subsys         = &exynos_subsys,
 212         .add_dev        = exynos_pm_add,
 213 };
 214
 215 static __init int exynos_pm_drvinit(void)
 216 {
 217         struct clk *pll_base;
 218         unsigned int tmp;
 219
 220         s3c_pm_init();
 221
 222         /* All wakeup disable */
 223
 224         tmp = __raw_readl(S5P_WAKEUP_MASK);
 225         tmp |= ((0xFF << 8) | (0x1F << 1));
 226         __raw_writel(tmp, S5P_WAKEUP_MASK);
 227
 228         if (!soc_is_exynos5250()) {
 229                 pll_base = clk_get(NULL, "xtal");
 230
 231                 if (!IS_ERR(pll_base)) {
 232                         pll_base_rate = clk_get_rate(pll_base);
 233                         clk_put(pll_base);
 234                 }
 235         }
 236
 237         return subsys_interface_register(&exynos_pm_interface);
 238 }
 239 arch_initcall(exynos_pm_drvinit);
 240
 241 static int exynos_pm_suspend(void)
 242 {
 243         unsigned long tmp;
 244
 245         /* Setting Central Sequence Register for power down mode */
 246
 247         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 248         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 249         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 250
 251         /* Setting SEQ_OPTION register */
 252
 253         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 254         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 255
 256         if (!soc_is_exynos5250()) {
 257                 /* Save Power control register */
 258                 asm ("mrc p15, 0, %0, c15, c0, 0"
 259                      : "=r" (tmp) : : "cc");
 260                 save_arm_register[0] = tmp;
 261
 262                 /* Save Diagnostic register */
 263                 asm ("mrc p15, 0, %0, c15, c0, 1"
 264                      : "=r" (tmp) : : "cc");
 265                 save_arm_register[1] = tmp;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static void exynos_pm_resume(void)
 272 {
 273         unsigned long tmp;
 274
 275         /*
 276          * If PMU failed while entering sleep mode, WFI will be
 277          * ignored by PMU and then exiting cpu_do_idle().
 278          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 279          * in this situation.
 280          */
 281         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 282         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 283                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 284                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 285                 /* No need to perform below restore code */
 286                 goto early_wakeup;
 287         }
 288         if (!soc_is_exynos5250()) {
 289                 /* Restore Power control register */
 290                 tmp = save_arm_register[0];
 291                 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 292                               : : "r" (tmp)
 293                               : "cc");
 294
 295                 /* Restore Diagnostic register */
 296                 tmp = save_arm_register[1];
 297                 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 298                               : : "r" (tmp)
 299                               : "cc");
 300         }
 301
 302         /* For release retention */
 303
 304         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 305         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 306         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 307         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 308         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 309         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 310         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 311
 312         if (soc_is_exynos5250())
 313                 s3c_pm_do_restore(exynos5_sys_save,
 314                         ARRAY_SIZE(exynos5_sys_save));
 315
 316         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 317
 318         if (!soc_is_exynos5250()) {
 319                 exynos4_restore_pll();
 320
 321 #ifdef CONFIG_SMP
 322                 scu_enable(S5P_VA_SCU);
 323 #endif
 324         }
 325
 326 early_wakeup:
 327
 328         /* Clear SLEEP mode set in INFORM1 */
 329         __raw_writel(0x0, S5P_INFORM1);
 330
 331         return;
 332 }
 333
 334 static struct syscore_ops exynos_pm_syscore_ops = {
 335         .suspend        = exynos_pm_suspend,
 336         .resume         = exynos_pm_resume,
 337 };
 338
 339 static __init int exynos_pm_syscore_init(void)
 340 {
 341         register_syscore_ops(&exynos_pm_syscore_ops);
 342         return 0;
 343 }
 344 arch_initcall(exynos_pm_syscore_init);