arch/arm/mach-exynos/platsmp.c

   1 /* linux/arch/arm/mach-exynos4/platsmp.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   7  *
   8  *  Copyright (C) 2002 ARM Ltd.
   9  *  All Rights Reserved
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/smp.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/hardware/gic.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/smp_scu.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/regs-clock.h>
  31 #include <mach/regs-pmu.h>
  32
  33 #include <plat/cpu.h>
  34
  35 #include "common.h"
  36
  37 extern void exynos4_secondary_startup(void);
  38
  39 static inline void __iomem *cpu_boot_reg_base(void)
  40 {
  41         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
  42                 return S5P_INFORM5;
  43         return S5P_VA_SYSRAM;
  44 }
  45
  46 static inline void __iomem *cpu_boot_reg(int cpu)
  47 {
  48         void __iomem *boot_reg;
  49
  50         boot_reg = cpu_boot_reg_base();
  51         if (soc_is_exynos4412())
  52                 boot_reg += 4*cpu;
  53         return boot_reg;
  54 }
  55
  56 /*
  57  * Write pen_release in a way that is guaranteed to be visible to all
  58  * observers, irrespective of whether they're taking part in coherency
  59  * or not.  This is necessary for the hotplug code to work reliably.
  60  */
  61 static void write_pen_release(int val)
  62 {
  63         pen_release = val;
  64         smp_wmb();
  65         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  66         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  67 }
  68
  69 static void __iomem *scu_base_addr(void)
  70 {
  71         return (void __iomem *)(S5P_VA_SCU);
  72 }
  73
  74 static DEFINE_SPINLOCK(boot_lock);
  75
  76 static void __cpuinit exynos_secondary_init(unsigned int cpu)
  77 {
  78         /*
  79          * if any interrupts are already enabled for the primary
  80          * core (e.g. timer irq), then they will not have been enabled
  81          * for us: do so
  82          */
  83         gic_secondary_init(0);
  84
  85         /*
  86          * let the primary processor know we're out of the
  87          * pen, then head off into the C entry point
  88          */
  89         write_pen_release(-1);
  90
  91         /*
  92          * Synchronise with the boot thread.
  93          */
  94         spin_lock(&boot_lock);
  95         spin_unlock(&boot_lock);
  96 }
  97
  98 static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
  99 {
 100         unsigned long timeout;
 101         unsigned long phys_cpu = cpu_logical_map(cpu);
 102
 103         /*
 104          * Set synchronisation state between this boot processor
 105          * and the secondary one
 106          */
 107         spin_lock(&boot_lock);
 108
 109         /*
 110          * The secondary processor is waiting to be released from
 111          * the holding pen - release it, then wait for it to flag
 112          * that it has been released by resetting pen_release.
 113          *
 114          * Note that "pen_release" is the hardware CPU ID, whereas
 115          * "cpu" is Linux's internal ID.
 116          */
 117         write_pen_release(phys_cpu);
 118
 119         if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
 120                 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
 121                              S5P_ARM_CORE1_CONFIGURATION);
 122
 123                 timeout = 10;
 124
 125                 /* wait max 10 ms until cpu1 is on */
 126                 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
 127                         & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
 128                         if (timeout-- == 0)
 129                                 break;
 130
 131                         mdelay(1);
 132                 }
 133
 134                 if (timeout == 0) {
 135                         printk(KERN_ERR "cpu1 power enable failed");
 136                         spin_unlock(&boot_lock);
 137                         return -ETIMEDOUT;
 138                 }
 139         }
 140         /*
 141          * Send the secondary CPU a soft interrupt, thereby causing
 142          * the boot monitor to read the system wide flags register,
 143          * and branch to the address found there.
 144          */
 145
 146         timeout = jiffies + (1 * HZ);
 147         while (time_before(jiffies, timeout)) {
 148                 smp_rmb();
 149
 150                 __raw_writel(virt_to_phys(exynos4_secondary_startup),
 151                                                         cpu_boot_reg(phys_cpu));
 152                 gic_raise_softirq(cpumask_of(cpu), 0);
 153
 154                 if (pen_release == -1)
 155                         break;
 156
 157                 udelay(10);
 158         }
 159
 160         /*
 161          * now the secondary core is starting up let it run its
 162          * calibrations, then wait for it to finish
 163          */
 164         spin_unlock(&boot_lock);
 165
 166         return pen_release != -1 ? -ENOSYS : 0;
 167 }
 168
 169 /*
 170  * Initialise the CPU possible map early - this describes the CPUs
 171  * which may be present or become present in the system.
 172  */
 173
 174 static void __init exynos_smp_init_cpus(void)
 175 {
 176         void __iomem *scu_base = scu_base_addr();
 177         unsigned int i, ncores;
 178
 179         if (soc_is_exynos5250())
 180                 ncores = 2;
 181         else
 182                 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 183
 184         /* sanity check */
 185         if (ncores > nr_cpu_ids) {
 186                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 187                         ncores, nr_cpu_ids);
 188                 ncores = nr_cpu_ids;
 189         }
 190
 191         for (i = 0; i < ncores; i++)
 192                 set_cpu_possible(i, true);
 193
 194         set_smp_cross_call(gic_raise_softirq);
 195 }
 196
 197 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 198 {
 199         int i;
 200
 201         if (!(soc_is_exynos5250() || soc_is_exynos5440()))
 202                 scu_enable(scu_base_addr());
 203
 204         /*
 205          * Write the address of secondary startup into the
 206          * system-wide flags register. The boot monitor waits
 207          * until it receives a soft interrupt, and then the
 208          * secondary CPU branches to this address.
 209          */
 210         for (i = 1; i < max_cpus; ++i)
 211                 __raw_writel(virt_to_phys(exynos4_secondary_startup),
 212                                         cpu_boot_reg(cpu_logical_map(i)));
 213 }
 214
 215 struct smp_operations exynos_smp_ops __initdata = {
 216         .smp_init_cpus          = exynos_smp_init_cpus,
 217         .smp_prepare_cpus       = exynos_smp_prepare_cpus,
 218         .smp_secondary_init     = exynos_secondary_init,
 219         .smp_boot_secondary     = exynos_boot_secondary,
 220 #ifdef CONFIG_HOTPLUG_CPU
 221         .cpu_die                = exynos_cpu_die,
 222 #endif
 223 };