arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/bitops.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/gpio.h>
  20 #include <clocksource/samsung_pwm.h>
  21 #include <linux/sched.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/of.h>
  24 #include <linux/of_fdt.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/export.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/of_address.h>
  29 #include <linux/irqchip/arm-gic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/platform_device.h>
  32
  33 #include <asm/proc-fns.h>
  34 #include <asm/exception.h>
  35 #include <asm/hardware/cache-l2x0.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/irq.h>
  38 #include <asm/cacheflush.h>
  39
  40 #include <mach/regs-irq.h>
  41 #include <mach/regs-pmu.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/pm.h>
  45 #include <plat/regs-serial.h>
  46
  47 #include "common.h"
  48 #define L2_AUX_VAL 0x7C470001
  49 #define L2_AUX_MASK 0xC200ffff
  50
  51 static const char name_exynos4210[] = "EXYNOS4210";
  52 static const char name_exynos4212[] = "EXYNOS4212";
  53 static const char name_exynos4412[] = "EXYNOS4412";
  54 static const char name_exynos5250[] = "EXYNOS5250";
  55 static const char name_exynos5420[] = "EXYNOS5420";
  56 static const char name_exynos5440[] = "EXYNOS5440";
  57
  58 static void exynos4_map_io(void);
  59 static void exynos5_map_io(void);
  60 static int exynos_init(void);
  61
  62 static struct cpu_table cpu_ids[] __initdata = {
  63         {
  64                 .idcode         = EXYNOS4210_CPU_ID,
  65                 .idmask         = EXYNOS4_CPU_MASK,
  66                 .map_io         = exynos4_map_io,
  67                 .init           = exynos_init,
  68                 .name           = name_exynos4210,
  69         }, {
  70                 .idcode         = EXYNOS4212_CPU_ID,
  71                 .idmask         = EXYNOS4_CPU_MASK,
  72                 .map_io         = exynos4_map_io,
  73                 .init           = exynos_init,
  74                 .name           = name_exynos4212,
  75         }, {
  76                 .idcode         = EXYNOS4412_CPU_ID,
  77                 .idmask         = EXYNOS4_CPU_MASK,
  78                 .map_io         = exynos4_map_io,
  79                 .init           = exynos_init,
  80                 .name           = name_exynos4412,
  81         }, {
  82                 .idcode         = EXYNOS5250_SOC_ID,
  83                 .idmask         = EXYNOS5_SOC_MASK,
  84                 .map_io         = exynos5_map_io,
  85                 .init           = exynos_init,
  86                 .name           = name_exynos5250,
  87         }, {
  88                 .idcode         = EXYNOS5420_SOC_ID,
  89                 .idmask         = EXYNOS5_SOC_MASK,
  90                 .map_io         = exynos5_map_io,
  91                 .init           = exynos_init,
  92                 .name           = name_exynos5420,
  93         }, {
  94                 .idcode         = EXYNOS5440_SOC_ID,
  95                 .idmask         = EXYNOS5_SOC_MASK,
  96                 .init           = exynos_init,
  97                 .name           = name_exynos5440,
  98         },
  99 };
 100
 101 /* Initial IO mappings */
 102
 103 static struct map_desc exynos4_iodesc[] __initdata = {
 104         {
 105                 .virtual        = (unsigned long)S3C_VA_SYS,
 106                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 107                 .length         = SZ_64K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)S3C_VA_TIMER,
 111                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 112                 .length         = SZ_16K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 116                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)S5P_VA_SROMC,
 121                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 126                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)S5P_VA_PMU,
 131                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 132                 .length         = SZ_64K,
 133                 .type           = MT_DEVICE,
 134         }, {
 135                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 136                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 137                 .length         = SZ_4K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 141                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 142                 .length         = SZ_64K,
 143                 .type           = MT_DEVICE,
 144         }, {
 145                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 146                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 147                 .length         = SZ_64K,
 148                 .type           = MT_DEVICE,
 149         }, {
 150                 .virtual        = (unsigned long)S5P_VA_CMU,
 151                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 152                 .length         = SZ_128K,
 153                 .type           = MT_DEVICE,
 154         }, {
 155                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 156                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 157                 .length         = SZ_8K,
 158                 .type           = MT_DEVICE,
 159         }, {
 160                 .virtual        = (unsigned long)S5P_VA_L2CC,
 161                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 162                 .length         = SZ_4K,
 163                 .type           = MT_DEVICE,
 164         }, {
 165                 .virtual        = (unsigned long)S5P_VA_DMC0,
 166                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 167                 .length         = SZ_64K,
 168                 .type           = MT_DEVICE,
 169         }, {
 170                 .virtual        = (unsigned long)S5P_VA_DMC1,
 171                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 172                 .length         = SZ_64K,
 173                 .type           = MT_DEVICE,
 174         }, {
 175                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 176                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 177                 .length         = SZ_4K,
 178                 .type           = MT_DEVICE,
 179         },
 180 };
 181
 182 static struct map_desc exynos4_iodesc0[] __initdata = {
 183         {
 184                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 185                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 186                 .length         = SZ_4K,
 187                 .type           = MT_DEVICE,
 188         },
 189 };
 190
 191 static struct map_desc exynos4_iodesc1[] __initdata = {
 192         {
 193                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 194                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 195                 .length         = SZ_4K,
 196                 .type           = MT_DEVICE,
 197         },
 198 };
 199
 200 static struct map_desc exynos4210_iodesc[] __initdata = {
 201         {
 202                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 203                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 204                 .length         = SZ_4K,
 205                 .type           = MT_DEVICE,
 206         },
 207 };
 208
 209 static struct map_desc exynos4x12_iodesc[] __initdata = {
 210         {
 211                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 212                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 213                 .length         = SZ_4K,
 214                 .type           = MT_DEVICE,
 215         },
 216 };
 217
 218 static struct map_desc exynos5250_iodesc[] __initdata = {
 219         {
 220                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 221                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 222                 .length         = SZ_4K,
 223                 .type           = MT_DEVICE,
 224         },
 225 };
 226
 227 static struct map_desc exynos5_iodesc[] __initdata = {
 228         {
 229                 .virtual        = (unsigned long)S3C_VA_SYS,
 230                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 231                 .length         = SZ_64K,
 232                 .type           = MT_DEVICE,
 233         }, {
 234                 .virtual        = (unsigned long)S3C_VA_TIMER,
 235                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 236                 .length         = SZ_16K,
 237                 .type           = MT_DEVICE,
 238         }, {
 239                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 240                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 241                 .length         = SZ_4K,
 242                 .type           = MT_DEVICE,
 243         }, {
 244                 .virtual        = (unsigned long)S5P_VA_SROMC,
 245                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 246                 .length         = SZ_4K,
 247                 .type           = MT_DEVICE,
 248         }, {
 249                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 250                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 251                 .length         = SZ_4K,
 252                 .type           = MT_DEVICE,
 253         }, {
 254                 .virtual        = (unsigned long)S5P_VA_CMU,
 255                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 256                 .length         = 144 * SZ_1K,
 257                 .type           = MT_DEVICE,
 258         }, {
 259                 .virtual        = (unsigned long)S5P_VA_PMU,
 260                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 261                 .length         = SZ_64K,
 262                 .type           = MT_DEVICE,
 263         },
 264 };
 265
 266 void exynos4_restart(enum reboot_mode mode, const char *cmd)
 267 {
 268         __raw_writel(0x1, S5P_SWRESET);
 269 }
 270
 271 void exynos5_restart(enum reboot_mode mode, const char *cmd)
 272 {
 273         struct device_node *np;
 274         u32 val;
 275         void __iomem *addr;
 276
 277         val = 0x1;
 278         addr = EXYNOS_SWRESET;
 279
 280         if (of_machine_is_compatible("samsung,exynos5440")) {
 281                 u32 status;
 282                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 283
 284                 addr = of_iomap(np, 0) + 0xbc;
 285                 status = __raw_readl(addr);
 286
 287                 addr = of_iomap(np, 0) + 0xcc;
 288                 val = __raw_readl(addr);
 289
 290                 val = (val & 0xffff0000) | (status & 0xffff);
 291         }
 292
 293         __raw_writel(val, addr);
 294 }
 295
 296 static struct platform_device exynos_cpuidle = {
 297         .name           = "exynos_cpuidle",
 298         .id             = -1,
 299 };
 300
 301 void __init exynos_cpuidle_init(void)
 302 {
 303         platform_device_register(&exynos_cpuidle);
 304 }
 305
 306 void __init exynos_init_late(void)
 307 {
 308         if (of_machine_is_compatible("samsung,exynos5440"))
 309                 /* to be supported later */
 310                 return;
 311
 312         exynos_pm_late_initcall();
 313 }
 314
 315 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 316                                         int depth, void *data)
 317 {
 318         struct map_desc iodesc;
 319         __be32 *reg;
 320         unsigned long len;
 321
 322         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 323                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 324                 return 0;
 325
 326         reg = of_get_flat_dt_prop(node, "reg", &len);
 327         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 328                 return 0;
 329
 330         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 331         iodesc.length = be32_to_cpu(reg[1]) - 1;
 332         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 333         iodesc.type = MT_DEVICE;
 334         iotable_init(&iodesc, 1);
 335         return 1;
 336 }
 337
 338 /*
 339  * exynos_map_io
 340  *
 341  * register the standard cpu IO areas
 342  */
 343
 344 void __init exynos_init_io(void)
 345 {
 346         debug_ll_io_init();
 347
 348         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 349
 350         /* detect cpu id and rev. */
 351         s5p_init_cpu(S5P_VA_CHIPID);
 352
 353         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 354 }
 355
 356 static void __init exynos4_map_io(void)
 357 {
 358         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 359
 360         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 361                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 362         else
 363                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 364
 365         if (soc_is_exynos4210())
 366                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 367         if (soc_is_exynos4212() || soc_is_exynos4412())
 368                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 369 }
 370
 371 static void __init exynos5_map_io(void)
 372 {
 373         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 374
 375         if (soc_is_exynos5250())
 376                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 377 }
 378
 379 struct bus_type exynos_subsys = {
 380         .name           = "exynos-core",
 381         .dev_name       = "exynos-core",
 382 };
 383
 384 static struct device exynos4_dev = {
 385         .bus    = &exynos_subsys,
 386 };
 387
 388 static int __init exynos_core_init(void)
 389 {
 390         return subsys_system_register(&exynos_subsys, NULL);
 391 }
 392 core_initcall(exynos_core_init);
 393
 394 static int __init exynos4_l2x0_cache_init(void)
 395 {
 396         int ret;
 397
 398         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 399         if (ret)
 400                 return ret;
 401
 402         l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 403         clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 404         return 0;
 405 }
 406 early_initcall(exynos4_l2x0_cache_init);
 407
 408 static int __init exynos_init(void)
 409 {
 410         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 411
 412         return device_register(&exynos4_dev);
 413 }