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drm/radeon/kms/igp: fix possible divide by 0 in bandwidth code (v2)
[linux-2.6.git] / drivers / gpu / drm / radeon / rs690.c
blobf4f0a61bcdce3d188dd01a5737120c4e9a0d6432
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "atom.h"
32 #include "rs690d.h"
33
34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
35 {
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
43 return 0;
44 udelay(1);
45 }
46 return -1;
47 }
48
49 static void rs690_gpu_init(struct radeon_device *rdev)
50 {
51 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57 }
58
59 union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62 };
63
64 void rs690_pm_info(struct radeon_device *rdev)
65 {
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
67 union igp_info *info;
68 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 if (info->info.usK8MemoryClock)
83 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84 else if (rdev->clock.default_mclk) {
85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
87 } else
88 rdev->pm.igp_system_mclk.full = dfixed_const(400);
89 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
91 break;
92 case 2:
93 tmp.full = dfixed_const(100);
94 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
96 if (info->info_v2.ulBootUpUMAClock)
97 rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
98 else if (rdev->clock.default_mclk)
99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
100 else
101 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
106 break;
107 default:
108 /* We assume the slower possible clock ie worst case */
109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110 rdev->pm.igp_system_mclk.full = dfixed_const(200);
111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
112 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
113 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
114 break;
115 }
116 } else {
117 /* We assume the slower possible clock ie worst case */
118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
121 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
122 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
123 }
124 /* Compute various bandwidth */
125 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
126 tmp.full = dfixed_const(4);
127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
128 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
129 * = ht_clk * ht_width / 5
130 */
131 tmp.full = dfixed_const(5);
132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
133 rdev->pm.igp_ht_link_width);
134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
135 if (tmp.full < rdev->pm.max_bandwidth.full) {
136 /* HT link is a limiting factor */
137 rdev->pm.max_bandwidth.full = tmp.full;
138 }
139 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
140 * = (sideport_clk * 14) / 10
141 */
142 tmp.full = dfixed_const(14);
143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144 tmp.full = dfixed_const(10);
145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
146 }
147
148 void rs690_mc_init(struct radeon_device *rdev)
149 {
150 u64 base;
151
152 rs400_gart_adjust_size(rdev);
153 rdev->mc.vram_is_ddr = true;
154 rdev->mc.vram_width = 128;
155 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
156 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
157 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
158 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16;
162 rs690_pm_info(rdev);
163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base);
165 radeon_gtt_location(rdev, &rdev->mc);
166 radeon_update_bandwidth_info(rdev);
167 }
168
169 void rs690_line_buffer_adjust(struct radeon_device *rdev,
170 struct drm_display_mode *mode1,
171 struct drm_display_mode *mode2)
172 {
173 u32 tmp;
174
175 /*
176 * Line Buffer Setup
177 * There is a single line buffer shared by both display controllers.
178 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
179 * the display controllers. The paritioning can either be done
180 * manually or via one of four preset allocations specified in bits 1:0:
181 * 0 - line buffer is divided in half and shared between crtc
182 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
183 * 2 - D1 gets the whole buffer
184 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
185 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
186 * allocation mode. In manual allocation mode, D1 always starts at 0,
187 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
188 */
189 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
190 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
191 /* auto */
192 if (mode1 && mode2) {
193 if (mode1->hdisplay > mode2->hdisplay) {
194 if (mode1->hdisplay > 2560)
195 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
196 else
197 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
198 } else if (mode2->hdisplay > mode1->hdisplay) {
199 if (mode2->hdisplay > 2560)
200 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
201 else
202 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
203 } else
204 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
205 } else if (mode1) {
206 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
207 } else if (mode2) {
208 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
209 }
210 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
211 }
212
213 struct rs690_watermark {
214 u32 lb_request_fifo_depth;
215 fixed20_12 num_line_pair;
216 fixed20_12 estimated_width;
217 fixed20_12 worst_case_latency;
218 fixed20_12 consumption_rate;
219 fixed20_12 active_time;
220 fixed20_12 dbpp;
221 fixed20_12 priority_mark_max;
222 fixed20_12 priority_mark;
223 fixed20_12 sclk;
224 };
225
226 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
227 struct radeon_crtc *crtc,
228 struct rs690_watermark *wm)
229 {
230 struct drm_display_mode *mode = &crtc->base.mode;
231 fixed20_12 a, b, c;
232 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
233 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
234
235 if (!crtc->base.enabled) {
236 /* FIXME: wouldn't it better to set priority mark to maximum */
237 wm->lb_request_fifo_depth = 4;
238 return;
239 }
240
241 if (crtc->vsc.full > dfixed_const(2))
242 wm->num_line_pair.full = dfixed_const(2);
243 else
244 wm->num_line_pair.full = dfixed_const(1);
245
246 b.full = dfixed_const(mode->crtc_hdisplay);
247 c.full = dfixed_const(256);
248 a.full = dfixed_div(b, c);
249 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
250 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
251 if (a.full < dfixed_const(4)) {
252 wm->lb_request_fifo_depth = 4;
253 } else {
254 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
255 }
256
257 /* Determine consumption rate
258 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
259 * vtaps = number of vertical taps,
260 * vsc = vertical scaling ratio, defined as source/destination
261 * hsc = horizontal scaling ration, defined as source/destination
262 */
263 a.full = dfixed_const(mode->clock);
264 b.full = dfixed_const(1000);
265 a.full = dfixed_div(a, b);
266 pclk.full = dfixed_div(b, a);
267 if (crtc->rmx_type != RMX_OFF) {
268 b.full = dfixed_const(2);
269 if (crtc->vsc.full > b.full)
270 b.full = crtc->vsc.full;
271 b.full = dfixed_mul(b, crtc->hsc);
272 c.full = dfixed_const(2);
273 b.full = dfixed_div(b, c);
274 consumption_time.full = dfixed_div(pclk, b);
275 } else {
276 consumption_time.full = pclk.full;
277 }
278 a.full = dfixed_const(1);
279 wm->consumption_rate.full = dfixed_div(a, consumption_time);
280
281
282 /* Determine line time
283 * LineTime = total time for one line of displayhtotal
284 * LineTime = total number of horizontal pixels
285 * pclk = pixel clock period(ns)
286 */
287 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
288 line_time.full = dfixed_mul(a, pclk);
289
290 /* Determine active time
291 * ActiveTime = time of active region of display within one line,
292 * hactive = total number of horizontal active pixels
293 * htotal = total number of horizontal pixels
294 */
295 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
296 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
297 wm->active_time.full = dfixed_mul(line_time, b);
298 wm->active_time.full = dfixed_div(wm->active_time, a);
299
300 /* Maximun bandwidth is the minimun bandwidth of all component */
301 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
302 if (rdev->mc.igp_sideport_enabled) {
303 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
304 rdev->pm.sideport_bandwidth.full)
305 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
306 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
307 read_delay_latency.full = dfixed_div(read_delay_latency,
308 rdev->pm.igp_sideport_mclk);
309 } else {
310 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
311 rdev->pm.k8_bandwidth.full)
312 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
313 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
314 rdev->pm.ht_bandwidth.full)
315 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
316 read_delay_latency.full = dfixed_const(5000);
317 }
318
319 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
320 a.full = dfixed_const(16);
321 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
322 a.full = dfixed_const(1000);
323 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
324 /* Determine chunk time
325 * ChunkTime = the time it takes the DCP to send one chunk of data
326 * to the LB which consists of pipeline delay and inter chunk gap
327 * sclk = system clock(ns)
328 */
329 a.full = dfixed_const(256 * 13);
330 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
331 a.full = dfixed_const(10);
332 chunk_time.full = dfixed_div(chunk_time, a);
333
334 /* Determine the worst case latency
335 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
336 * WorstCaseLatency = worst case time from urgent to when the MC starts
337 * to return data
338 * READ_DELAY_IDLE_MAX = constant of 1us
339 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
340 * which consists of pipeline delay and inter chunk gap
341 */
342 if (dfixed_trunc(wm->num_line_pair) > 1) {
343 a.full = dfixed_const(3);
344 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
345 wm->worst_case_latency.full += read_delay_latency.full;
346 } else {
347 a.full = dfixed_const(2);
348 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
349 wm->worst_case_latency.full += read_delay_latency.full;
350 }
351
352 /* Determine the tolerable latency
353 * TolerableLatency = Any given request has only 1 line time
354 * for the data to be returned
355 * LBRequestFifoDepth = Number of chunk requests the LB can
356 * put into the request FIFO for a display
357 * LineTime = total time for one line of display
358 * ChunkTime = the time it takes the DCP to send one chunk
359 * of data to the LB which consists of
360 * pipeline delay and inter chunk gap
361 */
362 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
363 tolerable_latency.full = line_time.full;
364 } else {
365 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
366 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
367 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
368 tolerable_latency.full = line_time.full - tolerable_latency.full;
369 }
370 /* We assume worst case 32bits (4 bytes) */
371 wm->dbpp.full = dfixed_const(4 * 8);
372
373 /* Determine the maximum priority mark
374 * width = viewport width in pixels
375 */
376 a.full = dfixed_const(16);
377 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
378 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
379 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
380
381 /* Determine estimated width */
382 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
383 estimated_width.full = dfixed_div(estimated_width, consumption_time);
384 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
385 wm->priority_mark.full = dfixed_const(10);
386 } else {
387 a.full = dfixed_const(16);
388 wm->priority_mark.full = dfixed_div(estimated_width, a);
389 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
390 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
391 }
392 }
393
394 void rs690_bandwidth_update(struct radeon_device *rdev)
395 {
396 struct drm_display_mode *mode0 = NULL;
397 struct drm_display_mode *mode1 = NULL;
398 struct rs690_watermark wm0;
399 struct rs690_watermark wm1;
400 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
401 fixed20_12 priority_mark02, priority_mark12, fill_rate;
402 fixed20_12 a, b;
403
404 radeon_update_display_priority(rdev);
405
406 if (rdev->mode_info.crtcs[0]->base.enabled)
407 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
408 if (rdev->mode_info.crtcs[1]->base.enabled)
409 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
410 /*
411 * Set display0/1 priority up in the memory controller for
412 * modes if the user specifies HIGH for displaypriority
413 * option.
414 */
415 if ((rdev->disp_priority == 2) &&
416 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
417 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
418 tmp &= C_000104_MC_DISP0R_INIT_LAT;
419 tmp &= C_000104_MC_DISP1R_INIT_LAT;
420 if (mode0)
421 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
422 if (mode1)
423 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
424 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
425 }
426 rs690_line_buffer_adjust(rdev, mode0, mode1);
427
428 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
429 WREG32(R_006C9C_DCP_CONTROL, 0);
430 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
431 WREG32(R_006C9C_DCP_CONTROL, 2);
432
433 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
434 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
435
436 tmp = (wm0.lb_request_fifo_depth - 1);
437 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
438 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
439
440 if (mode0 && mode1) {
441 if (dfixed_trunc(wm0.dbpp) > 64)
442 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
443 else
444 a.full = wm0.num_line_pair.full;
445 if (dfixed_trunc(wm1.dbpp) > 64)
446 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
447 else
448 b.full = wm1.num_line_pair.full;
449 a.full += b.full;
450 fill_rate.full = dfixed_div(wm0.sclk, a);
451 if (wm0.consumption_rate.full > fill_rate.full) {
452 b.full = wm0.consumption_rate.full - fill_rate.full;
453 b.full = dfixed_mul(b, wm0.active_time);
454 a.full = dfixed_mul(wm0.worst_case_latency,
455 wm0.consumption_rate);
456 a.full = a.full + b.full;
457 b.full = dfixed_const(16 * 1000);
458 priority_mark02.full = dfixed_div(a, b);
459 } else {
460 a.full = dfixed_mul(wm0.worst_case_latency,
461 wm0.consumption_rate);
462 b.full = dfixed_const(16 * 1000);
463 priority_mark02.full = dfixed_div(a, b);
464 }
465 if (wm1.consumption_rate.full > fill_rate.full) {
466 b.full = wm1.consumption_rate.full - fill_rate.full;
467 b.full = dfixed_mul(b, wm1.active_time);
468 a.full = dfixed_mul(wm1.worst_case_latency,
469 wm1.consumption_rate);
470 a.full = a.full + b.full;
471 b.full = dfixed_const(16 * 1000);
472 priority_mark12.full = dfixed_div(a, b);
473 } else {
474 a.full = dfixed_mul(wm1.worst_case_latency,
475 wm1.consumption_rate);
476 b.full = dfixed_const(16 * 1000);
477 priority_mark12.full = dfixed_div(a, b);
478 }
479 if (wm0.priority_mark.full > priority_mark02.full)
480 priority_mark02.full = wm0.priority_mark.full;
481 if (dfixed_trunc(priority_mark02) < 0)
482 priority_mark02.full = 0;
483 if (wm0.priority_mark_max.full > priority_mark02.full)
484 priority_mark02.full = wm0.priority_mark_max.full;
485 if (wm1.priority_mark.full > priority_mark12.full)
486 priority_mark12.full = wm1.priority_mark.full;
487 if (dfixed_trunc(priority_mark12) < 0)
488 priority_mark12.full = 0;
489 if (wm1.priority_mark_max.full > priority_mark12.full)
490 priority_mark12.full = wm1.priority_mark_max.full;
491 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
492 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
493 if (rdev->disp_priority == 2) {
494 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
495 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
496 }
497 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
498 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
499 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
500 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
501 } else if (mode0) {
502 if (dfixed_trunc(wm0.dbpp) > 64)
503 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
504 else
505 a.full = wm0.num_line_pair.full;
506 fill_rate.full = dfixed_div(wm0.sclk, a);
507 if (wm0.consumption_rate.full > fill_rate.full) {
508 b.full = wm0.consumption_rate.full - fill_rate.full;
509 b.full = dfixed_mul(b, wm0.active_time);
510 a.full = dfixed_mul(wm0.worst_case_latency,
511 wm0.consumption_rate);
512 a.full = a.full + b.full;
513 b.full = dfixed_const(16 * 1000);
514 priority_mark02.full = dfixed_div(a, b);
515 } else {
516 a.full = dfixed_mul(wm0.worst_case_latency,
517 wm0.consumption_rate);
518 b.full = dfixed_const(16 * 1000);
519 priority_mark02.full = dfixed_div(a, b);
520 }
521 if (wm0.priority_mark.full > priority_mark02.full)
522 priority_mark02.full = wm0.priority_mark.full;
523 if (dfixed_trunc(priority_mark02) < 0)
524 priority_mark02.full = 0;
525 if (wm0.priority_mark_max.full > priority_mark02.full)
526 priority_mark02.full = wm0.priority_mark_max.full;
527 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
528 if (rdev->disp_priority == 2)
529 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
530 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
531 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
532 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
533 S_006D48_D2MODE_PRIORITY_A_OFF(1));
534 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
535 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
536 } else {
537 if (dfixed_trunc(wm1.dbpp) > 64)
538 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
539 else
540 a.full = wm1.num_line_pair.full;
541 fill_rate.full = dfixed_div(wm1.sclk, a);
542 if (wm1.consumption_rate.full > fill_rate.full) {
543 b.full = wm1.consumption_rate.full - fill_rate.full;
544 b.full = dfixed_mul(b, wm1.active_time);
545 a.full = dfixed_mul(wm1.worst_case_latency,
546 wm1.consumption_rate);
547 a.full = a.full + b.full;
548 b.full = dfixed_const(16 * 1000);
549 priority_mark12.full = dfixed_div(a, b);
550 } else {
551 a.full = dfixed_mul(wm1.worst_case_latency,
552 wm1.consumption_rate);
553 b.full = dfixed_const(16 * 1000);
554 priority_mark12.full = dfixed_div(a, b);
555 }
556 if (wm1.priority_mark.full > priority_mark12.full)
557 priority_mark12.full = wm1.priority_mark.full;
558 if (dfixed_trunc(priority_mark12) < 0)
559 priority_mark12.full = 0;
560 if (wm1.priority_mark_max.full > priority_mark12.full)
561 priority_mark12.full = wm1.priority_mark_max.full;
562 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
563 if (rdev->disp_priority == 2)
564 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
565 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
566 S_006548_D1MODE_PRIORITY_A_OFF(1));
567 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
568 S_00654C_D1MODE_PRIORITY_B_OFF(1));
569 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
570 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
571 }
572 }
573
574 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
575 {
576 uint32_t r;
577
578 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
579 r = RREG32(R_00007C_MC_DATA);
580 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
581 return r;
582 }
583
584 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
585 {
586 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
587 S_000078_MC_IND_WR_EN(1));
588 WREG32(R_00007C_MC_DATA, v);
589 WREG32(R_000078_MC_INDEX, 0x7F);
590 }
591
592 void rs690_mc_program(struct radeon_device *rdev)
593 {
594 struct rv515_mc_save save;
595
596 /* Stops all mc clients */
597 rv515_mc_stop(rdev, &save);
598
599 /* Wait for mc idle */
600 if (rs690_mc_wait_for_idle(rdev))
601 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
602 /* Program MC, should be a 32bits limited address space */
603 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
604 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
605 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
606 WREG32(R_000134_HDP_FB_LOCATION,
607 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
608
609 rv515_mc_resume(rdev, &save);
610 }
611
612 static int rs690_startup(struct radeon_device *rdev)
613 {
614 int r;
615
616 rs690_mc_program(rdev);
617 /* Resume clock */
618 rv515_clock_startup(rdev);
619 /* Initialize GPU configuration (# pipes, ...) */
620 rs690_gpu_init(rdev);
621 /* Initialize GART (initialize after TTM so we can allocate
622 * memory through TTM but finalize after TTM) */
623 r = rs400_gart_enable(rdev);
624 if (r)
625 return r;
626 /* Enable IRQ */
627 rs600_irq_set(rdev);
628 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
629 /* 1M ring buffer */
630 r = r100_cp_init(rdev, 1024 * 1024);
631 if (r) {
632 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
633 return r;
634 }
635 r = r100_wb_init(rdev);
636 if (r)
637 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
638 r = r100_ib_init(rdev);
639 if (r) {
640 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
641 return r;
642 }
643 return 0;
644 }
645
646 int rs690_resume(struct radeon_device *rdev)
647 {
648 /* Make sur GART are not working */
649 rs400_gart_disable(rdev);
650 /* Resume clock before doing reset */
651 rv515_clock_startup(rdev);
652 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
653 if (radeon_asic_reset(rdev)) {
654 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
655 RREG32(R_000E40_RBBM_STATUS),
656 RREG32(R_0007C0_CP_STAT));
657 }
658 /* post */
659 atom_asic_init(rdev->mode_info.atom_context);
660 /* Resume clock after posting */
661 rv515_clock_startup(rdev);
662 /* Initialize surface registers */
663 radeon_surface_init(rdev);
664 return rs690_startup(rdev);
665 }
666
667 int rs690_suspend(struct radeon_device *rdev)
668 {
669 r100_cp_disable(rdev);
670 r100_wb_disable(rdev);
671 rs600_irq_disable(rdev);
672 rs400_gart_disable(rdev);
673 return 0;
674 }
675
676 void rs690_fini(struct radeon_device *rdev)
677 {
678 r100_cp_fini(rdev);
679 r100_wb_fini(rdev);
680 r100_ib_fini(rdev);
681 radeon_gem_fini(rdev);
682 rs400_gart_fini(rdev);
683 radeon_irq_kms_fini(rdev);
684 radeon_fence_driver_fini(rdev);
685 radeon_bo_fini(rdev);
686 radeon_atombios_fini(rdev);
687 kfree(rdev->bios);
688 rdev->bios = NULL;
689 }
690
691 int rs690_init(struct radeon_device *rdev)
692 {
693 int r;
694
695 /* Disable VGA */
696 rv515_vga_render_disable(rdev);
697 /* Initialize scratch registers */
698 radeon_scratch_init(rdev);
699 /* Initialize surface registers */
700 radeon_surface_init(rdev);
701 /* TODO: disable VGA need to use VGA request */
702 /* BIOS*/
703 if (!radeon_get_bios(rdev)) {
704 if (ASIC_IS_AVIVO(rdev))
705 return -EINVAL;
706 }
707 if (rdev->is_atom_bios) {
708 r = radeon_atombios_init(rdev);
709 if (r)
710 return r;
711 } else {
712 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
713 return -EINVAL;
714 }
715 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
716 if (radeon_asic_reset(rdev)) {
717 dev_warn(rdev->dev,
718 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
719 RREG32(R_000E40_RBBM_STATUS),
720 RREG32(R_0007C0_CP_STAT));
721 }
722 /* check if cards are posted or not */
723 if (radeon_boot_test_post_card(rdev) == false)
724 return -EINVAL;
725
726 /* Initialize clocks */
727 radeon_get_clock_info(rdev->ddev);
728 /* initialize memory controller */
729 rs690_mc_init(rdev);
730 rv515_debugfs(rdev);
731 /* Fence driver */
732 r = radeon_fence_driver_init(rdev);
733 if (r)
734 return r;
735 r = radeon_irq_kms_init(rdev);
736 if (r)
737 return r;
738 /* Memory manager */
739 r = radeon_bo_init(rdev);
740 if (r)
741 return r;
742 r = rs400_gart_init(rdev);
743 if (r)
744 return r;
745 rs600_set_safe_registers(rdev);
746 rdev->accel_working = true;
747 r = rs690_startup(rdev);
748 if (r) {
749 /* Somethings want wront with the accel init stop accel */
750 dev_err(rdev->dev, "Disabling GPU acceleration\n");
751 r100_cp_fini(rdev);
752 r100_wb_fini(rdev);
753 r100_ib_fini(rdev);
754 rs400_gart_fini(rdev);
755 radeon_irq_kms_fini(rdev);
756 rdev->accel_working = false;
757 }
758 return 0;
759 }
Linus' kernel tree