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ARM: SAMSUNG: use regulator VDD for ADC
[linux-2.6.git] / drivers / net / sh_eth.c
blob1f3f7b4dd6389d6bcdf4ea8c76baf66d92896f63
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
32 #include <linux/io.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36 #include <asm/cacheflush.h>
37
38 #include "sh_eth.h"
39
40 #define SH_ETH_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR| \
44 NETIF_MSG_TX_ERR)
45
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device *ndev)
50 {
51 struct sh_eth_private *mdp = netdev_priv(ndev);
52
53 if (mdp->duplex) /* Full */
54 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
55 else /* Half */
56 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
57 }
58
59 static void sh_eth_set_rate(struct net_device *ndev)
60 {
61 struct sh_eth_private *mdp = netdev_priv(ndev);
62
63 switch (mdp->speed) {
64 case 10: /* 10BASE */
65 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
66 break;
67 case 100:/* 100BASE */
68 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
69 break;
70 default:
71 break;
72 }
73 }
74
75 /* SH7724 */
76 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
77 .set_duplex = sh_eth_set_duplex,
78 .set_rate = sh_eth_set_rate,
79
80 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
81 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
82 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
83
84 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
85 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
86 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
87 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
88
89 .apr = 1,
90 .mpr = 1,
91 .tpauser = 1,
92 .hw_swap = 1,
93 .rpadir = 1,
94 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
95 };
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97 #define SH_ETH_HAS_BOTH_MODULES 1
98 #define SH_ETH_HAS_TSU 1
99 static void sh_eth_set_duplex(struct net_device *ndev)
100 {
101 struct sh_eth_private *mdp = netdev_priv(ndev);
102
103 if (mdp->duplex) /* Full */
104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
105 else /* Half */
106 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
107 }
108
109 static void sh_eth_set_rate(struct net_device *ndev)
110 {
111 struct sh_eth_private *mdp = netdev_priv(ndev);
112
113 switch (mdp->speed) {
114 case 10: /* 10BASE */
115 sh_eth_write(ndev, 0, RTRATE);
116 break;
117 case 100:/* 100BASE */
118 sh_eth_write(ndev, 1, RTRATE);
119 break;
120 default:
121 break;
122 }
123 }
124
125 /* SH7757 */
126 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
127 .set_duplex = sh_eth_set_duplex,
128 .set_rate = sh_eth_set_rate,
129
130 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
131 .rmcr_value = 0x00000001,
132
133 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
134 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
135 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
136 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
137
138 .apr = 1,
139 .mpr = 1,
140 .tpauser = 1,
141 .hw_swap = 1,
142 .no_ade = 1,
143 .rpadir = 1,
144 .rpadir_value = 2 << 16,
145 };
146
147 #define SH_GIGA_ETH_BASE 0xfee00000
148 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
149 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
150 static void sh_eth_chip_reset_giga(struct net_device *ndev)
151 {
152 int i;
153 unsigned long mahr[2], malr[2];
154
155 /* save MAHR and MALR */
156 for (i = 0; i < 2; i++) {
157 malr[i] = readl(GIGA_MALR(i));
158 mahr[i] = readl(GIGA_MAHR(i));
159 }
160
161 /* reset device */
162 writel(ARSTR_ARSTR, SH_GIGA_ETH_BASE + 0x1800);
163 mdelay(1);
164
165 /* restore MAHR and MALR */
166 for (i = 0; i < 2; i++) {
167 writel(malr[i], GIGA_MALR(i));
168 writel(mahr[i], GIGA_MAHR(i));
169 }
170 }
171
172 static int sh_eth_is_gether(struct sh_eth_private *mdp);
173 static void sh_eth_reset(struct net_device *ndev)
174 {
175 struct sh_eth_private *mdp = netdev_priv(ndev);
176 int cnt = 100;
177
178 if (sh_eth_is_gether(mdp)) {
179 sh_eth_write(ndev, 0x03, EDSR);
180 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
181 EDMR);
182 while (cnt > 0) {
183 if (!(sh_eth_read(ndev, EDMR) & 0x3))
184 break;
185 mdelay(1);
186 cnt--;
187 }
188 if (cnt < 0)
189 printk(KERN_ERR "Device reset fail\n");
190
191 /* Table Init */
192 sh_eth_write(ndev, 0x0, TDLAR);
193 sh_eth_write(ndev, 0x0, TDFAR);
194 sh_eth_write(ndev, 0x0, TDFXR);
195 sh_eth_write(ndev, 0x0, TDFFR);
196 sh_eth_write(ndev, 0x0, RDLAR);
197 sh_eth_write(ndev, 0x0, RDFAR);
198 sh_eth_write(ndev, 0x0, RDFXR);
199 sh_eth_write(ndev, 0x0, RDFFR);
200 } else {
201 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
202 EDMR);
203 mdelay(3);
204 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
205 EDMR);
206 }
207 }
208
209 static void sh_eth_set_duplex_giga(struct net_device *ndev)
210 {
211 struct sh_eth_private *mdp = netdev_priv(ndev);
212
213 if (mdp->duplex) /* Full */
214 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
215 else /* Half */
216 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
217 }
218
219 static void sh_eth_set_rate_giga(struct net_device *ndev)
220 {
221 struct sh_eth_private *mdp = netdev_priv(ndev);
222
223 switch (mdp->speed) {
224 case 10: /* 10BASE */
225 sh_eth_write(ndev, 0x00000000, GECMR);
226 break;
227 case 100:/* 100BASE */
228 sh_eth_write(ndev, 0x00000010, GECMR);
229 break;
230 case 1000: /* 1000BASE */
231 sh_eth_write(ndev, 0x00000020, GECMR);
232 break;
233 default:
234 break;
235 }
236 }
237
238 /* SH7757(GETHERC) */
239 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
240 .chip_reset = sh_eth_chip_reset_giga,
241 .set_duplex = sh_eth_set_duplex_giga,
242 .set_rate = sh_eth_set_rate_giga,
243
244 .ecsr_value = ECSR_ICD | ECSR_MPD,
245 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
246 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
247
248 .tx_check = EESR_TC1 | EESR_FTC,
249 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
250 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
251 EESR_ECI,
252 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
253 EESR_TFE,
254 .fdr_value = 0x0000072f,
255 .rmcr_value = 0x00000001,
256
257 .apr = 1,
258 .mpr = 1,
259 .tpauser = 1,
260 .bculr = 1,
261 .hw_swap = 1,
262 .rpadir = 1,
263 .rpadir_value = 2 << 16,
264 .no_trimd = 1,
265 .no_ade = 1,
266 };
267
268 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
269 {
270 if (sh_eth_is_gether(mdp))
271 return &sh_eth_my_cpu_data_giga;
272 else
273 return &sh_eth_my_cpu_data;
274 }
275
276 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
277 #define SH_ETH_HAS_TSU 1
278 static void sh_eth_chip_reset(struct net_device *ndev)
279 {
280 struct sh_eth_private *mdp = netdev_priv(ndev);
281
282 /* reset device */
283 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
284 mdelay(1);
285 }
286
287 static void sh_eth_reset(struct net_device *ndev)
288 {
289 int cnt = 100;
290
291 sh_eth_write(ndev, EDSR_ENALL, EDSR);
292 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
293 while (cnt > 0) {
294 if (!(sh_eth_read(ndev, EDMR) & 0x3))
295 break;
296 mdelay(1);
297 cnt--;
298 }
299 if (cnt == 0)
300 printk(KERN_ERR "Device reset fail\n");
301
302 /* Table Init */
303 sh_eth_write(ndev, 0x0, TDLAR);
304 sh_eth_write(ndev, 0x0, TDFAR);
305 sh_eth_write(ndev, 0x0, TDFXR);
306 sh_eth_write(ndev, 0x0, TDFFR);
307 sh_eth_write(ndev, 0x0, RDLAR);
308 sh_eth_write(ndev, 0x0, RDFAR);
309 sh_eth_write(ndev, 0x0, RDFXR);
310 sh_eth_write(ndev, 0x0, RDFFR);
311 }
312
313 static void sh_eth_set_duplex(struct net_device *ndev)
314 {
315 struct sh_eth_private *mdp = netdev_priv(ndev);
316
317 if (mdp->duplex) /* Full */
318 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
319 else /* Half */
320 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
321 }
322
323 static void sh_eth_set_rate(struct net_device *ndev)
324 {
325 struct sh_eth_private *mdp = netdev_priv(ndev);
326
327 switch (mdp->speed) {
328 case 10: /* 10BASE */
329 sh_eth_write(ndev, GECMR_10, GECMR);
330 break;
331 case 100:/* 100BASE */
332 sh_eth_write(ndev, GECMR_100, GECMR);
333 break;
334 case 1000: /* 1000BASE */
335 sh_eth_write(ndev, GECMR_1000, GECMR);
336 break;
337 default:
338 break;
339 }
340 }
341
342 /* sh7763 */
343 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
344 .chip_reset = sh_eth_chip_reset,
345 .set_duplex = sh_eth_set_duplex,
346 .set_rate = sh_eth_set_rate,
347
348 .ecsr_value = ECSR_ICD | ECSR_MPD,
349 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
350 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
351
352 .tx_check = EESR_TC1 | EESR_FTC,
353 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
354 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
355 EESR_ECI,
356 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
357 EESR_TFE,
358
359 .apr = 1,
360 .mpr = 1,
361 .tpauser = 1,
362 .bculr = 1,
363 .hw_swap = 1,
364 .no_trimd = 1,
365 .no_ade = 1,
366 .tsu = 1,
367 };
368
369 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
370 #define SH_ETH_RESET_DEFAULT 1
371 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
372 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
373
374 .apr = 1,
375 .mpr = 1,
376 .tpauser = 1,
377 .hw_swap = 1,
378 };
379 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
380 #define SH_ETH_RESET_DEFAULT 1
381 #define SH_ETH_HAS_TSU 1
382 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
383 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
384 .tsu = 1,
385 };
386 #endif
387
388 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
389 {
390 if (!cd->ecsr_value)
391 cd->ecsr_value = DEFAULT_ECSR_INIT;
392
393 if (!cd->ecsipr_value)
394 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
395
396 if (!cd->fcftr_value)
397 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
398 DEFAULT_FIFO_F_D_RFD;
399
400 if (!cd->fdr_value)
401 cd->fdr_value = DEFAULT_FDR_INIT;
402
403 if (!cd->rmcr_value)
404 cd->rmcr_value = DEFAULT_RMCR_VALUE;
405
406 if (!cd->tx_check)
407 cd->tx_check = DEFAULT_TX_CHECK;
408
409 if (!cd->eesr_err_check)
410 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
411
412 if (!cd->tx_error_check)
413 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
414 }
415
416 #if defined(SH_ETH_RESET_DEFAULT)
417 /* Chip Reset */
418 static void sh_eth_reset(struct net_device *ndev)
419 {
420 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
421 mdelay(3);
422 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
423 }
424 #endif
425
426 #if defined(CONFIG_CPU_SH4)
427 static void sh_eth_set_receive_align(struct sk_buff *skb)
428 {
429 int reserve;
430
431 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
432 if (reserve)
433 skb_reserve(skb, reserve);
434 }
435 #else
436 static void sh_eth_set_receive_align(struct sk_buff *skb)
437 {
438 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
439 }
440 #endif
441
442
443 /* CPU <-> EDMAC endian convert */
444 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
445 {
446 switch (mdp->edmac_endian) {
447 case EDMAC_LITTLE_ENDIAN:
448 return cpu_to_le32(x);
449 case EDMAC_BIG_ENDIAN:
450 return cpu_to_be32(x);
451 }
452 return x;
453 }
454
455 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
456 {
457 switch (mdp->edmac_endian) {
458 case EDMAC_LITTLE_ENDIAN:
459 return le32_to_cpu(x);
460 case EDMAC_BIG_ENDIAN:
461 return be32_to_cpu(x);
462 }
463 return x;
464 }
465
466 /*
467 * Program the hardware MAC address from dev->dev_addr.
468 */
469 static void update_mac_address(struct net_device *ndev)
470 {
471 sh_eth_write(ndev,
472 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
473 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
474 sh_eth_write(ndev,
475 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
476 }
477
478 /*
479 * Get MAC address from SuperH MAC address register
480 *
481 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
482 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
483 * When you want use this device, you must set MAC address in bootloader.
484 *
485 */
486 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
487 {
488 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
489 memcpy(ndev->dev_addr, mac, 6);
490 } else {
491 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
492 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
493 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
494 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
495 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
496 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
497 }
498 }
499
500 static int sh_eth_is_gether(struct sh_eth_private *mdp)
501 {
502 if (mdp->reg_offset == sh_eth_offset_gigabit)
503 return 1;
504 else
505 return 0;
506 }
507
508 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
509 {
510 if (sh_eth_is_gether(mdp))
511 return EDTRR_TRNS_GETHER;
512 else
513 return EDTRR_TRNS_ETHER;
514 }
515
516 struct bb_info {
517 void (*set_gate)(unsigned long addr);
518 struct mdiobb_ctrl ctrl;
519 u32 addr;
520 u32 mmd_msk;/* MMD */
521 u32 mdo_msk;
522 u32 mdi_msk;
523 u32 mdc_msk;
524 };
525
526 /* PHY bit set */
527 static void bb_set(u32 addr, u32 msk)
528 {
529 writel(readl(addr) | msk, addr);
530 }
531
532 /* PHY bit clear */
533 static void bb_clr(u32 addr, u32 msk)
534 {
535 writel((readl(addr) & ~msk), addr);
536 }
537
538 /* PHY bit read */
539 static int bb_read(u32 addr, u32 msk)
540 {
541 return (readl(addr) & msk) != 0;
542 }
543
544 /* Data I/O pin control */
545 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
546 {
547 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
548
549 if (bitbang->set_gate)
550 bitbang->set_gate(bitbang->addr);
551
552 if (bit)
553 bb_set(bitbang->addr, bitbang->mmd_msk);
554 else
555 bb_clr(bitbang->addr, bitbang->mmd_msk);
556 }
557
558 /* Set bit data*/
559 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
560 {
561 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
562
563 if (bitbang->set_gate)
564 bitbang->set_gate(bitbang->addr);
565
566 if (bit)
567 bb_set(bitbang->addr, bitbang->mdo_msk);
568 else
569 bb_clr(bitbang->addr, bitbang->mdo_msk);
570 }
571
572 /* Get bit data*/
573 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
574 {
575 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
576
577 if (bitbang->set_gate)
578 bitbang->set_gate(bitbang->addr);
579
580 return bb_read(bitbang->addr, bitbang->mdi_msk);
581 }
582
583 /* MDC pin control */
584 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
585 {
586 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
587
588 if (bitbang->set_gate)
589 bitbang->set_gate(bitbang->addr);
590
591 if (bit)
592 bb_set(bitbang->addr, bitbang->mdc_msk);
593 else
594 bb_clr(bitbang->addr, bitbang->mdc_msk);
595 }
596
597 /* mdio bus control struct */
598 static struct mdiobb_ops bb_ops = {
599 .owner = THIS_MODULE,
600 .set_mdc = sh_mdc_ctrl,
601 .set_mdio_dir = sh_mmd_ctrl,
602 .set_mdio_data = sh_set_mdio,
603 .get_mdio_data = sh_get_mdio,
604 };
605
606 /* free skb and descriptor buffer */
607 static void sh_eth_ring_free(struct net_device *ndev)
608 {
609 struct sh_eth_private *mdp = netdev_priv(ndev);
610 int i;
611
612 /* Free Rx skb ringbuffer */
613 if (mdp->rx_skbuff) {
614 for (i = 0; i < RX_RING_SIZE; i++) {
615 if (mdp->rx_skbuff[i])
616 dev_kfree_skb(mdp->rx_skbuff[i]);
617 }
618 }
619 kfree(mdp->rx_skbuff);
620
621 /* Free Tx skb ringbuffer */
622 if (mdp->tx_skbuff) {
623 for (i = 0; i < TX_RING_SIZE; i++) {
624 if (mdp->tx_skbuff[i])
625 dev_kfree_skb(mdp->tx_skbuff[i]);
626 }
627 }
628 kfree(mdp->tx_skbuff);
629 }
630
631 /* format skb and descriptor buffer */
632 static void sh_eth_ring_format(struct net_device *ndev)
633 {
634 struct sh_eth_private *mdp = netdev_priv(ndev);
635 int i;
636 struct sk_buff *skb;
637 struct sh_eth_rxdesc *rxdesc = NULL;
638 struct sh_eth_txdesc *txdesc = NULL;
639 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
640 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
641
642 mdp->cur_rx = mdp->cur_tx = 0;
643 mdp->dirty_rx = mdp->dirty_tx = 0;
644
645 memset(mdp->rx_ring, 0, rx_ringsize);
646
647 /* build Rx ring buffer */
648 for (i = 0; i < RX_RING_SIZE; i++) {
649 /* skb */
650 mdp->rx_skbuff[i] = NULL;
651 skb = dev_alloc_skb(mdp->rx_buf_sz);
652 mdp->rx_skbuff[i] = skb;
653 if (skb == NULL)
654 break;
655 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
656 DMA_FROM_DEVICE);
657 skb->dev = ndev; /* Mark as being used by this device. */
658 sh_eth_set_receive_align(skb);
659
660 /* RX descriptor */
661 rxdesc = &mdp->rx_ring[i];
662 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
663 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
664
665 /* The size of the buffer is 16 byte boundary. */
666 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
667 /* Rx descriptor address set */
668 if (i == 0) {
669 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
670 if (sh_eth_is_gether(mdp))
671 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
672 }
673 }
674
675 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
676
677 /* Mark the last entry as wrapping the ring. */
678 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
679
680 memset(mdp->tx_ring, 0, tx_ringsize);
681
682 /* build Tx ring buffer */
683 for (i = 0; i < TX_RING_SIZE; i++) {
684 mdp->tx_skbuff[i] = NULL;
685 txdesc = &mdp->tx_ring[i];
686 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
687 txdesc->buffer_length = 0;
688 if (i == 0) {
689 /* Tx descriptor address set */
690 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
691 if (sh_eth_is_gether(mdp))
692 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
693 }
694 }
695
696 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
697 }
698
699 /* Get skb and descriptor buffer */
700 static int sh_eth_ring_init(struct net_device *ndev)
701 {
702 struct sh_eth_private *mdp = netdev_priv(ndev);
703 int rx_ringsize, tx_ringsize, ret = 0;
704
705 /*
706 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
707 * card needs room to do 8 byte alignment, +2 so we can reserve
708 * the first 2 bytes, and +16 gets room for the status word from the
709 * card.
710 */
711 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
712 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
713 if (mdp->cd->rpadir)
714 mdp->rx_buf_sz += NET_IP_ALIGN;
715
716 /* Allocate RX and TX skb rings */
717 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
718 GFP_KERNEL);
719 if (!mdp->rx_skbuff) {
720 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
721 ret = -ENOMEM;
722 return ret;
723 }
724
725 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
726 GFP_KERNEL);
727 if (!mdp->tx_skbuff) {
728 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
729 ret = -ENOMEM;
730 goto skb_ring_free;
731 }
732
733 /* Allocate all Rx descriptors. */
734 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
735 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
736 GFP_KERNEL);
737
738 if (!mdp->rx_ring) {
739 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
740 rx_ringsize);
741 ret = -ENOMEM;
742 goto desc_ring_free;
743 }
744
745 mdp->dirty_rx = 0;
746
747 /* Allocate all Tx descriptors. */
748 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
749 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
750 GFP_KERNEL);
751 if (!mdp->tx_ring) {
752 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
753 tx_ringsize);
754 ret = -ENOMEM;
755 goto desc_ring_free;
756 }
757 return ret;
758
759 desc_ring_free:
760 /* free DMA buffer */
761 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
762
763 skb_ring_free:
764 /* Free Rx and Tx skb ring buffer */
765 sh_eth_ring_free(ndev);
766
767 return ret;
768 }
769
770 static int sh_eth_dev_init(struct net_device *ndev)
771 {
772 int ret = 0;
773 struct sh_eth_private *mdp = netdev_priv(ndev);
774 u_int32_t rx_int_var, tx_int_var;
775 u32 val;
776
777 /* Soft Reset */
778 sh_eth_reset(ndev);
779
780 /* Descriptor format */
781 sh_eth_ring_format(ndev);
782 if (mdp->cd->rpadir)
783 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
784
785 /* all sh_eth int mask */
786 sh_eth_write(ndev, 0, EESIPR);
787
788 #if defined(__LITTLE_ENDIAN__)
789 if (mdp->cd->hw_swap)
790 sh_eth_write(ndev, EDMR_EL, EDMR);
791 else
792 #endif
793 sh_eth_write(ndev, 0, EDMR);
794
795 /* FIFO size set */
796 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
797 sh_eth_write(ndev, 0, TFTR);
798
799 /* Frame recv control */
800 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
801
802 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
803 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
804 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
805
806 if (mdp->cd->bculr)
807 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
808
809 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
810
811 if (!mdp->cd->no_trimd)
812 sh_eth_write(ndev, 0, TRIMD);
813
814 /* Recv frame limit set register */
815 sh_eth_write(ndev, RFLR_VALUE, RFLR);
816
817 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
818 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
819
820 /* PAUSE Prohibition */
821 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
822 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
823
824 sh_eth_write(ndev, val, ECMR);
825
826 if (mdp->cd->set_rate)
827 mdp->cd->set_rate(ndev);
828
829 /* E-MAC Status Register clear */
830 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
831
832 /* E-MAC Interrupt Enable register */
833 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
834
835 /* Set MAC address */
836 update_mac_address(ndev);
837
838 /* mask reset */
839 if (mdp->cd->apr)
840 sh_eth_write(ndev, APR_AP, APR);
841 if (mdp->cd->mpr)
842 sh_eth_write(ndev, MPR_MP, MPR);
843 if (mdp->cd->tpauser)
844 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
845
846 /* Setting the Rx mode will start the Rx process. */
847 sh_eth_write(ndev, EDRRR_R, EDRRR);
848
849 netif_start_queue(ndev);
850
851 return ret;
852 }
853
854 /* free Tx skb function */
855 static int sh_eth_txfree(struct net_device *ndev)
856 {
857 struct sh_eth_private *mdp = netdev_priv(ndev);
858 struct sh_eth_txdesc *txdesc;
859 int freeNum = 0;
860 int entry = 0;
861
862 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
863 entry = mdp->dirty_tx % TX_RING_SIZE;
864 txdesc = &mdp->tx_ring[entry];
865 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
866 break;
867 /* Free the original skb. */
868 if (mdp->tx_skbuff[entry]) {
869 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
870 mdp->tx_skbuff[entry] = NULL;
871 freeNum++;
872 }
873 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
874 if (entry >= TX_RING_SIZE - 1)
875 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
876
877 mdp->stats.tx_packets++;
878 mdp->stats.tx_bytes += txdesc->buffer_length;
879 }
880 return freeNum;
881 }
882
883 /* Packet receive function */
884 static int sh_eth_rx(struct net_device *ndev)
885 {
886 struct sh_eth_private *mdp = netdev_priv(ndev);
887 struct sh_eth_rxdesc *rxdesc;
888
889 int entry = mdp->cur_rx % RX_RING_SIZE;
890 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
891 struct sk_buff *skb;
892 u16 pkt_len = 0;
893 u32 desc_status;
894
895 rxdesc = &mdp->rx_ring[entry];
896 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
897 desc_status = edmac_to_cpu(mdp, rxdesc->status);
898 pkt_len = rxdesc->frame_length;
899
900 if (--boguscnt < 0)
901 break;
902
903 if (!(desc_status & RDFEND))
904 mdp->stats.rx_length_errors++;
905
906 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
907 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
908 mdp->stats.rx_errors++;
909 if (desc_status & RD_RFS1)
910 mdp->stats.rx_crc_errors++;
911 if (desc_status & RD_RFS2)
912 mdp->stats.rx_frame_errors++;
913 if (desc_status & RD_RFS3)
914 mdp->stats.rx_length_errors++;
915 if (desc_status & RD_RFS4)
916 mdp->stats.rx_length_errors++;
917 if (desc_status & RD_RFS6)
918 mdp->stats.rx_missed_errors++;
919 if (desc_status & RD_RFS10)
920 mdp->stats.rx_over_errors++;
921 } else {
922 if (!mdp->cd->hw_swap)
923 sh_eth_soft_swap(
924 phys_to_virt(ALIGN(rxdesc->addr, 4)),
925 pkt_len + 2);
926 skb = mdp->rx_skbuff[entry];
927 mdp->rx_skbuff[entry] = NULL;
928 if (mdp->cd->rpadir)
929 skb_reserve(skb, NET_IP_ALIGN);
930 skb_put(skb, pkt_len);
931 skb->protocol = eth_type_trans(skb, ndev);
932 netif_rx(skb);
933 mdp->stats.rx_packets++;
934 mdp->stats.rx_bytes += pkt_len;
935 }
936 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
937 entry = (++mdp->cur_rx) % RX_RING_SIZE;
938 rxdesc = &mdp->rx_ring[entry];
939 }
940
941 /* Refill the Rx ring buffers. */
942 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
943 entry = mdp->dirty_rx % RX_RING_SIZE;
944 rxdesc = &mdp->rx_ring[entry];
945 /* The size of the buffer is 16 byte boundary. */
946 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
947
948 if (mdp->rx_skbuff[entry] == NULL) {
949 skb = dev_alloc_skb(mdp->rx_buf_sz);
950 mdp->rx_skbuff[entry] = skb;
951 if (skb == NULL)
952 break; /* Better luck next round. */
953 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
954 DMA_FROM_DEVICE);
955 skb->dev = ndev;
956 sh_eth_set_receive_align(skb);
957
958 skb_checksum_none_assert(skb);
959 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
960 }
961 if (entry >= RX_RING_SIZE - 1)
962 rxdesc->status |=
963 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
964 else
965 rxdesc->status |=
966 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
967 }
968
969 /* Restart Rx engine if stopped. */
970 /* If we don't need to check status, don't. -KDU */
971 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
972 sh_eth_write(ndev, EDRRR_R, EDRRR);
973
974 return 0;
975 }
976
977 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
978 {
979 /* disable tx and rx */
980 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
981 ~(ECMR_RE | ECMR_TE), ECMR);
982 }
983
984 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
985 {
986 /* enable tx and rx */
987 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
988 (ECMR_RE | ECMR_TE), ECMR);
989 }
990
991 /* error control function */
992 static void sh_eth_error(struct net_device *ndev, int intr_status)
993 {
994 struct sh_eth_private *mdp = netdev_priv(ndev);
995 u32 felic_stat;
996 u32 link_stat;
997 u32 mask;
998
999 if (intr_status & EESR_ECI) {
1000 felic_stat = sh_eth_read(ndev, ECSR);
1001 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1002 if (felic_stat & ECSR_ICD)
1003 mdp->stats.tx_carrier_errors++;
1004 if (felic_stat & ECSR_LCHNG) {
1005 /* Link Changed */
1006 if (mdp->cd->no_psr || mdp->no_ether_link) {
1007 if (mdp->link == PHY_DOWN)
1008 link_stat = 0;
1009 else
1010 link_stat = PHY_ST_LINK;
1011 } else {
1012 link_stat = (sh_eth_read(ndev, PSR));
1013 if (mdp->ether_link_active_low)
1014 link_stat = ~link_stat;
1015 }
1016 if (!(link_stat & PHY_ST_LINK))
1017 sh_eth_rcv_snd_disable(ndev);
1018 else {
1019 /* Link Up */
1020 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1021 ~DMAC_M_ECI, EESIPR);
1022 /*clear int */
1023 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1024 ECSR);
1025 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1026 DMAC_M_ECI, EESIPR);
1027 /* enable tx and rx */
1028 sh_eth_rcv_snd_enable(ndev);
1029 }
1030 }
1031 }
1032
1033 if (intr_status & EESR_TWB) {
1034 /* Write buck end. unused write back interrupt */
1035 if (intr_status & EESR_TABT) /* Transmit Abort int */
1036 mdp->stats.tx_aborted_errors++;
1037 if (netif_msg_tx_err(mdp))
1038 dev_err(&ndev->dev, "Transmit Abort\n");
1039 }
1040
1041 if (intr_status & EESR_RABT) {
1042 /* Receive Abort int */
1043 if (intr_status & EESR_RFRMER) {
1044 /* Receive Frame Overflow int */
1045 mdp->stats.rx_frame_errors++;
1046 if (netif_msg_rx_err(mdp))
1047 dev_err(&ndev->dev, "Receive Abort\n");
1048 }
1049 }
1050
1051 if (intr_status & EESR_TDE) {
1052 /* Transmit Descriptor Empty int */
1053 mdp->stats.tx_fifo_errors++;
1054 if (netif_msg_tx_err(mdp))
1055 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1056 }
1057
1058 if (intr_status & EESR_TFE) {
1059 /* FIFO under flow */
1060 mdp->stats.tx_fifo_errors++;
1061 if (netif_msg_tx_err(mdp))
1062 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1063 }
1064
1065 if (intr_status & EESR_RDE) {
1066 /* Receive Descriptor Empty int */
1067 mdp->stats.rx_over_errors++;
1068
1069 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
1070 sh_eth_write(ndev, EDRRR_R, EDRRR);
1071 if (netif_msg_rx_err(mdp))
1072 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1073 }
1074
1075 if (intr_status & EESR_RFE) {
1076 /* Receive FIFO Overflow int */
1077 mdp->stats.rx_fifo_errors++;
1078 if (netif_msg_rx_err(mdp))
1079 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1080 }
1081
1082 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1083 /* Address Error */
1084 mdp->stats.tx_fifo_errors++;
1085 if (netif_msg_tx_err(mdp))
1086 dev_err(&ndev->dev, "Address Error\n");
1087 }
1088
1089 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1090 if (mdp->cd->no_ade)
1091 mask &= ~EESR_ADE;
1092 if (intr_status & mask) {
1093 /* Tx error */
1094 u32 edtrr = sh_eth_read(ndev, EDTRR);
1095 /* dmesg */
1096 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1097 intr_status, mdp->cur_tx);
1098 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1099 mdp->dirty_tx, (u32) ndev->state, edtrr);
1100 /* dirty buffer free */
1101 sh_eth_txfree(ndev);
1102
1103 /* SH7712 BUG */
1104 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1105 /* tx dma start */
1106 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1107 }
1108 /* wakeup */
1109 netif_wake_queue(ndev);
1110 }
1111 }
1112
1113 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1114 {
1115 struct net_device *ndev = netdev;
1116 struct sh_eth_private *mdp = netdev_priv(ndev);
1117 struct sh_eth_cpu_data *cd = mdp->cd;
1118 irqreturn_t ret = IRQ_NONE;
1119 u32 intr_status = 0;
1120
1121 spin_lock(&mdp->lock);
1122
1123 /* Get interrpt stat */
1124 intr_status = sh_eth_read(ndev, EESR);
1125 /* Clear interrupt */
1126 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1127 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1128 cd->tx_check | cd->eesr_err_check)) {
1129 sh_eth_write(ndev, intr_status, EESR);
1130 ret = IRQ_HANDLED;
1131 } else
1132 goto other_irq;
1133
1134 if (intr_status & (EESR_FRC | /* Frame recv*/
1135 EESR_RMAF | /* Multi cast address recv*/
1136 EESR_RRF | /* Bit frame recv */
1137 EESR_RTLF | /* Long frame recv*/
1138 EESR_RTSF | /* short frame recv */
1139 EESR_PRE | /* PHY-LSI recv error */
1140 EESR_CERF)){ /* recv frame CRC error */
1141 sh_eth_rx(ndev);
1142 }
1143
1144 /* Tx Check */
1145 if (intr_status & cd->tx_check) {
1146 sh_eth_txfree(ndev);
1147 netif_wake_queue(ndev);
1148 }
1149
1150 if (intr_status & cd->eesr_err_check)
1151 sh_eth_error(ndev, intr_status);
1152
1153 other_irq:
1154 spin_unlock(&mdp->lock);
1155
1156 return ret;
1157 }
1158
1159 static void sh_eth_timer(unsigned long data)
1160 {
1161 struct net_device *ndev = (struct net_device *)data;
1162 struct sh_eth_private *mdp = netdev_priv(ndev);
1163
1164 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1165 }
1166
1167 /* PHY state control function */
1168 static void sh_eth_adjust_link(struct net_device *ndev)
1169 {
1170 struct sh_eth_private *mdp = netdev_priv(ndev);
1171 struct phy_device *phydev = mdp->phydev;
1172 int new_state = 0;
1173
1174 if (phydev->link != PHY_DOWN) {
1175 if (phydev->duplex != mdp->duplex) {
1176 new_state = 1;
1177 mdp->duplex = phydev->duplex;
1178 if (mdp->cd->set_duplex)
1179 mdp->cd->set_duplex(ndev);
1180 }
1181
1182 if (phydev->speed != mdp->speed) {
1183 new_state = 1;
1184 mdp->speed = phydev->speed;
1185 if (mdp->cd->set_rate)
1186 mdp->cd->set_rate(ndev);
1187 }
1188 if (mdp->link == PHY_DOWN) {
1189 sh_eth_write(ndev,
1190 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1191 new_state = 1;
1192 mdp->link = phydev->link;
1193 }
1194 } else if (mdp->link) {
1195 new_state = 1;
1196 mdp->link = PHY_DOWN;
1197 mdp->speed = 0;
1198 mdp->duplex = -1;
1199 }
1200
1201 if (new_state && netif_msg_link(mdp))
1202 phy_print_status(phydev);
1203 }
1204
1205 /* PHY init function */
1206 static int sh_eth_phy_init(struct net_device *ndev)
1207 {
1208 struct sh_eth_private *mdp = netdev_priv(ndev);
1209 char phy_id[MII_BUS_ID_SIZE + 3];
1210 struct phy_device *phydev = NULL;
1211
1212 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1213 mdp->mii_bus->id , mdp->phy_id);
1214
1215 mdp->link = PHY_DOWN;
1216 mdp->speed = 0;
1217 mdp->duplex = -1;
1218
1219 /* Try connect to PHY */
1220 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1221 0, mdp->phy_interface);
1222 if (IS_ERR(phydev)) {
1223 dev_err(&ndev->dev, "phy_connect failed\n");
1224 return PTR_ERR(phydev);
1225 }
1226
1227 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1228 phydev->addr, phydev->drv->name);
1229
1230 mdp->phydev = phydev;
1231
1232 return 0;
1233 }
1234
1235 /* PHY control start function */
1236 static int sh_eth_phy_start(struct net_device *ndev)
1237 {
1238 struct sh_eth_private *mdp = netdev_priv(ndev);
1239 int ret;
1240
1241 ret = sh_eth_phy_init(ndev);
1242 if (ret)
1243 return ret;
1244
1245 /* reset phy - this also wakes it from PDOWN */
1246 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1247 phy_start(mdp->phydev);
1248
1249 return 0;
1250 }
1251
1252 static int sh_eth_get_settings(struct net_device *ndev,
1253 struct ethtool_cmd *ecmd)
1254 {
1255 struct sh_eth_private *mdp = netdev_priv(ndev);
1256 unsigned long flags;
1257 int ret;
1258
1259 spin_lock_irqsave(&mdp->lock, flags);
1260 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1261 spin_unlock_irqrestore(&mdp->lock, flags);
1262
1263 return ret;
1264 }
1265
1266 static int sh_eth_set_settings(struct net_device *ndev,
1267 struct ethtool_cmd *ecmd)
1268 {
1269 struct sh_eth_private *mdp = netdev_priv(ndev);
1270 unsigned long flags;
1271 int ret;
1272
1273 spin_lock_irqsave(&mdp->lock, flags);
1274
1275 /* disable tx and rx */
1276 sh_eth_rcv_snd_disable(ndev);
1277
1278 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1279 if (ret)
1280 goto error_exit;
1281
1282 if (ecmd->duplex == DUPLEX_FULL)
1283 mdp->duplex = 1;
1284 else
1285 mdp->duplex = 0;
1286
1287 if (mdp->cd->set_duplex)
1288 mdp->cd->set_duplex(ndev);
1289
1290 error_exit:
1291 mdelay(1);
1292
1293 /* enable tx and rx */
1294 sh_eth_rcv_snd_enable(ndev);
1295
1296 spin_unlock_irqrestore(&mdp->lock, flags);
1297
1298 return ret;
1299 }
1300
1301 static int sh_eth_nway_reset(struct net_device *ndev)
1302 {
1303 struct sh_eth_private *mdp = netdev_priv(ndev);
1304 unsigned long flags;
1305 int ret;
1306
1307 spin_lock_irqsave(&mdp->lock, flags);
1308 ret = phy_start_aneg(mdp->phydev);
1309 spin_unlock_irqrestore(&mdp->lock, flags);
1310
1311 return ret;
1312 }
1313
1314 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1315 {
1316 struct sh_eth_private *mdp = netdev_priv(ndev);
1317 return mdp->msg_enable;
1318 }
1319
1320 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1321 {
1322 struct sh_eth_private *mdp = netdev_priv(ndev);
1323 mdp->msg_enable = value;
1324 }
1325
1326 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1327 "rx_current", "tx_current",
1328 "rx_dirty", "tx_dirty",
1329 };
1330 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1331
1332 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1333 {
1334 switch (sset) {
1335 case ETH_SS_STATS:
1336 return SH_ETH_STATS_LEN;
1337 default:
1338 return -EOPNOTSUPP;
1339 }
1340 }
1341
1342 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1343 struct ethtool_stats *stats, u64 *data)
1344 {
1345 struct sh_eth_private *mdp = netdev_priv(ndev);
1346 int i = 0;
1347
1348 /* device-specific stats */
1349 data[i++] = mdp->cur_rx;
1350 data[i++] = mdp->cur_tx;
1351 data[i++] = mdp->dirty_rx;
1352 data[i++] = mdp->dirty_tx;
1353 }
1354
1355 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1356 {
1357 switch (stringset) {
1358 case ETH_SS_STATS:
1359 memcpy(data, *sh_eth_gstrings_stats,
1360 sizeof(sh_eth_gstrings_stats));
1361 break;
1362 }
1363 }
1364
1365 static struct ethtool_ops sh_eth_ethtool_ops = {
1366 .get_settings = sh_eth_get_settings,
1367 .set_settings = sh_eth_set_settings,
1368 .nway_reset = sh_eth_nway_reset,
1369 .get_msglevel = sh_eth_get_msglevel,
1370 .set_msglevel = sh_eth_set_msglevel,
1371 .get_link = ethtool_op_get_link,
1372 .get_strings = sh_eth_get_strings,
1373 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1374 .get_sset_count = sh_eth_get_sset_count,
1375 };
1376
1377 /* network device open function */
1378 static int sh_eth_open(struct net_device *ndev)
1379 {
1380 int ret = 0;
1381 struct sh_eth_private *mdp = netdev_priv(ndev);
1382
1383 pm_runtime_get_sync(&mdp->pdev->dev);
1384
1385 ret = request_irq(ndev->irq, sh_eth_interrupt,
1386 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1387 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1388 defined(CONFIG_CPU_SUBTYPE_SH7757)
1389 IRQF_SHARED,
1390 #else
1391 0,
1392 #endif
1393 ndev->name, ndev);
1394 if (ret) {
1395 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1396 return ret;
1397 }
1398
1399 /* Descriptor set */
1400 ret = sh_eth_ring_init(ndev);
1401 if (ret)
1402 goto out_free_irq;
1403
1404 /* device init */
1405 ret = sh_eth_dev_init(ndev);
1406 if (ret)
1407 goto out_free_irq;
1408
1409 /* PHY control start*/
1410 ret = sh_eth_phy_start(ndev);
1411 if (ret)
1412 goto out_free_irq;
1413
1414 /* Set the timer to check for link beat. */
1415 init_timer(&mdp->timer);
1416 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1417 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1418
1419 return ret;
1420
1421 out_free_irq:
1422 free_irq(ndev->irq, ndev);
1423 pm_runtime_put_sync(&mdp->pdev->dev);
1424 return ret;
1425 }
1426
1427 /* Timeout function */
1428 static void sh_eth_tx_timeout(struct net_device *ndev)
1429 {
1430 struct sh_eth_private *mdp = netdev_priv(ndev);
1431 struct sh_eth_rxdesc *rxdesc;
1432 int i;
1433
1434 netif_stop_queue(ndev);
1435
1436 if (netif_msg_timer(mdp))
1437 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1438 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1439
1440 /* tx_errors count up */
1441 mdp->stats.tx_errors++;
1442
1443 /* timer off */
1444 del_timer_sync(&mdp->timer);
1445
1446 /* Free all the skbuffs in the Rx queue. */
1447 for (i = 0; i < RX_RING_SIZE; i++) {
1448 rxdesc = &mdp->rx_ring[i];
1449 rxdesc->status = 0;
1450 rxdesc->addr = 0xBADF00D0;
1451 if (mdp->rx_skbuff[i])
1452 dev_kfree_skb(mdp->rx_skbuff[i]);
1453 mdp->rx_skbuff[i] = NULL;
1454 }
1455 for (i = 0; i < TX_RING_SIZE; i++) {
1456 if (mdp->tx_skbuff[i])
1457 dev_kfree_skb(mdp->tx_skbuff[i]);
1458 mdp->tx_skbuff[i] = NULL;
1459 }
1460
1461 /* device init */
1462 sh_eth_dev_init(ndev);
1463
1464 /* timer on */
1465 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1466 add_timer(&mdp->timer);
1467 }
1468
1469 /* Packet transmit function */
1470 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1471 {
1472 struct sh_eth_private *mdp = netdev_priv(ndev);
1473 struct sh_eth_txdesc *txdesc;
1474 u32 entry;
1475 unsigned long flags;
1476
1477 spin_lock_irqsave(&mdp->lock, flags);
1478 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1479 if (!sh_eth_txfree(ndev)) {
1480 if (netif_msg_tx_queued(mdp))
1481 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1482 netif_stop_queue(ndev);
1483 spin_unlock_irqrestore(&mdp->lock, flags);
1484 return NETDEV_TX_BUSY;
1485 }
1486 }
1487 spin_unlock_irqrestore(&mdp->lock, flags);
1488
1489 entry = mdp->cur_tx % TX_RING_SIZE;
1490 mdp->tx_skbuff[entry] = skb;
1491 txdesc = &mdp->tx_ring[entry];
1492 txdesc->addr = virt_to_phys(skb->data);
1493 /* soft swap. */
1494 if (!mdp->cd->hw_swap)
1495 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1496 skb->len + 2);
1497 /* write back */
1498 __flush_purge_region(skb->data, skb->len);
1499 if (skb->len < ETHERSMALL)
1500 txdesc->buffer_length = ETHERSMALL;
1501 else
1502 txdesc->buffer_length = skb->len;
1503
1504 if (entry >= TX_RING_SIZE - 1)
1505 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1506 else
1507 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1508
1509 mdp->cur_tx++;
1510
1511 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1512 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1513
1514 return NETDEV_TX_OK;
1515 }
1516
1517 /* device close function */
1518 static int sh_eth_close(struct net_device *ndev)
1519 {
1520 struct sh_eth_private *mdp = netdev_priv(ndev);
1521 int ringsize;
1522
1523 netif_stop_queue(ndev);
1524
1525 /* Disable interrupts by clearing the interrupt mask. */
1526 sh_eth_write(ndev, 0x0000, EESIPR);
1527
1528 /* Stop the chip's Tx and Rx processes. */
1529 sh_eth_write(ndev, 0, EDTRR);
1530 sh_eth_write(ndev, 0, EDRRR);
1531
1532 /* PHY Disconnect */
1533 if (mdp->phydev) {
1534 phy_stop(mdp->phydev);
1535 phy_disconnect(mdp->phydev);
1536 }
1537
1538 free_irq(ndev->irq, ndev);
1539
1540 del_timer_sync(&mdp->timer);
1541
1542 /* Free all the skbuffs in the Rx queue. */
1543 sh_eth_ring_free(ndev);
1544
1545 /* free DMA buffer */
1546 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1547 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1548
1549 /* free DMA buffer */
1550 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1551 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1552
1553 pm_runtime_put_sync(&mdp->pdev->dev);
1554
1555 return 0;
1556 }
1557
1558 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1559 {
1560 struct sh_eth_private *mdp = netdev_priv(ndev);
1561
1562 pm_runtime_get_sync(&mdp->pdev->dev);
1563
1564 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1565 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1566 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1567 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1568 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1569 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1570 if (sh_eth_is_gether(mdp)) {
1571 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1572 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1573 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1574 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1575 } else {
1576 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1577 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1578 }
1579 pm_runtime_put_sync(&mdp->pdev->dev);
1580
1581 return &mdp->stats;
1582 }
1583
1584 /* ioctl to device funciotn*/
1585 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1586 int cmd)
1587 {
1588 struct sh_eth_private *mdp = netdev_priv(ndev);
1589 struct phy_device *phydev = mdp->phydev;
1590
1591 if (!netif_running(ndev))
1592 return -EINVAL;
1593
1594 if (!phydev)
1595 return -ENODEV;
1596
1597 return phy_mii_ioctl(phydev, rq, cmd);
1598 }
1599
1600 #if defined(SH_ETH_HAS_TSU)
1601 /* Multicast reception directions set */
1602 static void sh_eth_set_multicast_list(struct net_device *ndev)
1603 {
1604 if (ndev->flags & IFF_PROMISC) {
1605 /* Set promiscuous. */
1606 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1607 ECMR_PRM, ECMR);
1608 } else {
1609 /* Normal, unicast/broadcast-only mode. */
1610 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1611 ECMR_MCT, ECMR);
1612 }
1613 }
1614 #endif /* SH_ETH_HAS_TSU */
1615
1616 /* SuperH's TSU register init function */
1617 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
1618 {
1619 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1620 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1621 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1622 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1623 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1624 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1625 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1626 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1627 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1628 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
1629 if (sh_eth_is_gether(mdp)) {
1630 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1631 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1632 } else {
1633 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1634 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1635 }
1636 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1637 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1638 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1639 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1640 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1641 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1642 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
1643 }
1644
1645 /* MDIO bus release function */
1646 static int sh_mdio_release(struct net_device *ndev)
1647 {
1648 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1649
1650 /* unregister mdio bus */
1651 mdiobus_unregister(bus);
1652
1653 /* remove mdio bus info from net_device */
1654 dev_set_drvdata(&ndev->dev, NULL);
1655
1656 /* free interrupts memory */
1657 kfree(bus->irq);
1658
1659 /* free bitbang info */
1660 free_mdio_bitbang(bus);
1661
1662 return 0;
1663 }
1664
1665 /* MDIO bus init function */
1666 static int sh_mdio_init(struct net_device *ndev, int id,
1667 struct sh_eth_plat_data *pd)
1668 {
1669 int ret, i;
1670 struct bb_info *bitbang;
1671 struct sh_eth_private *mdp = netdev_priv(ndev);
1672
1673 /* create bit control struct for PHY */
1674 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1675 if (!bitbang) {
1676 ret = -ENOMEM;
1677 goto out;
1678 }
1679
1680 /* bitbang init */
1681 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
1682 bitbang->set_gate = pd->set_mdio_gate;
1683 bitbang->mdi_msk = 0x08;
1684 bitbang->mdo_msk = 0x04;
1685 bitbang->mmd_msk = 0x02;/* MMD */
1686 bitbang->mdc_msk = 0x01;
1687 bitbang->ctrl.ops = &bb_ops;
1688
1689 /* MII controller setting */
1690 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1691 if (!mdp->mii_bus) {
1692 ret = -ENOMEM;
1693 goto out_free_bitbang;
1694 }
1695
1696 /* Hook up MII support for ethtool */
1697 mdp->mii_bus->name = "sh_mii";
1698 mdp->mii_bus->parent = &ndev->dev;
1699 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1700
1701 /* PHY IRQ */
1702 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1703 if (!mdp->mii_bus->irq) {
1704 ret = -ENOMEM;
1705 goto out_free_bus;
1706 }
1707
1708 for (i = 0; i < PHY_MAX_ADDR; i++)
1709 mdp->mii_bus->irq[i] = PHY_POLL;
1710
1711 /* regist mdio bus */
1712 ret = mdiobus_register(mdp->mii_bus);
1713 if (ret)
1714 goto out_free_irq;
1715
1716 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1717
1718 return 0;
1719
1720 out_free_irq:
1721 kfree(mdp->mii_bus->irq);
1722
1723 out_free_bus:
1724 free_mdio_bitbang(mdp->mii_bus);
1725
1726 out_free_bitbang:
1727 kfree(bitbang);
1728
1729 out:
1730 return ret;
1731 }
1732
1733 static const u16 *sh_eth_get_register_offset(int register_type)
1734 {
1735 const u16 *reg_offset = NULL;
1736
1737 switch (register_type) {
1738 case SH_ETH_REG_GIGABIT:
1739 reg_offset = sh_eth_offset_gigabit;
1740 break;
1741 case SH_ETH_REG_FAST_SH4:
1742 reg_offset = sh_eth_offset_fast_sh4;
1743 break;
1744 case SH_ETH_REG_FAST_SH3_SH2:
1745 reg_offset = sh_eth_offset_fast_sh3_sh2;
1746 break;
1747 default:
1748 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1749 break;
1750 }
1751
1752 return reg_offset;
1753 }
1754
1755 static const struct net_device_ops sh_eth_netdev_ops = {
1756 .ndo_open = sh_eth_open,
1757 .ndo_stop = sh_eth_close,
1758 .ndo_start_xmit = sh_eth_start_xmit,
1759 .ndo_get_stats = sh_eth_get_stats,
1760 #if defined(SH_ETH_HAS_TSU)
1761 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1762 #endif
1763 .ndo_tx_timeout = sh_eth_tx_timeout,
1764 .ndo_do_ioctl = sh_eth_do_ioctl,
1765 .ndo_validate_addr = eth_validate_addr,
1766 .ndo_set_mac_address = eth_mac_addr,
1767 .ndo_change_mtu = eth_change_mtu,
1768 };
1769
1770 static int sh_eth_drv_probe(struct platform_device *pdev)
1771 {
1772 int ret, devno = 0;
1773 struct resource *res;
1774 struct net_device *ndev = NULL;
1775 struct sh_eth_private *mdp;
1776 struct sh_eth_plat_data *pd;
1777
1778 /* get base addr */
1779 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1780 if (unlikely(res == NULL)) {
1781 dev_err(&pdev->dev, "invalid resource\n");
1782 ret = -EINVAL;
1783 goto out;
1784 }
1785
1786 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1787 if (!ndev) {
1788 dev_err(&pdev->dev, "Could not allocate device.\n");
1789 ret = -ENOMEM;
1790 goto out;
1791 }
1792
1793 /* The sh Ether-specific entries in the device structure. */
1794 ndev->base_addr = res->start;
1795 devno = pdev->id;
1796 if (devno < 0)
1797 devno = 0;
1798
1799 ndev->dma = -1;
1800 ret = platform_get_irq(pdev, 0);
1801 if (ret < 0) {
1802 ret = -ENODEV;
1803 goto out_release;
1804 }
1805 ndev->irq = ret;
1806
1807 SET_NETDEV_DEV(ndev, &pdev->dev);
1808
1809 /* Fill in the fields of the device structure with ethernet values. */
1810 ether_setup(ndev);
1811
1812 mdp = netdev_priv(ndev);
1813 spin_lock_init(&mdp->lock);
1814 mdp->pdev = pdev;
1815 pm_runtime_enable(&pdev->dev);
1816 pm_runtime_resume(&pdev->dev);
1817
1818 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1819 /* get PHY ID */
1820 mdp->phy_id = pd->phy;
1821 mdp->phy_interface = pd->phy_interface;
1822 /* EDMAC endian */
1823 mdp->edmac_endian = pd->edmac_endian;
1824 mdp->no_ether_link = pd->no_ether_link;
1825 mdp->ether_link_active_low = pd->ether_link_active_low;
1826 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
1827
1828 /* set cpu data */
1829 #if defined(SH_ETH_HAS_BOTH_MODULES)
1830 mdp->cd = sh_eth_get_cpu_data(mdp);
1831 #else
1832 mdp->cd = &sh_eth_my_cpu_data;
1833 #endif
1834 sh_eth_set_default_cpu_data(mdp->cd);
1835
1836 /* set function */
1837 ndev->netdev_ops = &sh_eth_netdev_ops;
1838 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1839 ndev->watchdog_timeo = TX_TIMEOUT;
1840
1841 /* debug message level */
1842 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1843 mdp->post_rx = POST_RX >> (devno << 1);
1844 mdp->post_fw = POST_FW >> (devno << 1);
1845
1846 /* read and set MAC address */
1847 read_mac_address(ndev, pd->mac_addr);
1848
1849 /* First device only init */
1850 if (!devno) {
1851 if (mdp->cd->tsu) {
1852 struct resource *rtsu;
1853 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1854 if (!rtsu) {
1855 dev_err(&pdev->dev, "Not found TSU resource\n");
1856 goto out_release;
1857 }
1858 mdp->tsu_addr = ioremap(rtsu->start,
1859 resource_size(rtsu));
1860 }
1861 if (mdp->cd->chip_reset)
1862 mdp->cd->chip_reset(ndev);
1863
1864 if (mdp->cd->tsu) {
1865 /* TSU init (Init only)*/
1866 sh_eth_tsu_init(mdp);
1867 }
1868 }
1869
1870 /* network device register */
1871 ret = register_netdev(ndev);
1872 if (ret)
1873 goto out_release;
1874
1875 /* mdio bus init */
1876 ret = sh_mdio_init(ndev, pdev->id, pd);
1877 if (ret)
1878 goto out_unregister;
1879
1880 /* print device information */
1881 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1882 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1883
1884 platform_set_drvdata(pdev, ndev);
1885
1886 return ret;
1887
1888 out_unregister:
1889 unregister_netdev(ndev);
1890
1891 out_release:
1892 /* net_dev free */
1893 if (mdp->tsu_addr)
1894 iounmap(mdp->tsu_addr);
1895 if (ndev)
1896 free_netdev(ndev);
1897
1898 out:
1899 return ret;
1900 }
1901
1902 static int sh_eth_drv_remove(struct platform_device *pdev)
1903 {
1904 struct net_device *ndev = platform_get_drvdata(pdev);
1905 struct sh_eth_private *mdp = netdev_priv(ndev);
1906
1907 iounmap(mdp->tsu_addr);
1908 sh_mdio_release(ndev);
1909 unregister_netdev(ndev);
1910 pm_runtime_disable(&pdev->dev);
1911 free_netdev(ndev);
1912 platform_set_drvdata(pdev, NULL);
1913
1914 return 0;
1915 }
1916
1917 static int sh_eth_runtime_nop(struct device *dev)
1918 {
1919 /*
1920 * Runtime PM callback shared between ->runtime_suspend()
1921 * and ->runtime_resume(). Simply returns success.
1922 *
1923 * This driver re-initializes all registers after
1924 * pm_runtime_get_sync() anyway so there is no need
1925 * to save and restore registers here.
1926 */
1927 return 0;
1928 }
1929
1930 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1931 .runtime_suspend = sh_eth_runtime_nop,
1932 .runtime_resume = sh_eth_runtime_nop,
1933 };
1934
1935 static struct platform_driver sh_eth_driver = {
1936 .probe = sh_eth_drv_probe,
1937 .remove = sh_eth_drv_remove,
1938 .driver = {
1939 .name = CARDNAME,
1940 .pm = &sh_eth_dev_pm_ops,
1941 },
1942 };
1943
1944 static int __init sh_eth_init(void)
1945 {
1946 return platform_driver_register(&sh_eth_driver);
1947 }
1948
1949 static void __exit sh_eth_cleanup(void)
1950 {
1951 platform_driver_unregister(&sh_eth_driver);
1952 }
1953
1954 module_init(sh_eth_init);
1955 module_exit(sh_eth_cleanup);
1956
1957 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1958 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1959 MODULE_LICENSE("GPL v2");
Linus' kernel tree