2 * AT91 Power Management
4 * Copyright (C) 2005 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #ifndef __ARCH_ARM_MACH_AT91_PM
12 #define __ARCH_ARM_MACH_AT91_PM
14 #include <mach/at91_ramc.h>
15 #ifdef CONFIG_ARCH_AT91RM9200
16 #include <mach/at91rm9200_sdramc.h>
19 * The AT91RM9200 goes into self-refresh mode with this command, and will
20 * terminate self-refresh automatically on the next SDRAM access.
22 * Self-refresh mode is exited as soon as a memory access is made, but we don't
23 * know for sure when that happens. However, we need to restore the low-power
24 * mode if it was enabled before going idle. Restoring low-power mode while
25 * still in self-refresh is "not recommended", but seems to work.
28 static inline void at91rm9200_standby(void)
30 u32 lpr
= at91_ramc_read(0, AT91RM9200_SDRAMC_LPR
);
35 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
36 " str %0, [%1, %2]\n\t"
37 " str %3, [%1, %4]\n\t"
38 " mcr p15, 0, %0, c7, c0, 4\n\t"
41 : "r" (0), "r" (AT91_BASE_SYS
), "r" (AT91RM9200_SDRAMC_LPR
),
42 "r" (1), "r" (AT91RM9200_SDRAMC_SRR
),
46 #define at91_standby at91rm9200_standby
48 #elif defined(CONFIG_ARCH_AT91SAM9G45)
50 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
53 static inline void at91sam9g45_standby(void)
55 /* Those two values allow us to delay self-refresh activation
58 u32 saved_lpr0
, saved_lpr1
;
60 saved_lpr1
= at91_ramc_read(1, AT91_DDRSDRC_LPR
);
61 lpr1
= saved_lpr1
& ~AT91_DDRSDRC_LPCB
;
62 lpr1
|= AT91_DDRSDRC_LPCB_SELF_REFRESH
;
64 saved_lpr0
= at91_ramc_read(0, AT91_DDRSDRC_LPR
);
65 lpr0
= saved_lpr0
& ~AT91_DDRSDRC_LPCB
;
66 lpr0
|= AT91_DDRSDRC_LPCB_SELF_REFRESH
;
68 /* self-refresh mode now */
69 at91_ramc_write(0, AT91_DDRSDRC_LPR
, lpr0
);
70 at91_ramc_write(1, AT91_DDRSDRC_LPR
, lpr1
);
74 at91_ramc_write(0, AT91_DDRSDRC_LPR
, saved_lpr0
);
75 at91_ramc_write(1, AT91_DDRSDRC_LPR
, saved_lpr1
);
78 #define at91_standby at91sam9g45_standby
82 #ifdef CONFIG_ARCH_AT91SAM9263
84 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
85 * handle those cases both here and in the Suspend-To-RAM support.
87 #warning Assuming EB1 SDRAM controller is *NOT* used
90 static inline void at91sam9_standby(void)
94 saved_lpr
= at91_ramc_read(0, AT91_SDRAMC_LPR
);
96 lpr
= saved_lpr
& ~AT91_SDRAMC_LPCB
;
97 at91_ramc_write(0, AT91_SDRAMC_LPR
, lpr
|
98 AT91_SDRAMC_LPCB_SELF_REFRESH
);
102 at91_ramc_write(0, AT91_SDRAMC_LPR
, saved_lpr
);
105 #define at91_standby at91sam9_standby