arch/arm/mach-at91/pm.h

   1 /*
   2  * AT91 Power Management
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11 #ifndef __ARCH_ARM_MACH_AT91_PM
  12 #define __ARCH_ARM_MACH_AT91_PM
  13
  14 #include <mach/at91_ramc.h>
  15 #ifdef CONFIG_ARCH_AT91RM9200
  16 #include <mach/at91rm9200_sdramc.h>
  17
  18 /*
  19  * The AT91RM9200 goes into self-refresh mode with this command, and will
  20  * terminate self-refresh automatically on the next SDRAM access.
  21  *
  22  * Self-refresh mode is exited as soon as a memory access is made, but we don't
  23  * know for sure when that happens. However, we need to restore the low-power
  24  * mode if it was enabled before going idle. Restoring low-power mode while
  25  * still in self-refresh is "not recommended", but seems to work.
  26  */
  27
  28 static inline void at91rm9200_standby(void)
  29 {
  30         u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
  31
  32         asm volatile(
  33                 "b    1f\n\t"
  34                 ".align    5\n\t"
  35                 "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
  36                 "    str    %0, [%1, %2]\n\t"
  37                 "    str    %3, [%1, %4]\n\t"
  38                 "    mcr    p15, 0, %0, c7, c0, 4\n\t"
  39                 "    str    %5, [%1, %2]"
  40                 :
  41                 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
  42                   "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
  43                   "r" (lpr));
  44 }
  45
  46 #define at91_standby at91rm9200_standby
  47
  48 #elif defined(CONFIG_ARCH_AT91SAM9G45)
  49
  50 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  51  * remember.
  52  */
  53 static inline void at91sam9g45_standby(void)
  54 {
  55         /* Those two values allow us to delay self-refresh activation
  56          * to the maximum. */
  57         u32 lpr0, lpr1;
  58         u32 saved_lpr0, saved_lpr1;
  59
  60         saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
  61         lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
  62         lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  63
  64         saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  65         lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
  66         lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  67
  68         /* self-refresh mode now */
  69         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
  70         at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
  71
  72         cpu_do_idle();
  73
  74         at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
  75         at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
  76 }
  77
  78 #define at91_standby at91sam9g45_standby
  79
  80 #else
  81
  82 #ifdef CONFIG_ARCH_AT91SAM9263
  83 /*
  84  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  85  * handle those cases both here and in the Suspend-To-RAM support.
  86  */
  87 #warning Assuming EB1 SDRAM controller is *NOT* used
  88 #endif
  89
  90 static inline void at91sam9_standby(void)
  91 {
  92         u32 saved_lpr, lpr;
  93
  94         saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
  95
  96         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
  97         at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
  98                         AT91_SDRAMC_LPCB_SELF_REFRESH);
  99
 100         cpu_do_idle();
 101
 102         at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
 103 }
 104
 105 #define at91_standby at91sam9_standby
 106
 107 #endif
 108
 109 #endif