1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/types.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/cpumask.h>
35 #include <linux/aer.h>
37 #include "ixgbe_type.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_dcb.h"
40 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
42 #include "ixgbe_fcoe.h"
43 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
44 #ifdef CONFIG_IXGBE_DCA
45 #include <linux/dca.h>
48 /* common prefix used by pr_<> macros */
50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
52 /* TX/RX descriptor defines */
53 #define IXGBE_DEFAULT_TXD 512
54 #define IXGBE_MAX_TXD 4096
55 #define IXGBE_MIN_TXD 64
57 #define IXGBE_DEFAULT_RXD 512
58 #define IXGBE_MAX_RXD 4096
59 #define IXGBE_MIN_RXD 64
62 #define IXGBE_DEFAULT_FCRTL 0x10000
63 #define IXGBE_MIN_FCRTL 0x40
64 #define IXGBE_MAX_FCRTL 0x7FF80
65 #define IXGBE_DEFAULT_FCRTH 0x20000
66 #define IXGBE_MIN_FCRTH 0x600
67 #define IXGBE_MAX_FCRTH 0x7FFF0
68 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
69 #define IXGBE_MIN_FCPAUSE 0
70 #define IXGBE_MAX_FCPAUSE 0xFFFF
72 /* Supported Rx Buffer Sizes */
73 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
74 #define IXGBE_RXBUFFER_2048 2048
75 #define IXGBE_RXBUFFER_4096 4096
76 #define IXGBE_RXBUFFER_8192 8192
77 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
90 /* How many Rx Buffers do we bundle into one write to the hardware ? */
91 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
93 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
94 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
97 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
99 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
101 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
103 #define IXGBE_MAX_RSC_INT_RATE 162760
105 #define IXGBE_MAX_VF_MC_ENTRIES 30
106 #define IXGBE_MAX_VF_FUNCTIONS 64
107 #define IXGBE_MAX_VFTA_ENTRIES 128
108 #define MAX_EMULATION_MAC_ADDRS 16
109 #define VMDQ_P(p) ((p) + adapter->num_vfs)
111 struct vf_data_storage
{
112 unsigned char vf_mac_addresses
[ETH_ALEN
];
113 u16 vf_mc_hashes
[IXGBE_MAX_VF_MC_ENTRIES
];
114 u16 num_vf_mc_hashes
;
115 u16 default_vf_vlan_id
;
119 u16 pf_vlan
; /* When set, guest VLAN config not allowed. */
123 /* wrapper around a pointer to a socket buffer,
124 * so a DMA handle can be stored along with the buffer */
125 struct ixgbe_tx_buffer
{
128 unsigned long time_stamp
;
134 struct ixgbe_rx_buffer
{
139 unsigned int page_offset
;
142 struct ixgbe_queue_stats
{
148 void *desc
; /* descriptor ring memory */
150 struct ixgbe_tx_buffer
*tx_buffer_info
;
151 struct ixgbe_rx_buffer
*rx_buffer_info
;
155 u16 count
; /* amount of descriptors */
160 u8 queue_index
; /* needed for multiqueue queue management */
162 #define IXGBE_RING_RX_PS_ENABLED (u8)(1)
163 u8 flags
; /* per ring feature flags */
167 unsigned int total_bytes
;
168 unsigned int total_packets
;
170 #ifdef CONFIG_IXGBE_DCA
171 /* cpu for tx queue */
175 u16 work_limit
; /* max work per interrupt */
176 u16 reg_idx
; /* holds the special value that gets
177 * the hardware register offset
178 * associated with this ring, which is
179 * different for DCB and RSS modes
182 struct ixgbe_queue_stats stats
;
183 unsigned long reinit_state
;
185 u64 rsc_count
; /* stat for coalesced packets */
186 u64 rsc_flush
; /* stats for flushed packets */
187 u32 restart_queue
; /* track tx queue restarts */
188 u32 non_eop_descs
; /* track hardware descriptor chaining */
190 unsigned int size
; /* length in bytes */
191 dma_addr_t dma
; /* phys. address of descriptor ring */
192 } ____cacheline_internodealigned_in_smp
;
194 enum ixgbe_ring_f_enum
{
197 RING_F_VMDQ
, /* SR-IOV uses the same ring feature */
202 #endif /* IXGBE_FCOE */
204 RING_F_ARRAY_SIZE
/* must be last in enum set */
207 #define IXGBE_MAX_DCB_INDICES 8
208 #define IXGBE_MAX_RSS_INDICES 16
209 #define IXGBE_MAX_VMDQ_INDICES 64
210 #define IXGBE_MAX_FDIR_INDICES 64
212 #define IXGBE_MAX_FCOE_INDICES 8
213 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
214 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
216 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
217 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
218 #endif /* IXGBE_FCOE */
219 struct ixgbe_ring_feature
{
222 } ____cacheline_internodealigned_in_smp
;
225 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
227 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
229 /* MAX_MSIX_Q_VECTORS of these are allocated,
230 * but we only use one per queue-specific vector.
232 struct ixgbe_q_vector
{
233 struct ixgbe_adapter
*adapter
;
234 unsigned int v_idx
; /* index of q_vector within array, also used for
235 * finding the bit in EICR and friends that
236 * represents the vector for this ring */
237 struct napi_struct napi
;
238 DECLARE_BITMAP(rxr_idx
, MAX_RX_QUEUES
); /* Rx ring indices */
239 DECLARE_BITMAP(txr_idx
, MAX_TX_QUEUES
); /* Tx ring indices */
240 u8 rxr_count
; /* Rx ring count assigned to this vector */
241 u8 txr_count
; /* Tx ring count assigned to this vector */
245 cpumask_var_t affinity_mask
;
248 /* Helper macros to switch between ints/sec and what the register uses.
249 * And yes, it's the same math going both ways. The lowest value
250 * supported by all of the ixgbe hardware is 8.
252 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
253 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
254 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
256 #define IXGBE_DESC_UNUSED(R) \
257 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
258 (R)->next_to_clean - (R)->next_to_use - 1)
260 #define IXGBE_RX_DESC_ADV(R, i) \
261 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
262 #define IXGBE_TX_DESC_ADV(R, i) \
263 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
264 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
265 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
267 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
269 /* Use 3K as the baby jumbo frame size for FCoE */
270 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
271 #endif /* IXGBE_FCOE */
273 #define OTHER_VECTOR 1
274 #define NON_Q_VECTORS (OTHER_VECTOR)
276 #define MAX_MSIX_VECTORS_82599 64
277 #define MAX_MSIX_Q_VECTORS_82599 64
278 #define MAX_MSIX_VECTORS_82598 18
279 #define MAX_MSIX_Q_VECTORS_82598 16
281 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
282 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
284 #define MIN_MSIX_Q_VECTORS 2
285 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
287 /* board specific private data structure */
288 struct ixgbe_adapter
{
289 struct timer_list watchdog_timer
;
290 struct vlan_group
*vlgrp
;
292 struct work_struct reset_task
;
293 struct ixgbe_q_vector
*q_vector
[MAX_MSIX_Q_VECTORS
];
294 char name
[MAX_MSIX_COUNT
][IFNAMSIZ
+ 9];
295 struct ixgbe_dcb_config dcb_cfg
;
296 struct ixgbe_dcb_config temp_dcb_cfg
;
298 enum ixgbe_fc_mode last_lfc_mode
;
300 /* Interrupt Throttle Rate */
307 struct ixgbe_ring
*tx_ring
[MAX_TX_QUEUES
] ____cacheline_aligned_in_smp
;
309 u32 tx_timeout_count
;
316 struct ixgbe_ring
*rx_ring
[MAX_RX_QUEUES
] ____cacheline_aligned_in_smp
;
318 int num_rx_pools
; /* == num_rx_queues in 82598 */
319 int num_rx_queues_per_pool
; /* 1 if 82598, can be many if 82599 */
320 u64 hw_csum_rx_error
;
321 u64 hw_rx_no_dma_resources
;
323 int num_msix_vectors
;
324 int max_msix_q_vectors
; /* true count of q_vectors for device */
325 struct ixgbe_ring_feature ring_feature
[RING_F_ARRAY_SIZE
];
326 struct msix_entry
*msix_entries
;
328 u32 alloc_rx_page_failed
;
329 u32 alloc_rx_buff_failed
;
331 /* Some features need tri-state capability,
332 * thus the additional *_CAPABLE flags.
335 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
336 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
337 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
338 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
339 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
340 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
341 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
342 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
343 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
344 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
345 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
346 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
347 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
348 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
349 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
350 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
351 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
352 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
353 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
354 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
355 #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
356 #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
357 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
358 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
359 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
360 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
361 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
362 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
365 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
366 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
367 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
368 /* default to trying for four seconds */
369 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
371 /* OS defined structs */
372 struct net_device
*netdev
;
373 struct pci_dev
*pdev
;
376 struct ixgbe_ring test_tx_ring
;
377 struct ixgbe_ring test_rx_ring
;
379 /* structs defined in ixgbe_hw.h */
382 struct ixgbe_hw_stats stats
;
384 /* Interrupt Throttle Rate */
390 unsigned int tx_ring_count
;
391 unsigned int rx_ring_count
;
395 unsigned long link_check_timeout
;
397 struct work_struct watchdog_task
;
398 struct work_struct sfp_task
;
399 struct timer_list sfp_timer
;
400 struct work_struct multispeed_fiber_task
;
401 struct work_struct sfp_config_module_task
;
404 spinlock_t fdir_perfect_lock
;
405 struct work_struct fdir_reinit_task
;
407 struct ixgbe_fcoe fcoe
;
408 #endif /* IXGBE_FCOE */
415 struct work_struct check_overtemp_task
;
419 DECLARE_BITMAP(active_vfs
, IXGBE_MAX_VF_FUNCTIONS
);
420 unsigned int num_vfs
;
421 struct vf_data_storage
*vfinfo
;
428 __IXGBE_FDIR_INIT_DONE
,
429 __IXGBE_SFP_MODULE_NOT_FOUND
437 extern struct ixgbe_info ixgbe_82598_info
;
438 extern struct ixgbe_info ixgbe_82599_info
;
439 #ifdef CONFIG_IXGBE_DCB
440 extern const struct dcbnl_rtnl_ops dcbnl_ops
;
441 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config
*src_dcb_cfg
,
442 struct ixgbe_dcb_config
*dst_dcb_cfg
,
446 extern char ixgbe_driver_name
[];
447 extern const char ixgbe_driver_version
[];
449 extern int ixgbe_up(struct ixgbe_adapter
*adapter
);
450 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
451 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
452 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
453 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
454 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
455 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
456 extern void ixgbe_free_rx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
457 extern void ixgbe_free_tx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
458 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
459 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
460 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
461 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
);
462 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
);
463 extern netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*,
465 struct ixgbe_adapter
*,
466 struct ixgbe_ring
*);
467 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*,
468 struct ixgbe_tx_buffer
*);
469 extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
470 struct ixgbe_ring
*rx_ring
,
472 extern void ixgbe_write_eitr(struct ixgbe_q_vector
*);
473 extern int ethtool_ioctl(struct ifreq
*ifr
);
474 extern s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
);
475 extern s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
);
476 extern s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
);
477 extern s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
478 struct ixgbe_atr_input
*input
,
480 extern s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
481 struct ixgbe_atr_input
*input
,
482 struct ixgbe_atr_input_masks
*input_masks
,
483 u16 soft_id
, u8 queue
);
484 extern s32
ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input
*input
,
486 extern s32
ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input
*input
,
488 extern s32
ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input
*input
,
490 extern s32
ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input
*input
,
492 extern s32
ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input
*input
,
494 extern s32
ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input
*input
,
496 extern s32
ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input
*input
,
498 extern void ixgbe_set_rx_mode(struct net_device
*netdev
);
500 extern void ixgbe_configure_fcoe(struct ixgbe_adapter
*adapter
);
501 extern int ixgbe_fso(struct ixgbe_adapter
*adapter
,
502 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
503 u32 tx_flags
, u8
*hdr_len
);
504 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter
*adapter
);
505 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter
*adapter
,
506 union ixgbe_adv_rx_desc
*rx_desc
,
507 struct sk_buff
*skb
);
508 extern int ixgbe_fcoe_ddp_get(struct net_device
*netdev
, u16 xid
,
509 struct scatterlist
*sgl
, unsigned int sgc
);
510 extern int ixgbe_fcoe_ddp_put(struct net_device
*netdev
, u16 xid
);
511 extern int ixgbe_fcoe_enable(struct net_device
*netdev
);
512 extern int ixgbe_fcoe_disable(struct net_device
*netdev
);
513 #ifdef CONFIG_IXGBE_DCB
514 extern u8
ixgbe_fcoe_getapp(struct ixgbe_adapter
*adapter
);
515 extern u8
ixgbe_fcoe_setapp(struct ixgbe_adapter
*adapter
, u8 up
);
516 #endif /* CONFIG_IXGBE_DCB */
517 extern int ixgbe_fcoe_get_wwn(struct net_device
*netdev
, u64
*wwn
, int type
);
518 #endif /* IXGBE_FCOE */
520 #endif /* _IXGBE_H_ */