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Merge branch 'for-3.11' of git://linux-nfs.org/~bfields/linux
[linux-2.6.git] / drivers / usb / phy / phy-tegra-usb.c
blobcec0855ed24852f3d33b7a38970bf7dc4c13a728
1 /*
2 * Copyright (C) 2010 Google, Inc.
3 * Copyright (C) 2013 NVIDIA Corporation
4 *
5 * Author:
6 * Erik Gilling <konkers@google.com>
7 * Benoit Goby <benoit@android.com>
8 * Venu Byravarasu <vbyravarasu@nvidia.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21 #include <linux/resource.h>
22 #include <linux/delay.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/export.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/gpio.h>
30 #include <linux/of.h>
31 #include <linux/of_gpio.h>
32 #include <linux/usb/otg.h>
33 #include <linux/usb/ulpi.h>
34 #include <asm/mach-types.h>
35 #include <linux/usb/ehci_def.h>
36 #include <linux/usb/tegra_usb_phy.h>
37
38 #define ULPI_VIEWPORT 0x170
39
40 /* PORTSC registers */
41 #define TEGRA_USB_PORTSC1 0x184
42 #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
43 #define TEGRA_USB_PORTSC1_PHCD (1 << 23)
44
45 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
46 #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
47
48 #define USB_SUSP_CTRL 0x400
49 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
50 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
51 #define USB_SUSP_CLR (1 << 5)
52 #define USB_PHY_CLK_VALID (1 << 7)
53 #define UTMIP_RESET (1 << 11)
54 #define UHSIC_RESET (1 << 11)
55 #define UTMIP_PHY_ENABLE (1 << 12)
56 #define ULPI_PHY_ENABLE (1 << 13)
57 #define USB_SUSP_SET (1 << 14)
58 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
59
60 #define USB1_LEGACY_CTRL 0x410
61 #define USB1_NO_LEGACY_MODE (1 << 0)
62 #define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
63 #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
64 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
65 (1 << 1)
66 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
67 #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
68
69 #define ULPI_TIMING_CTRL_0 0x424
70 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
71 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
72
73 #define ULPI_TIMING_CTRL_1 0x428
74 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
75 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
76 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
77 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
78 #define ULPI_DIR_TRIMMER_LOAD (1 << 24)
79 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
80
81 #define UTMIP_PLL_CFG1 0x804
82 #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
83 #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
84
85 #define UTMIP_XCVR_CFG0 0x808
86 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
87 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
88 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
89 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
90 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
91 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
92 #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
93
94 #define UTMIP_BIAS_CFG0 0x80c
95 #define UTMIP_OTGPD (1 << 11)
96 #define UTMIP_BIASPD (1 << 10)
97
98 #define UTMIP_HSRX_CFG0 0x810
99 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
100 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
101
102 #define UTMIP_HSRX_CFG1 0x814
103 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
104
105 #define UTMIP_TX_CFG0 0x820
106 #define UTMIP_FS_PREABMLE_J (1 << 19)
107 #define UTMIP_HS_DISCON_DISABLE (1 << 8)
108
109 #define UTMIP_MISC_CFG0 0x824
110 #define UTMIP_DPDM_OBSERVE (1 << 26)
111 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
112 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
113 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
114 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
115 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
116 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
117
118 #define UTMIP_MISC_CFG1 0x828
119 #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
120 #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
121
122 #define UTMIP_DEBOUNCE_CFG0 0x82c
123 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
124
125 #define UTMIP_BAT_CHRG_CFG0 0x830
126 #define UTMIP_PD_CHRG (1 << 0)
127
128 #define UTMIP_SPARE_CFG0 0x834
129 #define FUSE_SETUP_SEL (1 << 3)
130
131 #define UTMIP_XCVR_CFG1 0x838
132 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
133 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
134 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
135 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
136
137 #define UTMIP_BIAS_CFG1 0x83c
138 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
139
140 static DEFINE_SPINLOCK(utmip_pad_lock);
141 static int utmip_pad_count;
142
143 struct tegra_xtal_freq {
144 int freq;
145 u8 enable_delay;
146 u8 stable_count;
147 u8 active_delay;
148 u8 xtal_freq_count;
149 u16 debounce;
150 };
151
152 static const struct tegra_xtal_freq tegra_freq_table[] = {
153 {
154 .freq = 12000000,
155 .enable_delay = 0x02,
156 .stable_count = 0x2F,
157 .active_delay = 0x04,
158 .xtal_freq_count = 0x76,
159 .debounce = 0x7530,
160 },
161 {
162 .freq = 13000000,
163 .enable_delay = 0x02,
164 .stable_count = 0x33,
165 .active_delay = 0x05,
166 .xtal_freq_count = 0x7F,
167 .debounce = 0x7EF4,
168 },
169 {
170 .freq = 19200000,
171 .enable_delay = 0x03,
172 .stable_count = 0x4B,
173 .active_delay = 0x06,
174 .xtal_freq_count = 0xBB,
175 .debounce = 0xBB80,
176 },
177 {
178 .freq = 26000000,
179 .enable_delay = 0x04,
180 .stable_count = 0x66,
181 .active_delay = 0x09,
182 .xtal_freq_count = 0xFE,
183 .debounce = 0xFDE8,
184 },
185 };
186
187 static struct tegra_utmip_config utmip_default[] = {
188 [0] = {
189 .hssync_start_delay = 9,
190 .idle_wait_delay = 17,
191 .elastic_limit = 16,
192 .term_range_adj = 6,
193 .xcvr_setup = 9,
194 .xcvr_lsfslew = 1,
195 .xcvr_lsrslew = 1,
196 },
197 [2] = {
198 .hssync_start_delay = 9,
199 .idle_wait_delay = 17,
200 .elastic_limit = 16,
201 .term_range_adj = 6,
202 .xcvr_setup = 9,
203 .xcvr_lsfslew = 2,
204 .xcvr_lsrslew = 2,
205 },
206 };
207
208 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
209 {
210 void __iomem *base = phy->regs;
211 unsigned long val;
212
213 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
214 val &= ~TEGRA_USB_PORTSC1_PTS(3);
215 val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
216 writel(val, base + TEGRA_USB_PORTSC1);
217 }
218
219 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
220 {
221 void __iomem *base = phy->regs;
222 unsigned long val;
223
224 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
225 if (enable)
226 val |= TEGRA_USB_PORTSC1_PHCD;
227 else
228 val &= ~TEGRA_USB_PORTSC1_PHCD;
229 writel(val, base + TEGRA_USB_PORTSC1);
230 }
231
232 static int utmip_pad_open(struct tegra_usb_phy *phy)
233 {
234 phy->pad_clk = devm_clk_get(phy->dev, "utmi-pads");
235 if (IS_ERR(phy->pad_clk)) {
236 pr_err("%s: can't get utmip pad clock\n", __func__);
237 return PTR_ERR(phy->pad_clk);
238 }
239
240 return 0;
241 }
242
243 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
244 {
245 unsigned long val, flags;
246 void __iomem *base = phy->pad_regs;
247
248 clk_prepare_enable(phy->pad_clk);
249
250 spin_lock_irqsave(&utmip_pad_lock, flags);
251
252 if (utmip_pad_count++ == 0) {
253 val = readl(base + UTMIP_BIAS_CFG0);
254 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
255 writel(val, base + UTMIP_BIAS_CFG0);
256 }
257
258 spin_unlock_irqrestore(&utmip_pad_lock, flags);
259
260 clk_disable_unprepare(phy->pad_clk);
261 }
262
263 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
264 {
265 unsigned long val, flags;
266 void __iomem *base = phy->pad_regs;
267
268 if (!utmip_pad_count) {
269 pr_err("%s: utmip pad already powered off\n", __func__);
270 return -EINVAL;
271 }
272
273 clk_prepare_enable(phy->pad_clk);
274
275 spin_lock_irqsave(&utmip_pad_lock, flags);
276
277 if (--utmip_pad_count == 0) {
278 val = readl(base + UTMIP_BIAS_CFG0);
279 val |= UTMIP_OTGPD | UTMIP_BIASPD;
280 writel(val, base + UTMIP_BIAS_CFG0);
281 }
282
283 spin_unlock_irqrestore(&utmip_pad_lock, flags);
284
285 clk_disable_unprepare(phy->pad_clk);
286
287 return 0;
288 }
289
290 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
291 {
292 unsigned long timeout = 2000;
293 do {
294 if ((readl(reg) & mask) == result)
295 return 0;
296 udelay(1);
297 timeout--;
298 } while (timeout);
299 return -1;
300 }
301
302 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
303 {
304 unsigned long val;
305 void __iomem *base = phy->regs;
306
307 if (phy->is_legacy_phy) {
308 val = readl(base + USB_SUSP_CTRL);
309 val |= USB_SUSP_SET;
310 writel(val, base + USB_SUSP_CTRL);
311
312 udelay(10);
313
314 val = readl(base + USB_SUSP_CTRL);
315 val &= ~USB_SUSP_SET;
316 writel(val, base + USB_SUSP_CTRL);
317 } else
318 set_phcd(phy, true);
319
320 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
321 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
322 }
323
324 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
325 {
326 unsigned long val;
327 void __iomem *base = phy->regs;
328
329 if (phy->is_legacy_phy) {
330 val = readl(base + USB_SUSP_CTRL);
331 val |= USB_SUSP_CLR;
332 writel(val, base + USB_SUSP_CTRL);
333
334 udelay(10);
335
336 val = readl(base + USB_SUSP_CTRL);
337 val &= ~USB_SUSP_CLR;
338 writel(val, base + USB_SUSP_CTRL);
339 } else
340 set_phcd(phy, false);
341
342 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
343 USB_PHY_CLK_VALID))
344 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
345 }
346
347 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
348 {
349 unsigned long val;
350 void __iomem *base = phy->regs;
351 struct tegra_utmip_config *config = phy->config;
352
353 val = readl(base + USB_SUSP_CTRL);
354 val |= UTMIP_RESET;
355 writel(val, base + USB_SUSP_CTRL);
356
357 if (phy->is_legacy_phy) {
358 val = readl(base + USB1_LEGACY_CTRL);
359 val |= USB1_NO_LEGACY_MODE;
360 writel(val, base + USB1_LEGACY_CTRL);
361 }
362
363 val = readl(base + UTMIP_TX_CFG0);
364 val &= ~UTMIP_FS_PREABMLE_J;
365 writel(val, base + UTMIP_TX_CFG0);
366
367 val = readl(base + UTMIP_HSRX_CFG0);
368 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
369 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
370 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
371 writel(val, base + UTMIP_HSRX_CFG0);
372
373 val = readl(base + UTMIP_HSRX_CFG1);
374 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
375 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
376 writel(val, base + UTMIP_HSRX_CFG1);
377
378 val = readl(base + UTMIP_DEBOUNCE_CFG0);
379 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
380 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
381 writel(val, base + UTMIP_DEBOUNCE_CFG0);
382
383 val = readl(base + UTMIP_MISC_CFG0);
384 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
385 writel(val, base + UTMIP_MISC_CFG0);
386
387 val = readl(base + UTMIP_MISC_CFG1);
388 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
389 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
390 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
391 writel(val, base + UTMIP_MISC_CFG1);
392
393 val = readl(base + UTMIP_PLL_CFG1);
394 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
395 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
396 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
397 writel(val, base + UTMIP_PLL_CFG1);
398
399 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
400 val = readl(base + USB_SUSP_CTRL);
401 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
402 writel(val, base + USB_SUSP_CTRL);
403 }
404
405 utmip_pad_power_on(phy);
406
407 val = readl(base + UTMIP_XCVR_CFG0);
408 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
409 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
410 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
411 UTMIP_XCVR_HSSLEW_MSB(~0));
412 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
413 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
414 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
415 writel(val, base + UTMIP_XCVR_CFG0);
416
417 val = readl(base + UTMIP_XCVR_CFG1);
418 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
419 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
420 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
421 writel(val, base + UTMIP_XCVR_CFG1);
422
423 val = readl(base + UTMIP_BAT_CHRG_CFG0);
424 val &= ~UTMIP_PD_CHRG;
425 writel(val, base + UTMIP_BAT_CHRG_CFG0);
426
427 val = readl(base + UTMIP_BIAS_CFG1);
428 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
429 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
430 writel(val, base + UTMIP_BIAS_CFG1);
431
432 if (phy->is_legacy_phy) {
433 val = readl(base + UTMIP_SPARE_CFG0);
434 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
435 val &= ~FUSE_SETUP_SEL;
436 else
437 val |= FUSE_SETUP_SEL;
438 writel(val, base + UTMIP_SPARE_CFG0);
439 } else {
440 val = readl(base + USB_SUSP_CTRL);
441 val |= UTMIP_PHY_ENABLE;
442 writel(val, base + USB_SUSP_CTRL);
443 }
444
445 val = readl(base + USB_SUSP_CTRL);
446 val &= ~UTMIP_RESET;
447 writel(val, base + USB_SUSP_CTRL);
448
449 if (phy->is_legacy_phy) {
450 val = readl(base + USB1_LEGACY_CTRL);
451 val &= ~USB1_VBUS_SENSE_CTL_MASK;
452 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
453 writel(val, base + USB1_LEGACY_CTRL);
454
455 val = readl(base + USB_SUSP_CTRL);
456 val &= ~USB_SUSP_SET;
457 writel(val, base + USB_SUSP_CTRL);
458 }
459
460 utmi_phy_clk_enable(phy);
461
462 if (!phy->is_legacy_phy)
463 set_pts(phy, 0);
464
465 return 0;
466 }
467
468 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
469 {
470 unsigned long val;
471 void __iomem *base = phy->regs;
472
473 utmi_phy_clk_disable(phy);
474
475 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
476 val = readl(base + USB_SUSP_CTRL);
477 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
478 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
479 writel(val, base + USB_SUSP_CTRL);
480 }
481
482 val = readl(base + USB_SUSP_CTRL);
483 val |= UTMIP_RESET;
484 writel(val, base + USB_SUSP_CTRL);
485
486 val = readl(base + UTMIP_BAT_CHRG_CFG0);
487 val |= UTMIP_PD_CHRG;
488 writel(val, base + UTMIP_BAT_CHRG_CFG0);
489
490 val = readl(base + UTMIP_XCVR_CFG0);
491 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
492 UTMIP_FORCE_PDZI_POWERDOWN;
493 writel(val, base + UTMIP_XCVR_CFG0);
494
495 val = readl(base + UTMIP_XCVR_CFG1);
496 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
497 UTMIP_FORCE_PDDR_POWERDOWN;
498 writel(val, base + UTMIP_XCVR_CFG1);
499
500 return utmip_pad_power_off(phy);
501 }
502
503 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
504 {
505 unsigned long val;
506 void __iomem *base = phy->regs;
507
508 val = readl(base + UTMIP_TX_CFG0);
509 val |= UTMIP_HS_DISCON_DISABLE;
510 writel(val, base + UTMIP_TX_CFG0);
511 }
512
513 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
514 {
515 unsigned long val;
516 void __iomem *base = phy->regs;
517
518 val = readl(base + UTMIP_TX_CFG0);
519 val &= ~UTMIP_HS_DISCON_DISABLE;
520 writel(val, base + UTMIP_TX_CFG0);
521 }
522
523 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
524 enum tegra_usb_phy_port_speed port_speed)
525 {
526 unsigned long val;
527 void __iomem *base = phy->regs;
528
529 val = readl(base + UTMIP_MISC_CFG0);
530 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
531 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
532 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
533 else
534 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
535 writel(val, base + UTMIP_MISC_CFG0);
536 udelay(1);
537
538 val = readl(base + UTMIP_MISC_CFG0);
539 val |= UTMIP_DPDM_OBSERVE;
540 writel(val, base + UTMIP_MISC_CFG0);
541 udelay(10);
542 }
543
544 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
545 {
546 unsigned long val;
547 void __iomem *base = phy->regs;
548
549 val = readl(base + UTMIP_MISC_CFG0);
550 val &= ~UTMIP_DPDM_OBSERVE;
551 writel(val, base + UTMIP_MISC_CFG0);
552 udelay(10);
553 }
554
555 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
556 {
557 int ret;
558 unsigned long val;
559 void __iomem *base = phy->regs;
560
561 ret = gpio_direction_output(phy->reset_gpio, 0);
562 if (ret < 0) {
563 dev_err(phy->dev, "gpio %d not set to 0\n", phy->reset_gpio);
564 return ret;
565 }
566 msleep(5);
567 ret = gpio_direction_output(phy->reset_gpio, 1);
568 if (ret < 0) {
569 dev_err(phy->dev, "gpio %d not set to 1\n", phy->reset_gpio);
570 return ret;
571 }
572
573 clk_prepare_enable(phy->clk);
574 msleep(1);
575
576 val = readl(base + USB_SUSP_CTRL);
577 val |= UHSIC_RESET;
578 writel(val, base + USB_SUSP_CTRL);
579
580 val = readl(base + ULPI_TIMING_CTRL_0);
581 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
582 writel(val, base + ULPI_TIMING_CTRL_0);
583
584 val = readl(base + USB_SUSP_CTRL);
585 val |= ULPI_PHY_ENABLE;
586 writel(val, base + USB_SUSP_CTRL);
587
588 val = 0;
589 writel(val, base + ULPI_TIMING_CTRL_1);
590
591 val |= ULPI_DATA_TRIMMER_SEL(4);
592 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
593 val |= ULPI_DIR_TRIMMER_SEL(4);
594 writel(val, base + ULPI_TIMING_CTRL_1);
595 udelay(10);
596
597 val |= ULPI_DATA_TRIMMER_LOAD;
598 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
599 val |= ULPI_DIR_TRIMMER_LOAD;
600 writel(val, base + ULPI_TIMING_CTRL_1);
601
602 /* Fix VbusInvalid due to floating VBUS */
603 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
604 if (ret) {
605 pr_err("%s: ulpi write failed\n", __func__);
606 return ret;
607 }
608
609 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
610 if (ret) {
611 pr_err("%s: ulpi write failed\n", __func__);
612 return ret;
613 }
614
615 val = readl(base + USB_SUSP_CTRL);
616 val |= USB_SUSP_CLR;
617 writel(val, base + USB_SUSP_CTRL);
618 udelay(100);
619
620 val = readl(base + USB_SUSP_CTRL);
621 val &= ~USB_SUSP_CLR;
622 writel(val, base + USB_SUSP_CTRL);
623
624 return 0;
625 }
626
627 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
628 {
629 clk_disable(phy->clk);
630 return gpio_direction_output(phy->reset_gpio, 0);
631 }
632
633 static void tegra_usb_phy_close(struct usb_phy *x)
634 {
635 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
636
637 clk_disable_unprepare(phy->pll_u);
638 }
639
640 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
641 {
642 if (phy->is_ulpi_phy)
643 return ulpi_phy_power_on(phy);
644 else
645 return utmi_phy_power_on(phy);
646 }
647
648 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
649 {
650 if (phy->is_ulpi_phy)
651 return ulpi_phy_power_off(phy);
652 else
653 return utmi_phy_power_off(phy);
654 }
655
656 static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
657 {
658 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
659 if (suspend)
660 return tegra_usb_phy_power_off(phy);
661 else
662 return tegra_usb_phy_power_on(phy);
663 }
664
665 static int ulpi_open(struct tegra_usb_phy *phy)
666 {
667 int err;
668
669 phy->clk = devm_clk_get(phy->dev, "ulpi-link");
670 if (IS_ERR(phy->clk)) {
671 pr_err("%s: can't get ulpi clock\n", __func__);
672 return PTR_ERR(phy->clk);
673 }
674
675 err = devm_gpio_request(phy->dev, phy->reset_gpio, "ulpi_phy_reset_b");
676 if (err < 0) {
677 dev_err(phy->dev, "request failed for gpio: %d\n",
678 phy->reset_gpio);
679 return err;
680 }
681
682 err = gpio_direction_output(phy->reset_gpio, 0);
683 if (err < 0) {
684 dev_err(phy->dev, "gpio %d direction not set to output\n",
685 phy->reset_gpio);
686 return err;
687 }
688
689 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
690 if (!phy->ulpi) {
691 dev_err(phy->dev, "otg_ulpi_create returned NULL\n");
692 err = -ENOMEM;
693 return err;
694 }
695
696 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
697 return 0;
698 }
699
700 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
701 {
702 unsigned long parent_rate;
703 int i;
704 int err;
705
706 if (!phy->is_ulpi_phy) {
707 if (phy->is_legacy_phy)
708 phy->config = &utmip_default[0];
709 else
710 phy->config = &utmip_default[2];
711 }
712
713 phy->pll_u = devm_clk_get(phy->dev, "pll_u");
714 if (IS_ERR(phy->pll_u)) {
715 pr_err("Can't get pll_u clock\n");
716 return PTR_ERR(phy->pll_u);
717 }
718
719 err = clk_prepare_enable(phy->pll_u);
720 if (err)
721 return err;
722
723 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
724 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
725 if (tegra_freq_table[i].freq == parent_rate) {
726 phy->freq = &tegra_freq_table[i];
727 break;
728 }
729 }
730 if (!phy->freq) {
731 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
732 err = -EINVAL;
733 goto fail;
734 }
735
736 if (phy->is_ulpi_phy)
737 err = ulpi_open(phy);
738 else
739 err = utmip_pad_open(phy);
740 if (err < 0)
741 goto fail;
742
743 return 0;
744
745 fail:
746 clk_disable_unprepare(phy->pll_u);
747 return err;
748 }
749
750 void tegra_usb_phy_preresume(struct usb_phy *x)
751 {
752 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
753
754 if (!phy->is_ulpi_phy)
755 utmi_phy_preresume(phy);
756 }
757 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
758
759 void tegra_usb_phy_postresume(struct usb_phy *x)
760 {
761 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
762
763 if (!phy->is_ulpi_phy)
764 utmi_phy_postresume(phy);
765 }
766 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
767
768 void tegra_ehci_phy_restore_start(struct usb_phy *x,
769 enum tegra_usb_phy_port_speed port_speed)
770 {
771 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
772
773 if (!phy->is_ulpi_phy)
774 utmi_phy_restore_start(phy, port_speed);
775 }
776 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
777
778 void tegra_ehci_phy_restore_end(struct usb_phy *x)
779 {
780 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
781
782 if (!phy->is_ulpi_phy)
783 utmi_phy_restore_end(phy);
784 }
785 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
786
787 static int tegra_usb_phy_probe(struct platform_device *pdev)
788 {
789 struct resource *res;
790 struct tegra_usb_phy *tegra_phy = NULL;
791 struct device_node *np = pdev->dev.of_node;
792 int err;
793
794 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
795 if (!tegra_phy) {
796 dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
797 return -ENOMEM;
798 }
799
800 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801 if (!res) {
802 dev_err(&pdev->dev, "Failed to get I/O memory\n");
803 return -ENXIO;
804 }
805
806 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
807 resource_size(res));
808 if (!tegra_phy->regs) {
809 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
810 return -ENOMEM;
811 }
812
813 tegra_phy->is_legacy_phy =
814 of_property_read_bool(np, "nvidia,has-legacy-mode");
815
816 err = of_property_match_string(np, "phy_type", "ulpi");
817 if (err < 0) {
818 tegra_phy->is_ulpi_phy = false;
819
820 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
821 if (!res) {
822 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
823 return -ENXIO;
824 }
825
826 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
827 resource_size(res));
828 if (!tegra_phy->regs) {
829 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
830 return -ENOMEM;
831 }
832 } else {
833 tegra_phy->is_ulpi_phy = true;
834
835 tegra_phy->reset_gpio =
836 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
837 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
838 dev_err(&pdev->dev, "invalid gpio: %d\n",
839 tegra_phy->reset_gpio);
840 return tegra_phy->reset_gpio;
841 }
842 }
843
844 err = of_property_match_string(np, "dr_mode", "otg");
845 if (err < 0) {
846 err = of_property_match_string(np, "dr_mode", "peripheral");
847 if (err < 0)
848 tegra_phy->mode = TEGRA_USB_PHY_MODE_HOST;
849 else
850 tegra_phy->mode = TEGRA_USB_PHY_MODE_DEVICE;
851 } else
852 tegra_phy->mode = TEGRA_USB_PHY_MODE_OTG;
853
854 tegra_phy->dev = &pdev->dev;
855 err = tegra_usb_phy_init(tegra_phy);
856 if (err < 0)
857 return err;
858
859 tegra_phy->u_phy.shutdown = tegra_usb_phy_close;
860 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
861
862 dev_set_drvdata(&pdev->dev, tegra_phy);
863 return 0;
864 }
865
866 static struct of_device_id tegra_usb_phy_id_table[] = {
867 { .compatible = "nvidia,tegra20-usb-phy", },
868 { },
869 };
870 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
871
872 static struct platform_driver tegra_usb_phy_driver = {
873 .probe = tegra_usb_phy_probe,
874 .driver = {
875 .name = "tegra-phy",
876 .owner = THIS_MODULE,
877 .of_match_table = of_match_ptr(tegra_usb_phy_id_table),
878 },
879 };
880 module_platform_driver(tegra_usb_phy_driver);
881
882 static int tegra_usb_phy_match(struct device *dev, void *data)
883 {
884 struct tegra_usb_phy *tegra_phy = dev_get_drvdata(dev);
885 struct device_node *dn = data;
886
887 return (tegra_phy->dev->of_node == dn) ? 1 : 0;
888 }
889
890 struct usb_phy *tegra_usb_get_phy(struct device_node *dn)
891 {
892 struct device *dev;
893 struct tegra_usb_phy *tegra_phy;
894
895 dev = driver_find_device(&tegra_usb_phy_driver.driver, NULL, dn,
896 tegra_usb_phy_match);
897 if (!dev)
898 return ERR_PTR(-EPROBE_DEFER);
899
900 tegra_phy = dev_get_drvdata(dev);
901
902 return &tegra_phy->u_phy;
903 }
904 EXPORT_SYMBOL_GPL(tegra_usb_get_phy);
905
906 MODULE_DESCRIPTION("Tegra USB PHY driver");
907 MODULE_LICENSE("GPL v2");
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