| blob | 382a1d74865d288cf26e4b256e67e21be5f3c4cc |
1 /*
2 * hw.h - DesignWare HS OTG Controller hardware definitions
3 *
4 * Copyright 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
37 #ifndef __DWC2_HW_H__
38 #define __DWC2_HW_H__
40 #define HSOTG_REG(x) (x)
42 #define GOTGCTL HSOTG_REG(0x000)
43 #define GOTGCTL_CHIRPEN (1 << 27)
44 #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
45 #define GOTGCTL_MULT_VALID_BC_SHIFT 22
46 #define GOTGCTL_OTGVER (1 << 20)
47 #define GOTGCTL_BSESVLD (1 << 19)
48 #define GOTGCTL_ASESVLD (1 << 18)
49 #define GOTGCTL_DBNC_SHORT (1 << 17)
50 #define GOTGCTL_CONID_B (1 << 16)
51 #define GOTGCTL_DEVHNPEN (1 << 11)
52 #define GOTGCTL_HSTSETHNPEN (1 << 10)
53 #define GOTGCTL_HNPREQ (1 << 9)
54 #define GOTGCTL_HSTNEGSCS (1 << 8)
55 #define GOTGCTL_SESREQ (1 << 1)
56 #define GOTGCTL_SESREQSCS (1 << 0)
58 #define GOTGINT HSOTG_REG(0x004)
59 #define GOTGINT_DBNCE_DONE (1 << 19)
60 #define GOTGINT_A_DEV_TOUT_CHG (1 << 18)
61 #define GOTGINT_HST_NEG_DET (1 << 17)
62 #define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9)
63 #define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8)
64 #define GOTGINT_SES_END_DET (1 << 2)
66 #define GAHBCFG HSOTG_REG(0x008)
67 #define GAHBCFG_AHB_SINGLE (1 << 23)
68 #define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22)
69 #define GAHBCFG_REM_MEM_SUPP (1 << 21)
70 #define GAHBCFG_P_TXF_EMP_LVL (1 << 8)
71 #define GAHBCFG_NP_TXF_EMP_LVL (1 << 7)
72 #define GAHBCFG_DMA_EN (1 << 5)
73 #define GAHBCFG_HBSTLEN_MASK (0xf << 1)
74 #define GAHBCFG_HBSTLEN_SHIFT 1
75 #define GAHBCFG_HBSTLEN_SINGLE (0 << 1)
76 #define GAHBCFG_HBSTLEN_INCR (1 << 1)
77 #define GAHBCFG_HBSTLEN_INCR4 (3 << 1)
78 #define GAHBCFG_HBSTLEN_INCR8 (5 << 1)
79 #define GAHBCFG_HBSTLEN_INCR16 (7 << 1)
80 #define GAHBCFG_GLBL_INTR_EN (1 << 0)
82 #define GUSBCFG HSOTG_REG(0x00C)
83 #define GUSBCFG_FORCEDEVMODE (1 << 30)
84 #define GUSBCFG_FORCEHOSTMODE (1 << 29)
85 #define GUSBCFG_TXENDDELAY (1 << 28)
86 #define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27)
87 #define GUSBCFG_ICUSBCAP (1 << 26)
88 #define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25)
89 #define GUSBCFG_INDICATORPASSTHROUGH (1 << 24)
90 #define GUSBCFG_INDICATORCOMPLEMENT (1 << 23)
91 #define GUSBCFG_TERMSELDLPULSE (1 << 22)
92 #define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21)
93 #define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20)
94 #define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19)
95 #define GUSBCFG_ULPI_AUTO_RES (1 << 18)
96 #define GUSBCFG_ULPI_FS_LS (1 << 17)
97 #define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16)
98 #define GUSBCFG_PHY_LP_CLK_SEL (1 << 15)
99 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
100 #define GUSBCFG_USBTRDTIM_SHIFT 10
101 #define GUSBCFG_HNPCAP (1 << 9)
102 #define GUSBCFG_SRPCAP (1 << 8)
103 #define GUSBCFG_DDRSEL (1 << 7)
104 #define GUSBCFG_PHYSEL (1 << 6)
105 #define GUSBCFG_FSINTF (1 << 5)
106 #define GUSBCFG_ULPI_UTMI_SEL (1 << 4)
107 #define GUSBCFG_PHYIF16 (1 << 3)
108 #define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
109 #define GUSBCFG_TOUTCAL_SHIFT 0
110 #define GUSBCFG_TOUTCAL_LIMIT 0x7
111 #define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
113 #define GRSTCTL HSOTG_REG(0x010)
114 #define GRSTCTL_AHBIDLE (1 << 31)
115 #define GRSTCTL_DMAREQ (1 << 30)
116 #define GRSTCTL_TXFNUM_MASK (0x1f << 6)
117 #define GRSTCTL_TXFNUM_SHIFT 6
118 #define GRSTCTL_TXFNUM_LIMIT 0x1f
119 #define GRSTCTL_TXFNUM(_x) ((_x) << 6)
120 #define GRSTCTL_TXFFLSH (1 << 5)
121 #define GRSTCTL_RXFFLSH (1 << 4)
122 #define GRSTCTL_IN_TKNQ_FLSH (1 << 3)
123 #define GRSTCTL_FRMCNTRRST (1 << 2)
124 #define GRSTCTL_HSFTRST (1 << 1)
125 #define GRSTCTL_CSFTRST (1 << 0)
127 #define GINTSTS HSOTG_REG(0x014)
128 #define GINTMSK HSOTG_REG(0x018)
129 #define GINTSTS_WKUPINT (1 << 31)
130 #define GINTSTS_SESSREQINT (1 << 30)
131 #define GINTSTS_DISCONNINT (1 << 29)
132 #define GINTSTS_CONIDSTSCHNG (1 << 28)
133 #define GINTSTS_LPMTRANRCVD (1 << 27)
134 #define GINTSTS_PTXFEMP (1 << 26)
135 #define GINTSTS_HCHINT (1 << 25)
136 #define GINTSTS_PRTINT (1 << 24)
137 #define GINTSTS_RESETDET (1 << 23)
138 #define GINTSTS_FET_SUSP (1 << 22)
139 #define GINTSTS_INCOMPL_IP (1 << 21)
140 #define GINTSTS_INCOMPL_SOIN (1 << 20)
141 #define GINTSTS_OEPINT (1 << 19)
142 #define GINTSTS_IEPINT (1 << 18)
143 #define GINTSTS_EPMIS (1 << 17)
144 #define GINTSTS_RESTOREDONE (1 << 16)
145 #define GINTSTS_EOPF (1 << 15)
146 #define GINTSTS_ISOUTDROP (1 << 14)
147 #define GINTSTS_ENUMDONE (1 << 13)
148 #define GINTSTS_USBRST (1 << 12)
149 #define GINTSTS_USBSUSP (1 << 11)
150 #define GINTSTS_ERLYSUSP (1 << 10)
151 #define GINTSTS_I2CINT (1 << 9)
152 #define GINTSTS_ULPI_CK_INT (1 << 8)
153 #define GINTSTS_GOUTNAKEFF (1 << 7)
154 #define GINTSTS_GINNAKEFF (1 << 6)
155 #define GINTSTS_NPTXFEMP (1 << 5)
156 #define GINTSTS_RXFLVL (1 << 4)
157 #define GINTSTS_SOF (1 << 3)
158 #define GINTSTS_OTGINT (1 << 2)
159 #define GINTSTS_MODEMIS (1 << 1)
160 #define GINTSTS_CURMODE_HOST (1 << 0)
162 #define GRXSTSR HSOTG_REG(0x01C)
163 #define GRXSTSP HSOTG_REG(0x020)
164 #define GRXSTS_FN_MASK (0x7f << 25)
165 #define GRXSTS_FN_SHIFT 25
166 #define GRXSTS_PKTSTS_MASK (0xf << 17)
167 #define GRXSTS_PKTSTS_SHIFT 17
168 #define GRXSTS_PKTSTS_GLOBALOUTNAK (1 << 17)
169 #define GRXSTS_PKTSTS_OUTRX (2 << 17)
170 #define GRXSTS_PKTSTS_HCHIN (2 << 17)
171 #define GRXSTS_PKTSTS_OUTDONE (3 << 17)
172 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP (3 << 17)
173 #define GRXSTS_PKTSTS_SETUPDONE (4 << 17)
174 #define GRXSTS_PKTSTS_DATATOGGLEERR (5 << 17)
175 #define GRXSTS_PKTSTS_SETUPRX (6 << 17)
176 #define GRXSTS_PKTSTS_HCHHALTED (7 << 17)
177 #define GRXSTS_HCHNUM_MASK (0xf << 0)
178 #define GRXSTS_HCHNUM_SHIFT 0
179 #define GRXSTS_DPID_MASK (0x3 << 15)
180 #define GRXSTS_DPID_SHIFT 15
181 #define GRXSTS_BYTECNT_MASK (0x7ff << 4)
182 #define GRXSTS_BYTECNT_SHIFT 4
183 #define GRXSTS_EPNUM_MASK (0xf << 0)
184 #define GRXSTS_EPNUM_SHIFT 0
186 #define GRXFSIZ HSOTG_REG(0x024)
188 #define GNPTXFSIZ HSOTG_REG(0x028)
189 #define GNPTXFSIZ_NP_TXF_DEP_MASK (0xffff << 16)
190 #define GNPTXFSIZ_NP_TXF_DEP_SHIFT 16
191 #define GNPTXFSIZ_NP_TXF_DEP_LIMIT 0xffff
192 #define GNPTXFSIZ_NP_TXF_DEP(_x) ((_x) << 16)
193 #define GNPTXFSIZ_NP_TXF_ST_ADDR_MASK (0xffff << 0)
194 #define GNPTXFSIZ_NP_TXF_ST_ADDR_SHIFT 0
195 #define GNPTXFSIZ_NP_TXF_ST_ADDR_LIMIT 0xffff
196 #define GNPTXFSIZ_NP_TXF_ST_ADDR(_x) ((_x) << 0)
198 #define GNPTXSTS HSOTG_REG(0x02C)
199 #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
200 #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
201 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
202 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
203 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
204 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
205 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
206 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
208 #define GI2CCTL HSOTG_REG(0x0030)
209 #define GI2CCTL_BSYDNE (1 << 31)
210 #define GI2CCTL_RW (1 << 30)
211 #define GI2CCTL_I2CDATSE0 (1 << 28)
212 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
213 #define GI2CCTL_I2CDEVADDR_SHIFT 26
214 #define GI2CCTL_I2CSUSPCTL (1 << 25)
215 #define GI2CCTL_ACK (1 << 24)
216 #define GI2CCTL_I2CEN (1 << 23)
217 #define GI2CCTL_ADDR_MASK (0x7f << 16)
218 #define GI2CCTL_ADDR_SHIFT 16
219 #define GI2CCTL_REGADDR_MASK (0xff << 8)
220 #define GI2CCTL_REGADDR_SHIFT 8
221 #define GI2CCTL_RWDATA_MASK (0xff << 0)
222 #define GI2CCTL_RWDATA_SHIFT 0
224 #define GPVNDCTL HSOTG_REG(0x0034)
225 #define GGPIO HSOTG_REG(0x0038)
226 #define GUID HSOTG_REG(0x003c)
227 #define GSNPSID HSOTG_REG(0x0040)
228 #define GHWCFG1 HSOTG_REG(0x0044)
230 #define GHWCFG2 HSOTG_REG(0x0048)
231 #define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31)
232 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
233 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
234 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
235 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
236 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
237 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
238 #define GHWCFG2_MULTI_PROC_INT (1 << 20)
239 #define GHWCFG2_DYNAMIC_FIFO (1 << 19)
240 #define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18)
241 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
242 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
243 #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
244 #define GHWCFG2_NUM_DEV_EP_SHIFT 10
245 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
246 #define GHWCFG2_FS_PHY_TYPE_SHIFT 8
247 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED (0 << 8)
248 #define GHWCFG2_FS_PHY_TYPE_DEDICATED (1 << 8)
249 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI (2 << 8)
250 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI (3 << 8)
251 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
252 #define GHWCFG2_HS_PHY_TYPE_SHIFT 6
253 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED (0 << 6)
254 #define GHWCFG2_HS_PHY_TYPE_UTMI (1 << 6)
255 #define GHWCFG2_HS_PHY_TYPE_ULPI (2 << 6)
256 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI (3 << 6)
257 #define GHWCFG2_POINT2POINT (1 << 5)
258 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
259 #define GHWCFG2_ARCHITECTURE_SHIFT 3
260 #define GHWCFG2_SLAVE_ONLY_ARCH (0 << 3)
261 #define GHWCFG2_EXT_DMA_ARCH (1 << 3)
262 #define GHWCFG2_INT_DMA_ARCH (2 << 3)
263 #define GHWCFG2_OP_MODE_MASK (0x7 << 0)
264 #define GHWCFG2_OP_MODE_SHIFT 0
265 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE (0 << 0)
266 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE (1 << 0)
267 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE (2 << 0)
268 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE (3 << 0)
269 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE (4 << 0)
270 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST (5 << 0)
271 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST (6 << 0)
272 #define GHWCFG2_OP_MODE_UNDEFINED (7 << 0)
274 #define GHWCFG3 HSOTG_REG(0x004c)
275 #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
276 #define GHWCFG3_DFIFO_DEPTH_SHIFT 16
277 #define GHWCFG3_OTG_LPM_EN (1 << 15)
278 #define GHWCFG3_BC_SUPPORT (1 << 14)
279 #define GHWCFG3_OTG_ENABLE_HSIC (1 << 13)
280 #define GHWCFG3_ADP_SUPP (1 << 12)
281 #define GHWCFG3_SYNCH_RESET_TYPE (1 << 11)
282 #define GHWCFG3_OPTIONAL_FEATURES (1 << 10)
283 #define GHWCFG3_VENDOR_CTRL_IF (1 << 9)
284 #define GHWCFG3_I2C (1 << 8)
285 #define GHWCFG3_OTG_FUNC (1 << 7)
286 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
287 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
288 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
289 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
291 #define GHWCFG4 HSOTG_REG(0x0050)
292 #define GHWCFG4_DESC_DMA_DYN (1 << 31)
293 #define GHWCFG4_DESC_DMA (1 << 30)
294 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
295 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
296 #define GHWCFG4_DED_FIFO_EN (1 << 25)
297 #define GHWCFG4_SESSION_END_FILT_EN (1 << 24)
298 #define GHWCFG4_B_VALID_FILT_EN (1 << 23)
299 #define GHWCFG4_A_VALID_FILT_EN (1 << 22)
300 #define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21)
301 #define GHWCFG4_IDDIG_FILT_EN (1 << 20)
302 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
303 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
304 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
305 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
306 #define GHWCFG4_XHIBER (1 << 7)
307 #define GHWCFG4_HIBER (1 << 6)
308 #define GHWCFG4_MIN_AHB_FREQ (1 << 5)
309 #define GHWCFG4_POWER_OPTIMIZ (1 << 4)
310 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
311 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
313 #define GLPMCFG HSOTG_REG(0x0054)
314 #define GLPMCFG_INV_SEL_HSIC (1 << 31)
315 #define GLPMCFG_HSIC_CONNECT (1 << 30)
316 #define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25)
317 #define GLPMCFG_RETRY_COUNT_STS_SHIFT 25
318 #define GLPMCFG_SEND_LPM (1 << 24)
319 #define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21)
320 #define GLPMCFG_RETRY_COUNT_SHIFT 21
321 #define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17)
322 #define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17
323 #define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16)
324 #define GLPMCFG_PRT_SLEEP_STS (1 << 15)
325 #define GLPMCFG_LPM_RESP_MASK (0x3 << 13)
326 #define GLPMCFG_LPM_RESP_SHIFT 13
327 #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
328 #define GLPMCFG_HIRD_THRES_SHIFT 8
329 #define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
330 #define GLPMCFG_EN_UTMI_SLEEP (1 << 7)
331 #define GLPMCFG_REM_WKUP_EN (1 << 6)
332 #define GLPMCFG_HIRD_MASK (0xf << 2)
333 #define GLPMCFG_HIRD_SHIFT 2
334 #define GLPMCFG_APPL_RESP (1 << 1)
335 #define GLPMCFG_LPM_CAP_EN (1 << 0)
337 #define GPWRDN HSOTG_REG(0x0058)
338 #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
339 #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
340 #define GPWRDN_ADP_INT (1 << 23)
341 #define GPWRDN_BSESSVLD (1 << 22)
342 #define GPWRDN_IDSTS (1 << 21)
343 #define GPWRDN_LINESTATE_MASK (0x3 << 19)
344 #define GPWRDN_LINESTATE_SHIFT 19
345 #define GPWRDN_STS_CHGINT_MSK (1 << 18)
346 #define GPWRDN_STS_CHGINT (1 << 17)
347 #define GPWRDN_SRP_DET_MSK (1 << 16)
348 #define GPWRDN_SRP_DET (1 << 15)
349 #define GPWRDN_CONNECT_DET_MSK (1 << 14)
350 #define GPWRDN_CONNECT_DET (1 << 13)
351 #define GPWRDN_DISCONN_DET_MSK (1 << 12)
352 #define GPWRDN_DISCONN_DET (1 << 11)
353 #define GPWRDN_RST_DET_MSK (1 << 10)
354 #define GPWRDN_RST_DET (1 << 9)
355 #define GPWRDN_LNSTSCHG_MSK (1 << 8)
356 #define GPWRDN_LNSTSCHG (1 << 7)
357 #define GPWRDN_DIS_VBUS (1 << 6)
358 #define GPWRDN_PWRDNSWTCH (1 << 5)
359 #define GPWRDN_PWRDNRSTN (1 << 4)
360 #define GPWRDN_PWRDNCLMP (1 << 3)
361 #define GPWRDN_RESTORE (1 << 2)
362 #define GPWRDN_PMUACTV (1 << 1)
363 #define GPWRDN_PMUINTSEL (1 << 0)
365 #define GDFIFOCFG HSOTG_REG(0x005c)
366 #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
367 #define GDFIFOCFG_EPINFOBASE_SHIFT 16
368 #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
369 #define GDFIFOCFG_GDFIFOCFG_SHIFT 0
371 #define ADPCTL HSOTG_REG(0x0060)
372 #define ADPCTL_AR_MASK (0x3 << 27)
373 #define ADPCTL_AR_SHIFT 27
374 #define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26)
375 #define ADPCTL_ADP_SNS_INT_MSK (1 << 25)
376 #define ADPCTL_ADP_PRB_INT_MSK (1 << 24)
377 #define ADPCTL_ADP_TMOUT_INT (1 << 23)
378 #define ADPCTL_ADP_SNS_INT (1 << 22)
379 #define ADPCTL_ADP_PRB_INT (1 << 21)
380 #define ADPCTL_ADPENA (1 << 20)
381 #define ADPCTL_ADPRES (1 << 19)
382 #define ADPCTL_ENASNS (1 << 18)
383 #define ADPCTL_ENAPRB (1 << 17)
384 #define ADPCTL_RTIM_MASK (0x7ff << 6)
385 #define ADPCTL_RTIM_SHIFT 6
386 #define ADPCTL_PRB_PER_MASK (0x3 << 4)
387 #define ADPCTL_PRB_PER_SHIFT 4
388 #define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
389 #define ADPCTL_PRB_DELTA_SHIFT 2
390 #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
391 #define ADPCTL_PRB_DSCHRG_SHIFT 0
393 #define HPTXFSIZ HSOTG_REG(0x100)
395 #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
396 #define DPTXFSIZN_DP_TXF_SIZE_MASK (0xffff << 16)
397 #define DPTXFSIZN_DP_TXF_SIZE_SHIFT 16
398 #define DPTXFSIZN_DP_TXF_SIZE_GET(_v) (((_v) >> 16) & 0xffff)
399 #define DPTXFSIZN_DP_TXF_SIZE_LIMIT 0xffff
400 #define DPTXFSIZN_DP_TXF_SIZE(_x) ((_x) << 16)
401 #define DPTXFSIZN_DP_TXF_ST_ADDR_MASK (0xffff << 0)
402 #define DPTXFSIZN_DP_TXF_ST_ADDR_SHIFT 0
404 #define FIFOSIZE_DEPTH_MASK (0xffff << 16)
405 #define FIFOSIZE_DEPTH_SHIFT 16
406 #define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
407 #define FIFOSIZE_STARTADDR_SHIFT 0
409 /* Device mode registers */
411 #define DCFG HSOTG_REG(0x800)
412 #define DCFG_EPMISCNT_MASK (0x1f << 18)
413 #define DCFG_EPMISCNT_SHIFT 18
414 #define DCFG_EPMISCNT_LIMIT 0x1f
415 #define DCFG_EPMISCNT(_x) ((_x) << 18)
416 #define DCFG_PERFRINT_MASK (0x3 << 11)
417 #define DCFG_PERFRINT_SHIFT 11
418 #define DCFG_PERFRINT_LIMIT 0x3
419 #define DCFG_PERFRINT(_x) ((_x) << 11)
420 #define DCFG_DEVADDR_MASK (0x7f << 4)
421 #define DCFG_DEVADDR_SHIFT 4
422 #define DCFG_DEVADDR_LIMIT 0x7f
423 #define DCFG_DEVADDR(_x) ((_x) << 4)
424 #define DCFG_NZ_STS_OUT_HSHK (1 << 2)
425 #define DCFG_DEVSPD_MASK (0x3 << 0)
426 #define DCFG_DEVSPD_SHIFT 0
427 #define DCFG_DEVSPD_HS (0 << 0)
428 #define DCFG_DEVSPD_FS (1 << 0)
429 #define DCFG_DEVSPD_LS (2 << 0)
430 #define DCFG_DEVSPD_FS48 (3 << 0)
432 #define DCTL HSOTG_REG(0x804)
433 #define DCTL_PWRONPRGDONE (1 << 11)
434 #define DCTL_CGOUTNAK (1 << 10)
435 #define DCTL_SGOUTNAK (1 << 9)
436 #define DCTL_CGNPINNAK (1 << 8)
437 #define DCTL_SGNPINNAK (1 << 7)
438 #define DCTL_TSTCTL_MASK (0x7 << 4)
439 #define DCTL_TSTCTL_SHIFT 4
440 #define DCTL_GOUTNAKSTS (1 << 3)
441 #define DCTL_GNPINNAKSTS (1 << 2)
442 #define DCTL_SFTDISCON (1 << 1)
443 #define DCTL_RMTWKUPSIG (1 << 0)
445 #define DSTS HSOTG_REG(0x808)
446 #define DSTS_SOFFN_MASK (0x3fff << 8)
447 #define DSTS_SOFFN_SHIFT 8
448 #define DSTS_SOFFN_LIMIT 0x3fff
449 #define DSTS_SOFFN(_x) ((_x) << 8)
450 #define DSTS_ERRATICERR (1 << 3)
451 #define DSTS_ENUMSPD_MASK (0x3 << 1)
452 #define DSTS_ENUMSPD_SHIFT 1
453 #define DSTS_ENUMSPD_HS (0 << 1)
454 #define DSTS_ENUMSPD_FS (1 << 1)
455 #define DSTS_ENUMSPD_LS (2 << 1)
456 #define DSTS_ENUMSPD_FS48 (3 << 1)
457 #define DSTS_SUSPSTS (1 << 0)
459 #define DIEPMSK HSOTG_REG(0x810)
460 #define DIEPMSK_TXFIFOEMPTY (1 << 7)
461 #define DIEPMSK_INEPNAKEFFMSK (1 << 6)
462 #define DIEPMSK_INTKNEPMISMSK (1 << 5)
463 #define DIEPMSK_INTKNTXFEMPMSK (1 << 4)
464 #define DIEPMSK_TIMEOUTMSK (1 << 3)
465 #define DIEPMSK_AHBERRMSK (1 << 2)
466 #define DIEPMSK_EPDISBLDMSK (1 << 1)
467 #define DIEPMSK_XFERCOMPLMSK (1 << 0)
469 #define DOEPMSK HSOTG_REG(0x814)
470 #define DOEPMSK_BACK2BACKSETUP (1 << 6)
471 #define DOEPMSK_OUTTKNEPDISMSK (1 << 4)
472 #define DOEPMSK_SETUPMSK (1 << 3)
473 #define DOEPMSK_AHBERRMSK (1 << 2)
474 #define DOEPMSK_EPDISBLDMSK (1 << 1)
475 #define DOEPMSK_XFERCOMPLMSK (1 << 0)
477 #define DAINT HSOTG_REG(0x818)
478 #define DAINTMSK HSOTG_REG(0x81C)
479 #define DAINT_OUTEP_SHIFT 16
480 #define DAINT_OUTEP(_x) (1 << ((_x) + 16))
481 #define DAINT_INEP(_x) (1 << (_x))
483 #define DTKNQR1 HSOTG_REG(0x820)
484 #define DTKNQR2 HSOTG_REG(0x824)
485 #define DTKNQR3 HSOTG_REG(0x830)
486 #define DTKNQR4 HSOTG_REG(0x834)
488 #define DVBUSDIS HSOTG_REG(0x828)
489 #define DVBUSPULSE HSOTG_REG(0x82C)
491 #define DIEPCTL0 HSOTG_REG(0x900)
492 #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
494 #define DOEPCTL0 HSOTG_REG(0xB00)
495 #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
497 /* EP0 specialness:
498 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
499 * bits[25..22] - should always be zero, this isn't a periodic endpoint
500 * bits[10..0] - MPS setting different for EP0
501 */
502 #define D0EPCTL_MPS_MASK (0x3 << 0)
503 #define D0EPCTL_MPS_SHIFT 0
504 #define D0EPCTL_MPS_64 (0 << 0)
505 #define D0EPCTL_MPS_32 (1 << 0)
506 #define D0EPCTL_MPS_16 (2 << 0)
507 #define D0EPCTL_MPS_8 (3 << 0)
509 #define DXEPCTL_EPENA (1 << 31)
510 #define DXEPCTL_EPDIS (1 << 30)
511 #define DXEPCTL_SETD1PID (1 << 29)
512 #define DXEPCTL_SETODDFR (1 << 29)
513 #define DXEPCTL_SETD0PID (1 << 28)
514 #define DXEPCTL_SETEVENFR (1 << 28)
515 #define DXEPCTL_SNAK (1 << 27)
516 #define DXEPCTL_CNAK (1 << 26)
517 #define DXEPCTL_TXFNUM_MASK (0xf << 22)
518 #define DXEPCTL_TXFNUM_SHIFT 22
519 #define DXEPCTL_TXFNUM_LIMIT 0xf
520 #define DXEPCTL_TXFNUM(_x) ((_x) << 22)
521 #define DXEPCTL_STALL (1 << 21)
522 #define DXEPCTL_SNP (1 << 20)
523 #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
524 #define DXEPCTL_EPTYPE_SHIFT 18
525 #define DXEPCTL_EPTYPE_CONTROL (0 << 18)
526 #define DXEPCTL_EPTYPE_ISO (1 << 18)
527 #define DXEPCTL_EPTYPE_BULK (2 << 18)
528 #define DXEPCTL_EPTYPE_INTTERUPT (3 << 18)
529 #define DXEPCTL_NAKSTS (1 << 17)
530 #define DXEPCTL_DPID (1 << 16)
531 #define DXEPCTL_EOFRNUM (1 << 16)
532 #define DXEPCTL_USBACTEP (1 << 15)
533 #define DXEPCTL_NEXTEP_MASK (0xf << 11)
534 #define DXEPCTL_NEXTEP_SHIFT 11
535 #define DXEPCTL_NEXTEP_LIMIT 0xf
536 #define DXEPCTL_NEXTEP(_x) ((_x) << 11)
537 #define DXEPCTL_MPS_MASK (0x7ff << 0)
538 #define DXEPCTL_MPS_SHIFT 0
539 #define DXEPCTL_MPS_LIMIT 0x7ff
540 #define DXEPCTL_MPS(_x) ((_x) << 0)
542 #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
543 #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
544 #define DXEPINT_INEPNAKEFF (1 << 6)
545 #define DXEPINT_BACK2BACKSETUP (1 << 6)
546 #define DXEPINT_INTKNEPMIS (1 << 5)
547 #define DXEPINT_INTKNTXFEMP (1 << 4)
548 #define DXEPINT_OUTTKNEPDIS (1 << 4)
549 #define DXEPINT_TIMEOUT (1 << 3)
550 #define DXEPINT_SETUP (1 << 3)
551 #define DXEPINT_AHBERR (1 << 2)
552 #define DXEPINT_EPDISBLD (1 << 1)
553 #define DXEPINT_XFERCOMPL (1 << 0)
555 #define DIEPTSIZ0 HSOTG_REG(0x910)
556 #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
557 #define DIEPTSIZ0_PKTCNT_SHIFT 19
558 #define DIEPTSIZ0_PKTCNT_LIMIT 0x3
559 #define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
560 #define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
561 #define DIEPTSIZ0_XFERSIZE_SHIFT 0
562 #define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
563 #define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
565 #define DOEPTSIZ0 HSOTG_REG(0xB10)
566 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
567 #define DOEPTSIZ0_SUPCNT_SHIFT 29
568 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
569 #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
570 #define DOEPTSIZ0_PKTCNT (1 << 19)
571 #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
572 #define DOEPTSIZ0_XFERSIZE_SHIFT 0
574 #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
575 #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
576 #define DXEPTSIZ_MC_MASK (0x3 << 29)
577 #define DXEPTSIZ_MC_SHIFT 29
578 #define DXEPTSIZ_MC_LIMIT 0x3
579 #define DXEPTSIZ_MC(_x) ((_x) << 29)
580 #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
581 #define DXEPTSIZ_PKTCNT_SHIFT 19
582 #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
583 #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
584 #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
585 #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
586 #define DXEPTSIZ_XFERSIZE_SHIFT 0
587 #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
588 #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
589 #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
591 #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
592 #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
594 #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
596 #define PCGCTL HSOTG_REG(0x0e00)
597 #define PCGCTL_IF_DEV_MODE (1 << 31)
598 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
599 #define PCGCTL_P2HD_PRT_SPD_SHIFT 29
600 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
601 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
602 #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
603 #define PCGCTL_MAC_DEV_ADDR_SHIFT 20
604 #define PCGCTL_MAX_TERMSEL (1 << 19)
605 #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
606 #define PCGCTL_MAX_XCVRSELECT_SHIFT 17
607 #define PCGCTL_PORT_POWER (1 << 16)
608 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
609 #define PCGCTL_PRT_CLK_SEL_SHIFT 14
610 #define PCGCTL_ESS_REG_RESTORED (1 << 13)
611 #define PCGCTL_EXTND_HIBER_SWITCH (1 << 12)
612 #define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11)
613 #define PCGCTL_ENBL_EXTND_HIBER (1 << 10)
614 #define PCGCTL_RESTOREMODE (1 << 9)
615 #define PCGCTL_RESETAFTSUSP (1 << 8)
616 #define PCGCTL_DEEP_SLEEP (1 << 7)
617 #define PCGCTL_PHY_IN_SLEEP (1 << 6)
618 #define PCGCTL_ENBL_SLEEP_GATING (1 << 5)
619 #define PCGCTL_RSTPDWNMODULE (1 << 3)
620 #define PCGCTL_PWRCLMP (1 << 2)
621 #define PCGCTL_GATEHCLK (1 << 1)
622 #define PCGCTL_STOPPCLK (1 << 0)
624 #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
626 /* Host Mode Registers */
628 #define HCFG HSOTG_REG(0x0400)
629 #define HCFG_MODECHTIMEN (1 << 31)
630 #define HCFG_PERSCHEDENA (1 << 26)
631 #define HCFG_FRLISTEN_MASK (0x3 << 24)
632 #define HCFG_FRLISTEN_SHIFT 24
633 #define HCFG_FRLISTEN_8 (0 << 24)
634 #define FRLISTEN_8_SIZE 8
635 #define HCFG_FRLISTEN_16 (1 << 24)
636 #define FRLISTEN_16_SIZE 16
637 #define HCFG_FRLISTEN_32 (2 << 24)
638 #define FRLISTEN_32_SIZE 32
639 #define HCFG_FRLISTEN_64 (3 << 24)
640 #define FRLISTEN_64_SIZE 64
641 #define HCFG_DESCDMA (1 << 23)
642 #define HCFG_RESVALID_MASK (0xff << 8)
643 #define HCFG_RESVALID_SHIFT 8
644 #define HCFG_ENA32KHZ (1 << 7)
645 #define HCFG_FSLSSUPP (1 << 2)
646 #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
647 #define HCFG_FSLSPCLKSEL_SHIFT 0
648 #define HCFG_FSLSPCLKSEL_30_60_MHZ (0 << 0)
649 #define HCFG_FSLSPCLKSEL_48_MHZ (1 << 0)
650 #define HCFG_FSLSPCLKSEL_6_MHZ (2 << 0)
652 #define HFIR HSOTG_REG(0x0404)
653 #define HFIR_FRINT_MASK (0xffff << 0)
654 #define HFIR_FRINT_SHIFT 0
655 #define HFIR_RLDCTRL (1 << 16)
657 #define HFNUM HSOTG_REG(0x0408)
658 #define HFNUM_FRREM_MASK (0xffff << 16)
659 #define HFNUM_FRREM_SHIFT 16
660 #define HFNUM_FRNUM_MASK (0xffff << 0)
661 #define HFNUM_FRNUM_SHIFT 0
662 #define HFNUM_MAX_FRNUM 0x3fff
664 #define HPTXSTS HSOTG_REG(0x0410)
665 #define TXSTS_QTOP_ODD (1 << 31)
666 #define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
667 #define TXSTS_QTOP_CHNEP_SHIFT 27
668 #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
669 #define TXSTS_QTOP_TOKEN_SHIFT 25
670 #define TXSTS_QTOP_TERMINATE (1 << 24)
671 #define TXSTS_QSPCAVAIL_MASK (0xff << 16)
672 #define TXSTS_QSPCAVAIL_SHIFT 16
673 #define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
674 #define TXSTS_FSPCAVAIL_SHIFT 0
676 #define HAINT HSOTG_REG(0x0414)
677 #define HAINTMSK HSOTG_REG(0x0418)
678 #define HFLBADDR HSOTG_REG(0x041c)
680 #define HPRT0 HSOTG_REG(0x0440)
681 #define HPRT0_SPD_MASK (0x3 << 17)
682 #define HPRT0_SPD_SHIFT 17
683 #define HPRT0_SPD_HIGH_SPEED (0 << 17)
684 #define HPRT0_SPD_FULL_SPEED (1 << 17)
685 #define HPRT0_SPD_LOW_SPEED (2 << 17)
686 #define HPRT0_TSTCTL_MASK (0xf << 13)
687 #define HPRT0_TSTCTL_SHIFT 13
688 #define HPRT0_PWR (1 << 12)
689 #define HPRT0_LNSTS_MASK (0x3 << 10)
690 #define HPRT0_LNSTS_SHIFT 10
691 #define HPRT0_RST (1 << 8)
692 #define HPRT0_SUSP (1 << 7)
693 #define HPRT0_RES (1 << 6)
694 #define HPRT0_OVRCURRCHG (1 << 5)
695 #define HPRT0_OVRCURRACT (1 << 4)
696 #define HPRT0_ENACHG (1 << 3)
697 #define HPRT0_ENA (1 << 2)
698 #define HPRT0_CONNDET (1 << 1)
699 #define HPRT0_CONNSTS (1 << 0)
701 #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
702 #define HCCHAR_CHENA (1 << 31)
703 #define HCCHAR_CHDIS (1 << 30)
704 #define HCCHAR_ODDFRM (1 << 29)
705 #define HCCHAR_DEVADDR_MASK (0x7f << 22)
706 #define HCCHAR_DEVADDR_SHIFT 22
707 #define HCCHAR_MULTICNT_MASK (0x3 << 20)
708 #define HCCHAR_MULTICNT_SHIFT 20
709 #define HCCHAR_EPTYPE_MASK (0x3 << 18)
710 #define HCCHAR_EPTYPE_SHIFT 18
711 #define HCCHAR_LSPDDEV (1 << 17)
712 #define HCCHAR_EPDIR (1 << 15)
713 #define HCCHAR_EPNUM_MASK (0xf << 11)
714 #define HCCHAR_EPNUM_SHIFT 11
715 #define HCCHAR_MPS_MASK (0x7ff << 0)
716 #define HCCHAR_MPS_SHIFT 0
718 #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
719 #define HCSPLT_SPLTENA (1 << 31)
720 #define HCSPLT_COMPSPLT (1 << 16)
721 #define HCSPLT_XACTPOS_MASK (0x3 << 14)
722 #define HCSPLT_XACTPOS_SHIFT 14
723 #define HCSPLT_XACTPOS_MID (0 << 14)
724 #define HCSPLT_XACTPOS_END (1 << 14)
725 #define HCSPLT_XACTPOS_BEGIN (2 << 14)
726 #define HCSPLT_XACTPOS_ALL (3 << 14)
727 #define HCSPLT_HUBADDR_MASK (0x7f << 7)
728 #define HCSPLT_HUBADDR_SHIFT 7
729 #define HCSPLT_PRTADDR_MASK (0x7f << 0)
730 #define HCSPLT_PRTADDR_SHIFT 0
732 #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
733 #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
734 #define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
735 #define HCINTMSK_FRM_LIST_ROLL (1 << 13)
736 #define HCINTMSK_XCS_XACT (1 << 12)
737 #define HCINTMSK_BNA (1 << 11)
738 #define HCINTMSK_DATATGLERR (1 << 10)
739 #define HCINTMSK_FRMOVRUN (1 << 9)
740 #define HCINTMSK_BBLERR (1 << 8)
741 #define HCINTMSK_XACTERR (1 << 7)
742 #define HCINTMSK_NYET (1 << 6)
743 #define HCINTMSK_ACK (1 << 5)
744 #define HCINTMSK_NAK (1 << 4)
745 #define HCINTMSK_STALL (1 << 3)
746 #define HCINTMSK_AHBERR (1 << 2)
747 #define HCINTMSK_CHHLTD (1 << 1)
748 #define HCINTMSK_XFERCOMPL (1 << 0)
750 #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
751 #define TSIZ_DOPNG (1 << 31)
752 #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
753 #define TSIZ_SC_MC_PID_SHIFT 29
754 #define TSIZ_SC_MC_PID_DATA0 (0 << 29)
755 #define TSIZ_SC_MC_PID_DATA2 (1 << 29)
756 #define TSIZ_SC_MC_PID_DATA1 (2 << 29)
757 #define TSIZ_SC_MC_PID_MDATA (3 << 29)
758 #define TSIZ_SC_MC_PID_SETUP (3 << 29)
759 #define TSIZ_PKTCNT_MASK (0x3ff << 19)
760 #define TSIZ_PKTCNT_SHIFT 19
761 #define TSIZ_NTD_MASK (0xff << 8)
762 #define TSIZ_NTD_SHIFT 8
763 #define TSIZ_SCHINFO_MASK (0xff << 0)
764 #define TSIZ_SCHINFO_SHIFT 0
765 #define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
766 #define TSIZ_XFERSIZE_SHIFT 0
768 #define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
769 #define HCDMA_DMA_ADDR_MASK (0x1fffff << 11)
770 #define HCDMA_DMA_ADDR_SHIFT 11
771 #define HCDMA_CTD_MASK (0xff << 3)
772 #define HCDMA_CTD_SHIFT 3
774 #define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
776 #define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
778 /**
779 * struct dwc2_hcd_dma_desc - Host-mode DMA descriptor structure
780 *
781 * @status: DMA descriptor status quadlet
782 * @buf: DMA descriptor data buffer pointer
783 *
784 * DMA Descriptor structure contains two quadlets:
785 * Status quadlet and Data buffer pointer.
786 */
788 u32 status;
789 u32 buf;
790 };
792 #define HOST_DMA_A (1 << 31)
793 #define HOST_DMA_STS_MASK (0x3 << 28)
794 #define HOST_DMA_STS_SHIFT 28
795 #define HOST_DMA_STS_PKTERR (1 << 28)
796 #define HOST_DMA_EOL (1 << 26)
797 #define HOST_DMA_IOC (1 << 25)
798 #define HOST_DMA_SUP (1 << 24)
799 #define HOST_DMA_ALT_QTD (1 << 23)
800 #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
801 #define HOST_DMA_QTD_OFFSET_SHIFT 17
802 #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
803 #define HOST_DMA_ISOC_NBYTES_SHIFT 0
804 #define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
805 #define HOST_DMA_NBYTES_SHIFT 0
807 #define MAX_DMA_DESC_SIZE 131071
808 #define MAX_DMA_DESC_NUM_GENERIC 64
809 #define MAX_DMA_DESC_NUM_HS_ISOC 256