?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'for-3.11' of git://linux-nfs.org/~bfields/linux
[linux-2.6.git] / drivers / staging / comedi / drivers / ni_atmio16d.c
blobda7396f94297fe7620faec494f500a906c3df0cf
1 /*
2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15 */
16 /*
17 Driver: ni_atmio16d
18 Description: National Instruments AT-MIO-16D
19 Author: Chris R. Baugher <baugher@enteract.com>
20 Status: unknown
21 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
22 */
23 /*
24 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
25 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
26 * handling code from his driver as an example for this one.
27 *
28 * Chris Baugher
29 * 5/1/2000
30 *
31 */
32
33 #include <linux/interrupt.h>
34 #include "../comedidev.h"
35
36 #include <linux/ioport.h>
37
38 #include "comedi_fc.h"
39 #include "8255.h"
40
41 /* Configuration and Status Registers */
42 #define COM_REG_1 0x00 /* wo 16 */
43 #define STAT_REG 0x00 /* ro 16 */
44 #define COM_REG_2 0x02 /* wo 16 */
45 /* Event Strobe Registers */
46 #define START_CONVERT_REG 0x08 /* wo 16 */
47 #define START_DAQ_REG 0x0A /* wo 16 */
48 #define AD_CLEAR_REG 0x0C /* wo 16 */
49 #define EXT_STROBE_REG 0x0E /* wo 16 */
50 /* Analog Output Registers */
51 #define DAC0_REG 0x10 /* wo 16 */
52 #define DAC1_REG 0x12 /* wo 16 */
53 #define INT2CLR_REG 0x14 /* wo 16 */
54 /* Analog Input Registers */
55 #define MUX_CNTR_REG 0x04 /* wo 16 */
56 #define MUX_GAIN_REG 0x06 /* wo 16 */
57 #define AD_FIFO_REG 0x16 /* ro 16 */
58 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
59 /* AM9513A Counter/Timer Registers */
60 #define AM9513A_DATA_REG 0x18 /* rw 16 */
61 #define AM9513A_COM_REG 0x1A /* wo 16 */
62 #define AM9513A_STAT_REG 0x1A /* ro 16 */
63 /* MIO-16 Digital I/O Registers */
64 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
65 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
66 /* RTSI Switch Registers */
67 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
68 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
69 /* DIO-24 Registers */
70 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
71 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
72 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
73 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
74
75 /* Command Register bits */
76 #define COMREG1_2SCADC 0x0001
77 #define COMREG1_1632CNT 0x0002
78 #define COMREG1_SCANEN 0x0008
79 #define COMREG1_DAQEN 0x0010
80 #define COMREG1_DMAEN 0x0020
81 #define COMREG1_CONVINTEN 0x0080
82 #define COMREG2_SCN2 0x0010
83 #define COMREG2_INTEN 0x0080
84 #define COMREG2_DOUTEN0 0x0100
85 #define COMREG2_DOUTEN1 0x0200
86 /* Status Register bits */
87 #define STAT_AD_OVERRUN 0x0100
88 #define STAT_AD_OVERFLOW 0x0200
89 #define STAT_AD_DAQPROG 0x0800
90 #define STAT_AD_CONVAVAIL 0x2000
91 #define STAT_AD_DAQSTOPINT 0x4000
92 /* AM9513A Counter/Timer defines */
93 #define CLOCK_1_MHZ 0x8B25
94 #define CLOCK_100_KHZ 0x8C25
95 #define CLOCK_10_KHZ 0x8D25
96 #define CLOCK_1_KHZ 0x8E25
97 #define CLOCK_100_HZ 0x8F25
98 /* Other miscellaneous defines */
99 #define ATMIO16D_SIZE 32 /* bus address range */
100 #define ATMIO16D_TIMEOUT 10
101
102 struct atmio16_board_t {
103
104 const char *name;
105 int has_8255;
106 };
107
108 /* range structs */
109 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
110 BIP_RANGE
111 (10),
112 BIP_RANGE
113 (1),
114 BIP_RANGE
115 (0.1),
116 BIP_RANGE
117 (0.02)
118 }
119 };
120
121 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
122 BIP_RANGE
123 (5),
124 BIP_RANGE
125 (0.5),
126 BIP_RANGE
127 (0.05),
128 BIP_RANGE
129 (0.01)
130 }
131 };
132
133 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
134 UNI_RANGE
135 (10),
136 UNI_RANGE
137 (1),
138 UNI_RANGE
139 (0.1),
140 UNI_RANGE
141 (0.02)
142 }
143 };
144
145 /* private data struct */
146 struct atmio16d_private {
147 enum { adc_diff, adc_singleended } adc_mux;
148 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
149 enum { adc_2comp, adc_straight } adc_coding;
150 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
151 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
152 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
153 const struct comedi_lrange *ao_range_type_list[2];
154 unsigned int ao_readback[2];
155 unsigned int com_reg_1_state; /* current state of command register 1 */
156 unsigned int com_reg_2_state; /* current state of command register 2 */
157 };
158
159 static void reset_counters(struct comedi_device *dev)
160 {
161 /* Counter 2 */
162 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
163 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
164 outw(0x4, dev->iobase + AM9513A_DATA_REG);
165 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
166 outw(0x3, dev->iobase + AM9513A_DATA_REG);
167 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
168 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
169 /* Counter 3 */
170 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
171 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
172 outw(0x4, dev->iobase + AM9513A_DATA_REG);
173 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
174 outw(0x3, dev->iobase + AM9513A_DATA_REG);
175 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
176 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
177 /* Counter 4 */
178 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
179 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
180 outw(0x4, dev->iobase + AM9513A_DATA_REG);
181 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
182 outw(0x3, dev->iobase + AM9513A_DATA_REG);
183 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
184 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
185 /* Counter 5 */
186 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
187 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
188 outw(0x4, dev->iobase + AM9513A_DATA_REG);
189 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
190 outw(0x3, dev->iobase + AM9513A_DATA_REG);
191 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
192 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
193
194 outw(0, dev->iobase + AD_CLEAR_REG);
195 }
196
197 static void reset_atmio16d(struct comedi_device *dev)
198 {
199 struct atmio16d_private *devpriv = dev->private;
200 int i;
201
202 /* now we need to initialize the board */
203 outw(0, dev->iobase + COM_REG_1);
204 outw(0, dev->iobase + COM_REG_2);
205 outw(0, dev->iobase + MUX_GAIN_REG);
206 /* init AM9513A timer */
207 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
208 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
209 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
210 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
211 for (i = 1; i <= 5; ++i) {
212 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
213 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
214 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
215 outw(0x3, dev->iobase + AM9513A_DATA_REG);
216 }
217 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
218 /* timer init done */
219 outw(0, dev->iobase + AD_CLEAR_REG);
220 outw(0, dev->iobase + INT2CLR_REG);
221 /* select straight binary mode for Analog Input */
222 devpriv->com_reg_1_state |= 1;
223 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
224 devpriv->adc_coding = adc_straight;
225 /* zero the analog outputs */
226 outw(2048, dev->iobase + DAC0_REG);
227 outw(2048, dev->iobase + DAC1_REG);
228 }
229
230 static irqreturn_t atmio16d_interrupt(int irq, void *d)
231 {
232 struct comedi_device *dev = d;
233 struct comedi_subdevice *s = &dev->subdevices[0];
234
235 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
236
237 comedi_event(dev, s);
238 return IRQ_HANDLED;
239 }
240
241 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_cmd *cmd)
244 {
245 int err = 0;
246
247 /* Step 1 : check if triggers are trivially valid */
248
249 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
250 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
251 TRIG_FOLLOW | TRIG_TIMER);
252 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
253 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
254 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
255
256 if (err)
257 return 1;
258
259 /* Step 2a : make sure trigger sources are unique */
260
261 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
262 err |= cfc_check_trigger_is_unique(cmd->stop_src);
263
264 /* Step 2b : and mutually compatible */
265
266 if (err)
267 return 2;
268
269 /* Step 3: check if arguments are trivially valid */
270
271 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
272
273 if (cmd->scan_begin_src == TRIG_FOLLOW) {
274 /* internal trigger */
275 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
276 } else {
277 #if 0
278 /* external trigger */
279 /* should be level/edge, hi/lo specification here */
280 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
281 #endif
282 }
283
284 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 10000);
285 #if 0
286 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER);
287 #endif
288
289 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
290
291 if (cmd->stop_src == TRIG_COUNT) {
292 /* any count is allowed */
293 } else { /* TRIG_NONE */
294 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
295 }
296
297 if (err)
298 return 3;
299
300 return 0;
301 }
302
303 static int atmio16d_ai_cmd(struct comedi_device *dev,
304 struct comedi_subdevice *s)
305 {
306 struct atmio16d_private *devpriv = dev->private;
307 struct comedi_cmd *cmd = &s->async->cmd;
308 unsigned int timer, base_clock;
309 unsigned int sample_count, tmp, chan, gain;
310 int i;
311
312 /* This is slowly becoming a working command interface. *
313 * It is still uber-experimental */
314
315 reset_counters(dev);
316 s->async->cur_chan = 0;
317
318 /* check if scanning multiple channels */
319 if (cmd->chanlist_len < 2) {
320 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
321 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
322 } else {
323 devpriv->com_reg_1_state |= COMREG1_SCANEN;
324 devpriv->com_reg_2_state |= COMREG2_SCN2;
325 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
326 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
327 }
328
329 /* Setup the Mux-Gain Counter */
330 for (i = 0; i < cmd->chanlist_len; ++i) {
331 chan = CR_CHAN(cmd->chanlist[i]);
332 gain = CR_RANGE(cmd->chanlist[i]);
333 outw(i, dev->iobase + MUX_CNTR_REG);
334 tmp = chan | (gain << 6);
335 if (i == cmd->scan_end_arg - 1)
336 tmp |= 0x0010; /* set LASTONE bit */
337 outw(tmp, dev->iobase + MUX_GAIN_REG);
338 }
339
340 /* Now program the sample interval timer */
341 /* Figure out which clock to use then get an
342 * appropriate timer value */
343 if (cmd->convert_arg < 65536000) {
344 base_clock = CLOCK_1_MHZ;
345 timer = cmd->convert_arg / 1000;
346 } else if (cmd->convert_arg < 655360000) {
347 base_clock = CLOCK_100_KHZ;
348 timer = cmd->convert_arg / 10000;
349 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) {
350 base_clock = CLOCK_10_KHZ;
351 timer = cmd->convert_arg / 100000;
352 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) {
353 base_clock = CLOCK_1_KHZ;
354 timer = cmd->convert_arg / 1000000;
355 }
356 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
357 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
358 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
359 outw(0x2, dev->iobase + AM9513A_DATA_REG);
360 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
361 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
362 outw(timer, dev->iobase + AM9513A_DATA_REG);
363 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
364
365 /* Now figure out how many samples to get */
366 /* and program the sample counter */
367 sample_count = cmd->stop_arg * cmd->scan_end_arg;
368 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
369 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
370 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
371 if (sample_count < 65536) {
372 /* use only Counter 4 */
373 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
374 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
375 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
376 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
377 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
378 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
379 } else {
380 /* Counter 4 and 5 are needed */
381
382 tmp = sample_count & 0xFFFF;
383 if (tmp)
384 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
385 else
386 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
387
388 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
389 outw(0, dev->iobase + AM9513A_DATA_REG);
390 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
391 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
392 outw(0x25, dev->iobase + AM9513A_DATA_REG);
393 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
394 tmp = sample_count & 0xFFFF;
395 if ((tmp == 0) || (tmp == 1)) {
396 outw((sample_count >> 16) & 0xFFFF,
397 dev->iobase + AM9513A_DATA_REG);
398 } else {
399 outw(((sample_count >> 16) & 0xFFFF) + 1,
400 dev->iobase + AM9513A_DATA_REG);
401 }
402 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
403 devpriv->com_reg_1_state |= COMREG1_1632CNT;
404 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
405 }
406
407 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
408 /* Figure out which clock to use then get an
409 * appropriate timer value */
410 if (cmd->chanlist_len > 1) {
411 if (cmd->scan_begin_arg < 65536000) {
412 base_clock = CLOCK_1_MHZ;
413 timer = cmd->scan_begin_arg / 1000;
414 } else if (cmd->scan_begin_arg < 655360000) {
415 base_clock = CLOCK_100_KHZ;
416 timer = cmd->scan_begin_arg / 10000;
417 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) {
418 base_clock = CLOCK_10_KHZ;
419 timer = cmd->scan_begin_arg / 100000;
420 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) {
421 base_clock = CLOCK_1_KHZ;
422 timer = cmd->scan_begin_arg / 1000000;
423 }
424 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
425 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
426 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
427 outw(0x2, dev->iobase + AM9513A_DATA_REG);
428 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
429 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
430 outw(timer, dev->iobase + AM9513A_DATA_REG);
431 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
432 }
433
434 /* Clear the A/D FIFO and reset the MUX counter */
435 outw(0, dev->iobase + AD_CLEAR_REG);
436 outw(0, dev->iobase + MUX_CNTR_REG);
437 outw(0, dev->iobase + INT2CLR_REG);
438 /* enable this acquisition operation */
439 devpriv->com_reg_1_state |= COMREG1_DAQEN;
440 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
441 /* enable interrupts for conversion completion */
442 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
443 devpriv->com_reg_2_state |= COMREG2_INTEN;
444 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
445 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
446 /* apply a trigger. this starts the counters! */
447 outw(0, dev->iobase + START_DAQ_REG);
448
449 return 0;
450 }
451
452 /* This will cancel a running acquisition operation */
453 static int atmio16d_ai_cancel(struct comedi_device *dev,
454 struct comedi_subdevice *s)
455 {
456 reset_atmio16d(dev);
457
458 return 0;
459 }
460
461 /* Mode 0 is used to get a single conversion on demand */
462 static int atmio16d_ai_insn_read(struct comedi_device *dev,
463 struct comedi_subdevice *s,
464 struct comedi_insn *insn, unsigned int *data)
465 {
466 struct atmio16d_private *devpriv = dev->private;
467 int i, t;
468 int chan;
469 int gain;
470 int status;
471
472 chan = CR_CHAN(insn->chanspec);
473 gain = CR_RANGE(insn->chanspec);
474
475 /* reset the Analog input circuitry */
476 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
477 /* reset the Analog Input MUX Counter to 0 */
478 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
479
480 /* set the Input MUX gain */
481 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
482
483 for (i = 0; i < insn->n; i++) {
484 /* start the conversion */
485 outw(0, dev->iobase + START_CONVERT_REG);
486 /* wait for it to finish */
487 for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
488 /* check conversion status */
489 status = inw(dev->iobase + STAT_REG);
490 if (status & STAT_AD_CONVAVAIL) {
491 /* read the data now */
492 data[i] = inw(dev->iobase + AD_FIFO_REG);
493 /* change to two's complement if need be */
494 if (devpriv->adc_coding == adc_2comp)
495 data[i] ^= 0x800;
496 break;
497 }
498 if (status & STAT_AD_OVERFLOW) {
499 printk(KERN_INFO "atmio16d: a/d FIFO overflow\n");
500 outw(0, dev->iobase + AD_CLEAR_REG);
501
502 return -ETIME;
503 }
504 }
505 /* end waiting, now check if it timed out */
506 if (t == ATMIO16D_TIMEOUT) {
507 printk(KERN_INFO "atmio16d: timeout\n");
508
509 return -ETIME;
510 }
511 }
512
513 return i;
514 }
515
516 static int atmio16d_ao_insn_read(struct comedi_device *dev,
517 struct comedi_subdevice *s,
518 struct comedi_insn *insn, unsigned int *data)
519 {
520 struct atmio16d_private *devpriv = dev->private;
521 int i;
522
523 for (i = 0; i < insn->n; i++)
524 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
525 return i;
526 }
527
528 static int atmio16d_ao_insn_write(struct comedi_device *dev,
529 struct comedi_subdevice *s,
530 struct comedi_insn *insn, unsigned int *data)
531 {
532 struct atmio16d_private *devpriv = dev->private;
533 int i;
534 int chan;
535 int d;
536
537 chan = CR_CHAN(insn->chanspec);
538
539 for (i = 0; i < insn->n; i++) {
540 d = data[i];
541 switch (chan) {
542 case 0:
543 if (devpriv->dac0_coding == dac_2comp)
544 d ^= 0x800;
545 outw(d, dev->iobase + DAC0_REG);
546 break;
547 case 1:
548 if (devpriv->dac1_coding == dac_2comp)
549 d ^= 0x800;
550 outw(d, dev->iobase + DAC1_REG);
551 break;
552 default:
553 return -EINVAL;
554 }
555 devpriv->ao_readback[chan] = data[i];
556 }
557 return i;
558 }
559
560 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
561 struct comedi_subdevice *s,
562 struct comedi_insn *insn, unsigned int *data)
563 {
564 if (data[0]) {
565 s->state &= ~data[0];
566 s->state |= (data[0] | data[1]);
567 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
568 }
569 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
570
571 return insn->n;
572 }
573
574 static int atmio16d_dio_insn_config(struct comedi_device *dev,
575 struct comedi_subdevice *s,
576 struct comedi_insn *insn,
577 unsigned int *data)
578 {
579 struct atmio16d_private *devpriv = dev->private;
580 int i;
581 int mask;
582
583 for (i = 0; i < insn->n; i++) {
584 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0;
585 s->io_bits &= ~mask;
586 if (data[i])
587 s->io_bits |= mask;
588 }
589 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
590 if (s->io_bits & 0x0f)
591 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
592 if (s->io_bits & 0xf0)
593 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
594 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
595
596 return i;
597 }
598
599 /*
600 options[0] - I/O port
601 options[1] - MIO irq
602 0 == no irq
603 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
604 options[2] - DIO irq
605 0 == no irq
606 N == irq N {3,4,5,6,7,9}
607 options[3] - DMA1 channel
608 0 == no DMA
609 N == DMA N {5,6,7}
610 options[4] - DMA2 channel
611 0 == no DMA
612 N == DMA N {5,6,7}
613
614 options[5] - a/d mux
615 0=differential, 1=single
616 options[6] - a/d range
617 0=bipolar10, 1=bipolar5, 2=unipolar10
618
619 options[7] - dac0 range
620 0=bipolar, 1=unipolar
621 options[8] - dac0 reference
622 0=internal, 1=external
623 options[9] - dac0 coding
624 0=2's comp, 1=straight binary
625
626 options[10] - dac1 range
627 options[11] - dac1 reference
628 options[12] - dac1 coding
629 */
630
631 static int atmio16d_attach(struct comedi_device *dev,
632 struct comedi_devconfig *it)
633 {
634 const struct atmio16_board_t *board = comedi_board(dev);
635 struct atmio16d_private *devpriv;
636 struct comedi_subdevice *s;
637 unsigned int irq;
638 int ret;
639
640 ret = comedi_request_region(dev, it->options[0], ATMIO16D_SIZE);
641 if (ret)
642 return ret;
643
644 ret = comedi_alloc_subdevices(dev, 4);
645 if (ret)
646 return ret;
647
648 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
649 if (!devpriv)
650 return -ENOMEM;
651 dev->private = devpriv;
652
653 /* reset the atmio16d hardware */
654 reset_atmio16d(dev);
655
656 /* check if our interrupt is available and get it */
657 irq = it->options[1];
658 if (irq) {
659
660 ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev);
661 if (ret < 0) {
662 printk(KERN_INFO "failed to allocate irq %u\n", irq);
663 return ret;
664 }
665 dev->irq = irq;
666 printk(KERN_INFO "( irq = %u )\n", irq);
667 } else {
668 printk(KERN_INFO "( no irq )");
669 }
670
671 /* set device options */
672 devpriv->adc_mux = it->options[5];
673 devpriv->adc_range = it->options[6];
674
675 devpriv->dac0_range = it->options[7];
676 devpriv->dac0_reference = it->options[8];
677 devpriv->dac0_coding = it->options[9];
678 devpriv->dac1_range = it->options[10];
679 devpriv->dac1_reference = it->options[11];
680 devpriv->dac1_coding = it->options[12];
681
682 /* setup sub-devices */
683 s = &dev->subdevices[0];
684 dev->read_subdev = s;
685 /* ai subdevice */
686 s->type = COMEDI_SUBD_AI;
687 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
688 s->n_chan = (devpriv->adc_mux ? 16 : 8);
689 s->len_chanlist = 16;
690 s->insn_read = atmio16d_ai_insn_read;
691 s->do_cmdtest = atmio16d_ai_cmdtest;
692 s->do_cmd = atmio16d_ai_cmd;
693 s->cancel = atmio16d_ai_cancel;
694 s->maxdata = 0xfff; /* 4095 decimal */
695 switch (devpriv->adc_range) {
696 case adc_bipolar10:
697 s->range_table = &range_atmio16d_ai_10_bipolar;
698 break;
699 case adc_bipolar5:
700 s->range_table = &range_atmio16d_ai_5_bipolar;
701 break;
702 case adc_unipolar10:
703 s->range_table = &range_atmio16d_ai_unipolar;
704 break;
705 }
706
707 /* ao subdevice */
708 s = &dev->subdevices[1];
709 s->type = COMEDI_SUBD_AO;
710 s->subdev_flags = SDF_WRITABLE;
711 s->n_chan = 2;
712 s->insn_read = atmio16d_ao_insn_read;
713 s->insn_write = atmio16d_ao_insn_write;
714 s->maxdata = 0xfff; /* 4095 decimal */
715 s->range_table_list = devpriv->ao_range_type_list;
716 switch (devpriv->dac0_range) {
717 case dac_bipolar:
718 devpriv->ao_range_type_list[0] = &range_bipolar10;
719 break;
720 case dac_unipolar:
721 devpriv->ao_range_type_list[0] = &range_unipolar10;
722 break;
723 }
724 switch (devpriv->dac1_range) {
725 case dac_bipolar:
726 devpriv->ao_range_type_list[1] = &range_bipolar10;
727 break;
728 case dac_unipolar:
729 devpriv->ao_range_type_list[1] = &range_unipolar10;
730 break;
731 }
732
733 /* Digital I/O */
734 s = &dev->subdevices[2];
735 s->type = COMEDI_SUBD_DIO;
736 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
737 s->n_chan = 8;
738 s->insn_bits = atmio16d_dio_insn_bits;
739 s->insn_config = atmio16d_dio_insn_config;
740 s->maxdata = 1;
741 s->range_table = &range_digital;
742
743 /* 8255 subdevice */
744 s = &dev->subdevices[3];
745 if (board->has_8255)
746 subdev_8255_init(dev, s, NULL, dev->iobase);
747 else
748 s->type = COMEDI_SUBD_UNUSED;
749
750 /* don't yet know how to deal with counter/timers */
751 #if 0
752 s = &dev->subdevices[4];
753 /* do */
754 s->type = COMEDI_SUBD_TIMER;
755 s->n_chan = 0;
756 s->maxdata = 0
757 #endif
758 printk("\n");
759
760 return 0;
761 }
762
763 static void atmio16d_detach(struct comedi_device *dev)
764 {
765 reset_atmio16d(dev);
766 comedi_legacy_detach(dev);
767 }
768
769 static const struct atmio16_board_t atmio16_boards[] = {
770 {
771 .name = "atmio16",
772 .has_8255 = 0,
773 }, {
774 .name = "atmio16d",
775 .has_8255 = 1,
776 },
777 };
778
779 static struct comedi_driver atmio16d_driver = {
780 .driver_name = "atmio16",
781 .module = THIS_MODULE,
782 .attach = atmio16d_attach,
783 .detach = atmio16d_detach,
784 .board_name = &atmio16_boards[0].name,
785 .num_names = ARRAY_SIZE(atmio16_boards),
786 .offset = sizeof(struct atmio16_board_t),
787 };
788 module_comedi_driver(atmio16d_driver);
789
790 MODULE_AUTHOR("Comedi http://www.comedi.org");
791 MODULE_DESCRIPTION("Comedi low-level driver");
792 MODULE_LICENSE("GPL");
Linus' kernel tree