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Merge branch 'for-3.11' of git://linux-nfs.org/~bfields/linux
[linux-2.6.git] / drivers / staging / comedi / drivers / mite.c
blob12c34db61d637c0048fdb543cf9265e384b6f496
1 /*
2 comedi/drivers/mite.c
3 Hardware driver for NI Mite PCI interface chip
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17 */
18
19 /*
20 The PCI-MIO E series driver was originally written by
21 Tomasz Motylewski <...>, and ported to comedi by ds.
22
23 References for specifications:
24
25 321747b.pdf Register Level Programmer Manual (obsolete)
26 321747c.pdf Register Level Programmer Manual (new)
27 DAQ-STC reference manual
28
29 Other possibly relevant info:
30
31 320517c.pdf User manual (obsolete)
32 320517f.pdf User manual (new)
33 320889a.pdf delete
34 320906c.pdf maximum signal ratings
35 321066a.pdf about 16x
36 321791a.pdf discontinuation of at-mio-16e-10 rev. c
37 321808a.pdf about at-mio-16e-10 rev P
38 321837a.pdf discontinuation of at-mio-16de-10 rev d
39 321838a.pdf about at-mio-16de-10 rev N
40
41 ISSUES:
42
43 */
44
45 /* #define USE_KMALLOC */
46
47 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
48
49 #include <linux/pci.h>
50
51 #include "../comedidev.h"
52
53 #include "comedi_fc.h"
54 #include "mite.h"
55
56 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
57
58 struct mite_struct *mite_alloc(struct pci_dev *pcidev)
59 {
60 struct mite_struct *mite;
61 unsigned int i;
62
63 mite = kzalloc(sizeof(*mite), GFP_KERNEL);
64 if (mite) {
65 spin_lock_init(&mite->lock);
66 mite->pcidev = pcidev;
67 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
68 mite->channels[i].mite = mite;
69 mite->channels[i].channel = i;
70 mite->channels[i].done = 1;
71 }
72 }
73 return mite;
74 }
75 EXPORT_SYMBOL_GPL(mite_alloc);
76
77 static void dump_chip_signature(u32 csigr_bits)
78 {
79 pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
80 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
81 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
82 pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
83 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
84 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
85 }
86
87 static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
88 {
89 unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
90 unsigned empty_count = (fcr_bits >> 16) & 0xff;
91 unsigned full_count = fcr_bits & 0xff;
92 return empty_count + full_count;
93 }
94
95 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
96 {
97 unsigned long length;
98 int i;
99 u32 csigr_bits;
100 unsigned unknown_dma_burst_bits;
101
102 pci_set_master(mite->pcidev);
103
104 mite->mite_io_addr = pci_ioremap_bar(mite->pcidev, 0);
105 if (!mite->mite_io_addr) {
106 dev_err(&mite->pcidev->dev,
107 "Failed to remap mite io memory address\n");
108 return -ENOMEM;
109 }
110 mite->mite_phys_addr = pci_resource_start(mite->pcidev, 0);
111
112 mite->daq_io_addr = pci_ioremap_bar(mite->pcidev, 1);
113 if (!mite->daq_io_addr) {
114 dev_err(&mite->pcidev->dev,
115 "Failed to remap daq io memory address\n");
116 return -ENOMEM;
117 }
118 mite->daq_phys_addr = pci_resource_start(mite->pcidev, 1);
119 length = pci_resource_len(mite->pcidev, 1);
120
121 if (use_iodwbsr_1) {
122 writel(0, mite->mite_io_addr + MITE_IODWBSR);
123 dev_info(&mite->pcidev->dev,
124 "using I/O Window Base Size register 1\n");
125 writel(mite->daq_phys_addr | WENAB |
126 MITE_IODWBSR_1_WSIZE_bits(length),
127 mite->mite_io_addr + MITE_IODWBSR_1);
128 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
129 } else {
130 writel(mite->daq_phys_addr | WENAB,
131 mite->mite_io_addr + MITE_IODWBSR);
132 }
133 /*
134 * make sure dma bursts work. I got this from running a bus analyzer
135 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
136 * of 0x61f and bursts worked. 6281 powered up with register value of
137 * 0x1f and bursts didn't work. The NI windows driver reads the
138 * register, then does a bitwise-or of 0x600 with it and writes it back.
139 */
140 unknown_dma_burst_bits =
141 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
142 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
143 writel(unknown_dma_burst_bits,
144 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
145
146 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
147 mite->num_channels = mite_csigr_dmac(csigr_bits);
148 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
149 dev_warn(&mite->pcidev->dev,
150 "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
151 mite->num_channels, MAX_MITE_DMA_CHANNELS);
152 mite->num_channels = MAX_MITE_DMA_CHANNELS;
153 }
154 dump_chip_signature(csigr_bits);
155 for (i = 0; i < mite->num_channels; i++) {
156 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
157 /* disable interrupts */
158 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
159 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
160 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
161 mite->mite_io_addr + MITE_CHCR(i));
162 }
163 mite->fifo_size = mite_fifo_size(mite, 0);
164 dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
165 return 0;
166 }
167 EXPORT_SYMBOL_GPL(mite_setup2);
168
169 int mite_setup(struct mite_struct *mite)
170 {
171 return mite_setup2(mite, 0);
172 }
173 EXPORT_SYMBOL_GPL(mite_setup);
174
175 void mite_unsetup(struct mite_struct *mite)
176 {
177 /* unsigned long offset, start, length; */
178
179 if (!mite)
180 return;
181
182 if (mite->mite_io_addr) {
183 iounmap(mite->mite_io_addr);
184 mite->mite_io_addr = NULL;
185 }
186 if (mite->daq_io_addr) {
187 iounmap(mite->daq_io_addr);
188 mite->daq_io_addr = NULL;
189 }
190 if (mite->mite_phys_addr)
191 mite->mite_phys_addr = 0;
192 }
193 EXPORT_SYMBOL_GPL(mite_unsetup);
194
195 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
196 {
197 struct mite_dma_descriptor_ring *ring =
198 kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
199
200 if (ring == NULL)
201 return ring;
202 ring->hw_dev = get_device(&mite->pcidev->dev);
203 if (ring->hw_dev == NULL) {
204 kfree(ring);
205 return NULL;
206 }
207 ring->n_links = 0;
208 ring->descriptors = NULL;
209 ring->descriptors_dma_addr = 0;
210 return ring;
211 };
212 EXPORT_SYMBOL_GPL(mite_alloc_ring);
213
214 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
215 {
216 if (ring) {
217 if (ring->descriptors) {
218 dma_free_coherent(ring->hw_dev,
219 ring->n_links *
220 sizeof(struct mite_dma_descriptor),
221 ring->descriptors,
222 ring->descriptors_dma_addr);
223 }
224 put_device(ring->hw_dev);
225 kfree(ring);
226 }
227 };
228 EXPORT_SYMBOL_GPL(mite_free_ring);
229
230 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
231 struct
232 mite_dma_descriptor_ring
233 *ring, unsigned min_channel,
234 unsigned max_channel)
235 {
236 int i;
237 unsigned long flags;
238 struct mite_channel *channel = NULL;
239
240 /* spin lock so mite_release_channel can be called safely
241 * from interrupts
242 */
243 spin_lock_irqsave(&mite->lock, flags);
244 for (i = min_channel; i <= max_channel; ++i) {
245 if (mite->channel_allocated[i] == 0) {
246 mite->channel_allocated[i] = 1;
247 channel = &mite->channels[i];
248 channel->ring = ring;
249 break;
250 }
251 }
252 spin_unlock_irqrestore(&mite->lock, flags);
253 return channel;
254 }
255 EXPORT_SYMBOL_GPL(mite_request_channel_in_range);
256
257 void mite_release_channel(struct mite_channel *mite_chan)
258 {
259 struct mite_struct *mite = mite_chan->mite;
260 unsigned long flags;
261
262 /* spin lock to prevent races with mite_request_channel */
263 spin_lock_irqsave(&mite->lock, flags);
264 if (mite->channel_allocated[mite_chan->channel]) {
265 mite_dma_disarm(mite_chan);
266 mite_dma_reset(mite_chan);
267 /*
268 * disable all channel's interrupts (do it after disarm/reset so
269 * MITE_CHCR reg isn't changed while dma is still active!)
270 */
271 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
272 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
273 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
274 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
275 mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
276 mite->channel_allocated[mite_chan->channel] = 0;
277 mite_chan->ring = NULL;
278 mmiowb();
279 }
280 spin_unlock_irqrestore(&mite->lock, flags);
281 }
282 EXPORT_SYMBOL_GPL(mite_release_channel);
283
284 void mite_dma_arm(struct mite_channel *mite_chan)
285 {
286 struct mite_struct *mite = mite_chan->mite;
287 int chor;
288 unsigned long flags;
289
290 MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
291 /*
292 * memory barrier is intended to insure any twiddling with the buffer
293 * is done before writing to the mite to arm dma transfer
294 */
295 smp_mb();
296 /* arm */
297 chor = CHOR_START;
298 spin_lock_irqsave(&mite->lock, flags);
299 mite_chan->done = 0;
300 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
301 mmiowb();
302 spin_unlock_irqrestore(&mite->lock, flags);
303 /* mite_dma_tcr(mite, channel); */
304 }
305 EXPORT_SYMBOL_GPL(mite_dma_arm);
306
307 /**************************************/
308
309 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
310 struct comedi_async *async)
311 {
312 unsigned int n_links;
313 int i;
314
315 if (ring->descriptors) {
316 dma_free_coherent(ring->hw_dev,
317 ring->n_links *
318 sizeof(struct mite_dma_descriptor),
319 ring->descriptors,
320 ring->descriptors_dma_addr);
321 }
322 ring->descriptors = NULL;
323 ring->descriptors_dma_addr = 0;
324 ring->n_links = 0;
325
326 if (async->prealloc_bufsz == 0)
327 return 0;
328
329 n_links = async->prealloc_bufsz >> PAGE_SHIFT;
330
331 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
332
333 ring->descriptors =
334 dma_alloc_coherent(ring->hw_dev,
335 n_links * sizeof(struct mite_dma_descriptor),
336 &ring->descriptors_dma_addr, GFP_KERNEL);
337 if (!ring->descriptors) {
338 dev_err(async->subdevice->device->class_dev,
339 "mite: ring buffer allocation failed\n");
340 return -ENOMEM;
341 }
342 ring->n_links = n_links;
343
344 for (i = 0; i < n_links; i++) {
345 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
346 ring->descriptors[i].addr =
347 cpu_to_le32(async->buf_page_list[i].dma_addr);
348 ring->descriptors[i].next =
349 cpu_to_le32(ring->descriptors_dma_addr + (i +
350 1) *
351 sizeof(struct mite_dma_descriptor));
352 }
353 ring->descriptors[n_links - 1].next =
354 cpu_to_le32(ring->descriptors_dma_addr);
355 /*
356 * barrier is meant to insure that all the writes to the dma descriptors
357 * have completed before the dma controller is commanded to read them
358 */
359 smp_wmb();
360 return 0;
361 }
362 EXPORT_SYMBOL_GPL(mite_buf_change);
363
364 void mite_prep_dma(struct mite_channel *mite_chan,
365 unsigned int num_device_bits, unsigned int num_memory_bits)
366 {
367 unsigned int chor, chcr, mcr, dcr, lkcr;
368 struct mite_struct *mite = mite_chan->mite;
369
370 MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
371
372 /* reset DMA and FIFO */
373 chor = CHOR_DMARESET | CHOR_FRESET;
374 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
375
376 /* short link chaining mode */
377 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
378 CHCR_BURSTEN;
379 /*
380 * Link Complete Interrupt: interrupt every time a link
381 * in MITE_RING is completed. This can generate a lot of
382 * extra interrupts, but right now we update the values
383 * of buf_int_ptr and buf_int_count at each interrupt. A
384 * better method is to poll the MITE before each user
385 * "read()" to calculate the number of bytes available.
386 */
387 chcr |= CHCR_SET_LC_IE;
388 if (num_memory_bits == 32 && num_device_bits == 16) {
389 /*
390 * Doing a combined 32 and 16 bit byteswap gets the 16 bit
391 * samples into the fifo in the right order. Tested doing 32 bit
392 * memory to 16 bit device transfers to the analog out of a
393 * pxi-6281, which has mite version = 1, type = 4. This also
394 * works for dma reads from the counters on e-series boards.
395 */
396 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
397 }
398 if (mite_chan->dir == COMEDI_INPUT)
399 chcr |= CHCR_DEV_TO_MEM;
400
401 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
402
403 /* to/from memory */
404 mcr = CR_RL(64) | CR_ASEQUP;
405 switch (num_memory_bits) {
406 case 8:
407 mcr |= CR_PSIZE8;
408 break;
409 case 16:
410 mcr |= CR_PSIZE16;
411 break;
412 case 32:
413 mcr |= CR_PSIZE32;
414 break;
415 default:
416 pr_warn("bug! invalid mem bit width for dma transfer\n");
417 break;
418 }
419 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
420
421 /* from/to device */
422 dcr = CR_RL(64) | CR_ASEQUP;
423 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
424 switch (num_device_bits) {
425 case 8:
426 dcr |= CR_PSIZE8;
427 break;
428 case 16:
429 dcr |= CR_PSIZE16;
430 break;
431 case 32:
432 dcr |= CR_PSIZE32;
433 break;
434 default:
435 pr_warn("bug! invalid dev bit width for dma transfer\n");
436 break;
437 }
438 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
439
440 /* reset the DAR */
441 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
442
443 /* the link is 32bits */
444 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
445 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
446
447 /* starting address for link chaining */
448 writel(mite_chan->ring->descriptors_dma_addr,
449 mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
450
451 MDPRINTK("exit mite_prep_dma\n");
452 }
453 EXPORT_SYMBOL_GPL(mite_prep_dma);
454
455 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
456 {
457 struct mite_struct *mite = mite_chan->mite;
458 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
459 }
460
461 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
462 {
463 struct mite_struct *mite = mite_chan->mite;
464 return readl(mite->mite_io_addr +
465 MITE_FCR(mite_chan->channel)) & 0x000000FF;
466 }
467 EXPORT_SYMBOL_GPL(mite_bytes_in_transit);
468
469 /* returns lower bound for number of bytes transferred from device to memory */
470 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
471 {
472 u32 device_byte_count;
473
474 device_byte_count = mite_device_bytes_transferred(mite_chan);
475 return device_byte_count - mite_bytes_in_transit(mite_chan);
476 }
477 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_lb);
478
479 /* returns upper bound for number of bytes transferred from device to memory */
480 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
481 {
482 u32 in_transit_count;
483
484 in_transit_count = mite_bytes_in_transit(mite_chan);
485 return mite_device_bytes_transferred(mite_chan) - in_transit_count;
486 }
487 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_ub);
488
489 /* returns lower bound for number of bytes read from memory to device */
490 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
491 {
492 u32 device_byte_count;
493
494 device_byte_count = mite_device_bytes_transferred(mite_chan);
495 return device_byte_count + mite_bytes_in_transit(mite_chan);
496 }
497 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_lb);
498
499 /* returns upper bound for number of bytes read from memory to device */
500 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
501 {
502 u32 in_transit_count;
503
504 in_transit_count = mite_bytes_in_transit(mite_chan);
505 return mite_device_bytes_transferred(mite_chan) + in_transit_count;
506 }
507 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_ub);
508
509 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
510 {
511 struct mite_struct *mite = mite_chan->mite;
512 int tcr;
513 int lkar;
514
515 lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
516 tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
517 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
518 lkar, tcr);
519
520 return tcr;
521 }
522 EXPORT_SYMBOL_GPL(mite_dma_tcr);
523
524 void mite_dma_disarm(struct mite_channel *mite_chan)
525 {
526 struct mite_struct *mite = mite_chan->mite;
527 unsigned chor;
528
529 /* disarm */
530 chor = CHOR_ABORT;
531 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
532 }
533 EXPORT_SYMBOL_GPL(mite_dma_disarm);
534
535 int mite_sync_input_dma(struct mite_channel *mite_chan,
536 struct comedi_async *async)
537 {
538 int count;
539 unsigned int nbytes, old_alloc_count;
540 const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
541
542 old_alloc_count = async->buf_write_alloc_count;
543 /* write alloc as much as we can */
544 comedi_buf_write_alloc(async, async->prealloc_bufsz);
545
546 nbytes = mite_bytes_written_to_memory_lb(mite_chan);
547 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
548 old_alloc_count) > 0) {
549 dev_warn(async->subdevice->device->class_dev,
550 "mite: DMA overwrite of free area\n");
551 async->events |= COMEDI_CB_OVERFLOW;
552 return -1;
553 }
554
555 count = nbytes - async->buf_write_count;
556 /* it's possible count will be negative due to
557 * conservative value returned by mite_bytes_written_to_memory_lb */
558 if (count <= 0)
559 return 0;
560
561 comedi_buf_write_free(async, count);
562
563 async->scan_progress += count;
564 if (async->scan_progress >= bytes_per_scan) {
565 async->scan_progress %= bytes_per_scan;
566 async->events |= COMEDI_CB_EOS;
567 }
568 async->events |= COMEDI_CB_BLOCK;
569 return 0;
570 }
571 EXPORT_SYMBOL_GPL(mite_sync_input_dma);
572
573 int mite_sync_output_dma(struct mite_channel *mite_chan,
574 struct comedi_async *async)
575 {
576 int count;
577 u32 nbytes_ub, nbytes_lb;
578 unsigned int old_alloc_count;
579 u32 stop_count =
580 async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
581
582 old_alloc_count = async->buf_read_alloc_count;
583 /* read alloc as much as we can */
584 comedi_buf_read_alloc(async, async->prealloc_bufsz);
585 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
586 if (async->cmd.stop_src == TRIG_COUNT &&
587 (int)(nbytes_lb - stop_count) > 0)
588 nbytes_lb = stop_count;
589 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
590 if (async->cmd.stop_src == TRIG_COUNT &&
591 (int)(nbytes_ub - stop_count) > 0)
592 nbytes_ub = stop_count;
593 if ((int)(nbytes_ub - old_alloc_count) > 0) {
594 dev_warn(async->subdevice->device->class_dev,
595 "mite: DMA underrun\n");
596 async->events |= COMEDI_CB_OVERFLOW;
597 return -1;
598 }
599 count = nbytes_lb - async->buf_read_count;
600 if (count <= 0)
601 return 0;
602
603 if (count) {
604 comedi_buf_read_free(async, count);
605 async->events |= COMEDI_CB_BLOCK;
606 }
607 return 0;
608 }
609 EXPORT_SYMBOL_GPL(mite_sync_output_dma);
610
611 unsigned mite_get_status(struct mite_channel *mite_chan)
612 {
613 struct mite_struct *mite = mite_chan->mite;
614 unsigned status;
615 unsigned long flags;
616
617 spin_lock_irqsave(&mite->lock, flags);
618 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
619 if (status & CHSR_DONE) {
620 mite_chan->done = 1;
621 writel(CHOR_CLRDONE,
622 mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
623 }
624 mmiowb();
625 spin_unlock_irqrestore(&mite->lock, flags);
626 return status;
627 }
628 EXPORT_SYMBOL_GPL(mite_get_status);
629
630 int mite_done(struct mite_channel *mite_chan)
631 {
632 struct mite_struct *mite = mite_chan->mite;
633 unsigned long flags;
634 int done;
635
636 mite_get_status(mite_chan);
637 spin_lock_irqsave(&mite->lock, flags);
638 done = mite_chan->done;
639 spin_unlock_irqrestore(&mite->lock, flags);
640 return done;
641 }
642 EXPORT_SYMBOL_GPL(mite_done);
643
644 #ifdef DEBUG_MITE
645
646 /* names of bits in mite registers */
647
648 static const char *const mite_CHOR_strings[] = {
649 "start", "cont", "stop", "abort",
650 "freset", "clrlc", "clrrb", "clrdone",
651 "clr_lpause", "set_lpause", "clr_send_tc",
652 "set_send_tc", "12", "13", "14",
653 "15", "16", "17", "18",
654 "19", "20", "21", "22",
655 "23", "24", "25", "26",
656 "27", "28", "29", "30",
657 "dmareset",
658 };
659
660 static const char *const mite_CHCR_strings[] = {
661 "continue", "ringbuff", "2", "3",
662 "4", "5", "6", "7",
663 "8", "9", "10", "11",
664 "12", "13", "bursten", "fifodis",
665 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
666 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
667 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
668 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
669 };
670
671 static const char *const mite_MCR_strings[] = {
672 "amdevice", "1", "2", "3",
673 "4", "5", "portio", "portvxi",
674 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
675 "12", "13", "blocken", "berhand",
676 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
677 "rd512", "rl1", "rl2", "rl8",
678 "24", "25", "26", "27",
679 "28", "29", "30", "stopen",
680 };
681
682 static const char *const mite_DCR_strings[] = {
683 "amdevice", "1", "2", "3",
684 "4", "5", "portio", "portvxi",
685 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
686 "aseqxp8", "13", "blocken", "berhand",
687 "reqsintlim", "reqs1", "reqs2", "rd32",
688 "rd512", "rl1", "rl2", "rl8",
689 "23", "24", "25", "27",
690 "28", "wsdevc", "wsdevs", "rwdevpack",
691 };
692
693 static const char *const mite_LKCR_strings[] = {
694 "amdevice", "1", "2", "3",
695 "4", "5", "portio", "portvxi",
696 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
697 "12", "13", "14", "berhand",
698 "16", "17", "18", "rd32",
699 "rd512", "rl1", "rl2", "rl8",
700 "24", "25", "26", "27",
701 "28", "29", "30", "chngend",
702 };
703
704 static const char *const mite_CHSR_strings[] = {
705 "d.err0", "d.err1", "m.err0", "m.err1",
706 "l.err0", "l.err1", "drq0", "drq1",
707 "end", "xferr", "operr0", "operr1",
708 "stops", "habort", "sabort", "error",
709 "16", "conts_rb", "18", "linkc",
710 "20", "drdy", "22", "mrdy",
711 "24", "done", "26", "sars",
712 "28", "lpauses", "30", "int",
713 };
714
715 static void mite_decode(const char *const *bit_str, unsigned int bits)
716 {
717 int i;
718
719 for (i = 31; i >= 0; i--) {
720 if (bits & (1 << i))
721 pr_debug(" %s\n", bit_str[i]);
722 }
723 }
724
725 void mite_dump_regs(struct mite_channel *mite_chan)
726 {
727 void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
728 unsigned int offset;
729 unsigned int value;
730 int channel = mite_chan->channel;
731
732 pr_debug("mite_dump_regs ch%i\n", channel);
733 pr_debug("mite address is =%p\n", mite_io_addr);
734
735 offset = MITE_CHOR(channel);
736 value = readl(mite_io_addr + offset);
737 pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
738 mite_decode(mite_CHOR_strings, value);
739 offset = MITE_CHCR(channel);
740 value = readl(mite_io_addr + offset);
741 pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
742 mite_decode(mite_CHCR_strings, value);
743 offset = MITE_TCR(channel);
744 value = readl(mite_io_addr + offset);
745 pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
746 offset = MITE_MCR(channel);
747 value = readl(mite_io_addr + offset);
748 pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
749 mite_decode(mite_MCR_strings, value);
750 offset = MITE_MAR(channel);
751 value = readl(mite_io_addr + offset);
752 pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
753 offset = MITE_DCR(channel);
754 value = readl(mite_io_addr + offset);
755 pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
756 mite_decode(mite_DCR_strings, value);
757 offset = MITE_DAR(channel);
758 value = readl(mite_io_addr + offset);
759 pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
760 offset = MITE_LKCR(channel);
761 value = readl(mite_io_addr + offset);
762 pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
763 mite_decode(mite_LKCR_strings, value);
764 offset = MITE_LKAR(channel);
765 value = readl(mite_io_addr + offset);
766 pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
767 offset = MITE_CHSR(channel);
768 value = readl(mite_io_addr + offset);
769 pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
770 mite_decode(mite_CHSR_strings, value);
771 offset = MITE_FCR(channel);
772 value = readl(mite_io_addr + offset);
773 pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
774 }
775 EXPORT_SYMBOL_GPL(mite_dump_regs);
776 #endif
777
778 static int __init mite_module_init(void)
779 {
780 return 0;
781 }
782
783 static void __exit mite_module_exit(void)
784 {
785 }
786
787 module_init(mite_module_init);
788 module_exit(mite_module_exit);
789
790 MODULE_AUTHOR("Comedi http://www.comedi.org");
791 MODULE_DESCRIPTION("Comedi low-level driver");
792 MODULE_LICENSE("GPL");
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