?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'for-3.11' of git://linux-nfs.org/~bfields/linux
[linux-2.6.git] / drivers / staging / comedi / drivers / amplc_dio200_pci.c
blobd7d9f5cc3ab40fe81dc074f588c863871b34948a
1 /* comedi/drivers/amplc_dio200_pci.c
2
3 Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296.
4
5 Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
6
7 COMEDI - Linux Control and Measurement Device Interface
8 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19 */
20 /*
21 * Driver: amplc_dio200_pci
22 * Description: Amplicon 200 Series PCI Digital I/O
23 * Author: Ian Abbott <abbotti@mev.co.uk>
24 * Devices: [Amplicon] PCI215 (amplc_dio200_pci), PCIe215, PCIe236,
25 * PCI272, PCIe296
26 * Updated: Mon, 18 Mar 2013 15:03:50 +0000
27 * Status: works
28 *
29 * Configuration options:
30 * none
31 *
32 * Manual configuration of PCI(e) cards is not supported; they are configured
33 * automatically.
34 *
35 * SUBDEVICES
36 *
37 * PCI215 PCIe215 PCIe236
38 * ------------- ------------- -------------
39 * Subdevices 5 8 8
40 * 0 PPI-X PPI-X PPI-X
41 * 1 PPI-Y UNUSED UNUSED
42 * 2 CTR-Z1 PPI-Y UNUSED
43 * 3 CTR-Z2 UNUSED UNUSED
44 * 4 INTERRUPT CTR-Z1 CTR-Z1
45 * 5 CTR-Z2 CTR-Z2
46 * 6 TIMER TIMER
47 * 7 INTERRUPT INTERRUPT
48 *
49 *
50 * PCI272 PCIe296
51 * ------------- -------------
52 * Subdevices 4 8
53 * 0 PPI-X PPI-X1
54 * 1 PPI-Y PPI-X2
55 * 2 PPI-Z PPI-Y1
56 * 3 INTERRUPT PPI-Y2
57 * 4 CTR-Z1
58 * 5 CTR-Z2
59 * 6 TIMER
60 * 7 INTERRUPT
61 *
62 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
63 * are configurable as inputs or outputs in four groups:
64 *
65 * Port A - channels 0 to 7
66 * Port B - channels 8 to 15
67 * Port CL - channels 16 to 19
68 * Port CH - channels 20 to 23
69 *
70 * Only mode 0 of the 8255 chips is supported.
71 *
72 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
73 * channel is configured individually with INSN_CONFIG instructions. The
74 * specific type of configuration instruction is specified in data[0].
75 * Some configuration instructions expect an additional parameter in
76 * data[1]; others return a value in data[1]. The following configuration
77 * instructions are supported:
78 *
79 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
80 * BCD/binary setting specified in data[1].
81 *
82 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
83 * counter channel into data[1].
84 *
85 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
86 * specified in data[1] (this is a hardware-specific value). Not
87 * supported on PC214E. For the other boards, valid clock sources are
88 * 0 to 7 as follows:
89 *
90 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
91 * connector. (N.B. for other values, the counter channel's CLKn
92 * pin on the SK1 connector is an output!)
93 * 1. Internal 10 MHz clock.
94 * 2. Internal 1 MHz clock.
95 * 3. Internal 100 kHz clock.
96 * 4. Internal 10 kHz clock.
97 * 5. Internal 1 kHz clock.
98 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
99 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
100 * the SK1 connector. This pin is shared by all three counter
101 * channels on the chip.
102 *
103 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
104 * and the following additional clock sources are defined:
105 *
106 * 8. HIGH logic level.
107 * 9. LOW logic level.
108 * 10. "Pattern present" signal.
109 * 11. Internal 20 MHz clock.
110 *
111 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
112 * clock source in data[1]. For internal clock sources, data[2] is set
113 * to the period in ns.
114 *
115 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
116 * specified in data[2] (this is a hardware-specific value). Not
117 * supported on PC214E. For the other boards, valid gate sources are 0
118 * to 7 as follows:
119 *
120 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
121 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
122 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
123 * connector. (N.B. for other values, the counter channel's GATn
124 * pin on the SK1 connector is an output!)
125 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
126 * 2 below).
127 * 4. Reserved.
128 * 5. Reserved.
129 * 6. Reserved.
130 * 7. Reserved.
131 *
132 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
133 * the following additional clock sources and clock sources 6 and 7 are
134 * (re)defined:
135 *
136 * 6. /GAT n, negated version of the counter channel's dedicated
137 * GAT input (negated version of gate source 2).
138 * 7. OUT n-2, the non-inverted output of counter channel n-2
139 * (negated version of gate source 3).
140 * 8. "Pattern present" signal, HIGH while pattern present.
141 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
142 * occurs.
143 * 10. "Pattern gone away" latched signal, latches LOW when pattern
144 * goes away after it occurred.
145 * 11. Negated "pattern present" signal, LOW while pattern present
146 * (negated version of gate source 8).
147 * 12. Negated "pattern occurred" latched signal, latches LOW when
148 * pattern occurs (negated version of gate source 9).
149 * 13. Negated "pattern gone away" latched signal, latches LOW when
150 * pattern goes away after it occurred (negated version of gate
151 * source 10).
152 *
153 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
154 * source in data[2].
155 *
156 * Clock and gate interconnection notes:
157 *
158 * 1. Clock source OUT n-1 is the output of the preceding channel on the
159 * same counter subdevice if n > 0, or the output of channel 2 on the
160 * preceding counter subdevice (see note 3) if n = 0.
161 *
162 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
163 * same counter subdevice if n = 2, or the inverted output of channel n+1
164 * on the preceding counter subdevice (see note 3) if n < 2.
165 *
166 * 3. The counter subdevices are connected in a ring, so the highest
167 * counter subdevice precedes the lowest.
168 *
169 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
170 *
171 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
172 * digital inputs come from the interrupt status register. The number of
173 * channels matches the number of interrupt sources. The PC214E does not
174 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
175 * below.
176 *
177 * INTERRUPT SOURCES
178 *
179 * PCI215 PCIe215 PCIe236
180 * ------------- ------------- -------------
181 * Sources 6 6 6
182 * 0 PPI-X-C0 PPI-X-C0 PPI-X-C0
183 * 1 PPI-X-C3 PPI-X-C3 PPI-X-C3
184 * 2 PPI-Y-C0 PPI-Y-C0 unused
185 * 3 PPI-Y-C3 PPI-Y-C3 unused
186 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
187 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
188 *
189 * PCI272 PCIe296
190 * ------------- -------------
191 * Sources 6 6
192 * 0 PPI-X-C0 PPI-X1-C0
193 * 1 PPI-X-C3 PPI-X1-C3
194 * 2 PPI-Y-C0 PPI-Y1-C0
195 * 3 PPI-Y-C3 PPI-Y1-C3
196 * 4 PPI-Z-C0 CTR-Z1-OUT1
197 * 5 PPI-Z-C3 CTR-Z2-OUT1
198 *
199 * When an interrupt source is enabled in the interrupt source enable
200 * register, a rising edge on the source signal latches the corresponding
201 * bit to 1 in the interrupt status register.
202 *
203 * When the interrupt status register value as a whole (actually, just the
204 * 6 least significant bits) goes from zero to non-zero, the board will
205 * generate an interrupt. The interrupt will remain asserted until the
206 * interrupt status register is cleared to zero. To clear a bit to zero in
207 * the interrupt status register, the corresponding interrupt source must
208 * be disabled in the interrupt source enable register (there is no
209 * separate interrupt clear register).
210 *
211 * COMMANDS
212 *
213 * The driver supports a read streaming acquisition command on the
214 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
215 * to be enabled. All channels will be sampled together (convert_src ==
216 * TRIG_NOW). The scan begins a short time after the hardware interrupt
217 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
218 * scan_begin_arg == 0). The value read from the interrupt status register
219 * is packed into a short value, one bit per requested channel, in the
220 * order they appear in the channel list.
221 */
222
223 #include <linux/pci.h>
224 #include <linux/interrupt.h>
225 #include <linux/slab.h>
226
227 #include "../comedidev.h"
228
229 #include "amplc_dio200.h"
230
231 /* PCI IDs */
232 #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a
233 #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b
234 #define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011
235 #define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012
236 #define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014
237
238 /*
239 * Board descriptions.
240 */
241
242 enum dio200_pci_model {
243 pci215_model,
244 pci272_model,
245 pcie215_model,
246 pcie236_model,
247 pcie296_model
248 };
249
250 static const struct dio200_board dio200_pci_boards[] = {
251 [pci215_model] = {
252 .name = "pci215",
253 .bustype = pci_bustype,
254 .mainbar = 2,
255 .mainsize = DIO200_IO_SIZE,
256 .layout = {
257 .n_subdevs = 5,
258 .sdtype = {sd_8255, sd_8255, sd_8254, sd_8254, sd_intr},
259 .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
260 .has_int_sce = true,
261 .has_clk_gat_sce = true,
262 },
263 },
264 [pci272_model] = {
265 .name = "pci272",
266 .bustype = pci_bustype,
267 .mainbar = 2,
268 .mainsize = DIO200_IO_SIZE,
269 .layout = {
270 .n_subdevs = 4,
271 .sdtype = {sd_8255, sd_8255, sd_8255, sd_intr},
272 .sdinfo = {0x00, 0x08, 0x10, 0x3F},
273 .has_int_sce = true,
274 },
275 },
276 [pcie215_model] = {
277 .name = "pcie215",
278 .bustype = pci_bustype,
279 .mainbar = 1,
280 .mainshift = 3,
281 .mainsize = DIO200_PCIE_IO_SIZE,
282 .layout = {
283 .n_subdevs = 8,
284 .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
285 sd_8254, sd_8254, sd_timer, sd_intr},
286 .sdinfo = {0x00, 0x00, 0x08, 0x00,
287 0x10, 0x14, 0x00, 0x3F},
288 .has_int_sce = true,
289 .has_clk_gat_sce = true,
290 .has_enhancements = true,
291 },
292 },
293 [pcie236_model] = {
294 .name = "pcie236",
295 .bustype = pci_bustype,
296 .mainbar = 1,
297 .mainshift = 3,
298 .mainsize = DIO200_PCIE_IO_SIZE,
299 .layout = {
300 .n_subdevs = 8,
301 .sdtype = {sd_8255, sd_none, sd_none, sd_none,
302 sd_8254, sd_8254, sd_timer, sd_intr},
303 .sdinfo = {0x00, 0x00, 0x00, 0x00,
304 0x10, 0x14, 0x00, 0x3F},
305 .has_int_sce = true,
306 .has_clk_gat_sce = true,
307 .has_enhancements = true,
308 },
309 },
310 [pcie296_model] = {
311 .name = "pcie296",
312 .bustype = pci_bustype,
313 .mainbar = 1,
314 .mainshift = 3,
315 .mainsize = DIO200_PCIE_IO_SIZE,
316 .layout = {
317 .n_subdevs = 8,
318 .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
319 sd_8254, sd_8254, sd_timer, sd_intr},
320 .sdinfo = {0x00, 0x04, 0x08, 0x0C,
321 0x10, 0x14, 0x00, 0x3F},
322 .has_int_sce = true,
323 .has_clk_gat_sce = true,
324 .has_enhancements = true,
325 },
326 },
327 };
328
329 /*
330 * This function does some special set-up for the PCIe boards
331 * PCIe215, PCIe236, PCIe296.
332 */
333 static int dio200_pcie_board_setup(struct comedi_device *dev)
334 {
335 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
336 void __iomem *brbase;
337
338 /*
339 * The board uses Altera Cyclone IV with PCI-Express hard IP.
340 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
341 * Control registers in PCI BAR 0, offset 0, and the length of
342 * these registers is 0x4000.
343 *
344 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
345 * Enable" register at offset 0x50 to allow generation of PCIe
346 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
347 */
348 if (pci_resource_len(pcidev, 0) < 0x4000) {
349 dev_err(dev->class_dev, "error! bad PCI region!\n");
350 return -EINVAL;
351 }
352 brbase = pci_ioremap_bar(pcidev, 0);
353 if (!brbase) {
354 dev_err(dev->class_dev, "error! failed to map registers!\n");
355 return -ENOMEM;
356 }
357 writel(0x80, brbase + 0x50);
358 iounmap(brbase);
359 /* Enable "enhanced" features of board. */
360 amplc_dio200_set_enhance(dev, 1);
361 return 0;
362 }
363
364 static int dio200_pci_auto_attach(struct comedi_device *dev,
365 unsigned long context_model)
366 {
367 struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
368 const struct dio200_board *thisboard = NULL;
369 struct dio200_private *devpriv;
370 unsigned int bar;
371 int ret;
372
373 if (context_model < ARRAY_SIZE(dio200_pci_boards))
374 thisboard = &dio200_pci_boards[context_model];
375 if (!thisboard)
376 return -EINVAL;
377 dev->board_ptr = thisboard;
378 dev->board_name = thisboard->name;
379
380 dev_info(dev->class_dev, "%s: attach pci %s (%s)\n",
381 dev->driver->driver_name, pci_name(pci_dev), dev->board_name);
382
383 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
384 if (!devpriv)
385 return -ENOMEM;
386 dev->private = devpriv;
387
388 ret = comedi_pci_enable(dev);
389 if (ret)
390 return ret;
391
392 bar = thisboard->mainbar;
393 if (pci_resource_len(pci_dev, bar) < thisboard->mainsize) {
394 dev_err(dev->class_dev, "error! PCI region size too small!\n");
395 return -EINVAL;
396 }
397 if (pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) {
398 devpriv->io.u.membase = pci_ioremap_bar(pci_dev, bar);
399 if (!devpriv->io.u.membase) {
400 dev_err(dev->class_dev,
401 "error! cannot remap registers\n");
402 return -ENOMEM;
403 }
404 devpriv->io.regtype = mmio_regtype;
405 } else {
406 devpriv->io.u.iobase = pci_resource_start(pci_dev, bar);
407 devpriv->io.regtype = io_regtype;
408 }
409 switch (context_model) {
410 case pcie215_model:
411 case pcie236_model:
412 case pcie296_model:
413 ret = dio200_pcie_board_setup(dev);
414 if (ret < 0)
415 return ret;
416 break;
417 default:
418 break;
419 }
420 return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
421 }
422
423 static void dio200_pci_detach(struct comedi_device *dev)
424 {
425 const struct dio200_board *thisboard = comedi_board(dev);
426 struct dio200_private *devpriv = dev->private;
427
428 if (!thisboard || !devpriv)
429 return;
430 amplc_dio200_common_detach(dev);
431 if (devpriv->io.regtype == mmio_regtype)
432 iounmap(devpriv->io.u.membase);
433 comedi_pci_disable(dev);
434 }
435
436 static struct comedi_driver dio200_pci_comedi_driver = {
437 .driver_name = "amplc_dio200_pci",
438 .module = THIS_MODULE,
439 .auto_attach = dio200_pci_auto_attach,
440 .detach = dio200_pci_detach,
441 };
442
443 static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = {
444 {
445 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215),
446 pci215_model
447 }, {
448 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272),
449 pci272_model
450 }, {
451 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236),
452 pcie236_model
453 }, {
454 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215),
455 pcie215_model
456 }, {
457 PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296),
458 pcie296_model
459 },
460 {0}
461 };
462
463 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
464
465 static int dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
466 {
467 return comedi_pci_auto_config(dev, &dio200_pci_comedi_driver,
468 id->driver_data);
469 }
470
471 static struct pci_driver dio200_pci_pci_driver = {
472 .name = "amplc_dio200_pci",
473 .id_table = dio200_pci_table,
474 .probe = dio200_pci_probe,
475 .remove = comedi_pci_auto_unconfig,
476 };
477 module_comedi_pci_driver(dio200_pci_comedi_driver, dio200_pci_pci_driver);
478
479 MODULE_AUTHOR("Comedi http://www.comedi.org");
480 MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series PCI(e) DIO boards");
481 MODULE_LICENSE("GPL");
Linus' kernel tree