2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
39 #define DP_RECEIVER_CAP_SIZE 0xf
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
46 struct intel_encoder base
;
49 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
56 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
57 struct i2c_adapter adapter
;
58 struct i2c_algo_dp_aux_data algo
;
61 int panel_power_up_delay
;
62 int panel_power_down_delay
;
63 int panel_power_cycle_delay
;
64 int backlight_on_delay
;
65 int backlight_off_delay
;
66 struct drm_display_mode
*panel_fixed_mode
; /* for eDP */
67 struct delayed_work panel_vdd_work
;
72 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
73 * @intel_dp: DP struct
75 * If a CPU or PCH DP output is attached to an eDP panel, this function
76 * will return true, and false otherwise.
78 static bool is_edp(struct intel_dp
*intel_dp
)
80 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
84 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
85 * @intel_dp: DP struct
87 * Returns true if the given DP struct corresponds to a PCH DP port attached
88 * to an eDP panel, false otherwise. Helpful for determining whether we
89 * may need FDI resources for a given DP output or not.
91 static bool is_pch_edp(struct intel_dp
*intel_dp
)
93 return intel_dp
->is_pch_edp
;
97 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
98 * @intel_dp: DP struct
100 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
104 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
107 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
109 return container_of(encoder
, struct intel_dp
, base
.base
);
112 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
114 return container_of(intel_attached_encoder(connector
),
115 struct intel_dp
, base
);
119 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
120 * @encoder: DRM encoder
122 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
123 * by intel_display.c.
125 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
127 struct intel_dp
*intel_dp
;
132 intel_dp
= enc_to_intel_dp(encoder
);
134 return is_pch_edp(intel_dp
);
137 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
138 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
139 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
142 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
143 int *lane_num
, int *link_bw
)
145 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
147 *lane_num
= intel_dp
->lane_count
;
148 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
150 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
155 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
157 int max_lane_count
= 4;
159 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
160 max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
161 switch (max_lane_count
) {
162 case 1: case 2: case 4:
168 return max_lane_count
;
172 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
174 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
176 switch (max_link_bw
) {
177 case DP_LINK_BW_1_62
:
181 max_link_bw
= DP_LINK_BW_1_62
;
188 intel_dp_link_clock(uint8_t link_bw
)
190 if (link_bw
== DP_LINK_BW_2_7
)
197 * The units on the numbers in the next two are... bizarre. Examples will
198 * make it clearer; this one parallels an example in the eDP spec.
200 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
202 * 270000 * 1 * 8 / 10 == 216000
204 * The actual data capacity of that configuration is 2.16Gbit/s, so the
205 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
206 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
207 * 119000. At 18bpp that's 2142000 kilobits per second.
209 * Thus the strange-looking division by 10 in intel_dp_link_required, to
210 * get the result in decakilobits instead of kilobits.
214 intel_dp_link_required(struct intel_dp
*intel_dp
, int pixel_clock
)
216 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
221 bpp
= intel_crtc
->bpp
;
223 return (pixel_clock
* bpp
+ 9) / 10;
227 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
229 return (max_link_clock
* max_lanes
* 8) / 10;
233 intel_dp_mode_valid(struct drm_connector
*connector
,
234 struct drm_display_mode
*mode
)
236 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
237 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
238 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
240 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
241 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
244 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
248 if (intel_dp_link_required(intel_dp
, mode
->clock
)
249 > intel_dp_max_data_rate(max_link_clock
, max_lanes
))
250 return MODE_CLOCK_HIGH
;
252 if (mode
->clock
< 10000)
253 return MODE_CLOCK_LOW
;
259 pack_aux(uint8_t *src
, int src_bytes
)
266 for (i
= 0; i
< src_bytes
; i
++)
267 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
272 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
277 for (i
= 0; i
< dst_bytes
; i
++)
278 dst
[i
] = src
>> ((3-i
) * 8);
281 /* hrawclock is 1/4 the FSB frequency */
283 intel_hrawclk(struct drm_device
*dev
)
285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
288 clkcfg
= I915_READ(CLKCFG
);
289 switch (clkcfg
& CLKCFG_FSB_MASK
) {
298 case CLKCFG_FSB_1067
:
300 case CLKCFG_FSB_1333
:
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600
:
304 case CLKCFG_FSB_1600_ALT
:
311 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
313 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
319 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
328 intel_dp_check_edp(struct intel_dp
*intel_dp
)
330 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 if (!is_edp(intel_dp
))
335 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
338 I915_READ(PCH_PP_STATUS
),
339 I915_READ(PCH_PP_CONTROL
));
344 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
345 uint8_t *send
, int send_bytes
,
346 uint8_t *recv
, int recv_size
)
348 uint32_t output_reg
= intel_dp
->output_reg
;
349 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 uint32_t ch_ctl
= output_reg
+ 0x10;
352 uint32_t ch_data
= ch_ctl
+ 4;
356 uint32_t aux_clock_divider
;
359 intel_dp_check_edp(intel_dp
);
360 /* The clock divider is based off the hrawclk,
361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
364 * Note that PCH attached eDP panels should use a 125MHz input
367 if (is_cpu_edp(intel_dp
)) {
369 aux_clock_divider
= 200; /* SNB eDP input clock at 400Mhz */
371 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
372 } else if (HAS_PCH_SPLIT(dev
))
373 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
375 aux_clock_divider
= intel_hrawclk(dev
) / 2;
382 /* Try to wait for any previous AUX channel activity */
383 for (try = 0; try < 3; try++) {
384 status
= I915_READ(ch_ctl
);
385 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
391 WARN(1, "dp_aux_ch not started status 0x%08x\n",
396 /* Must try at least 3 times according to DP spec */
397 for (try = 0; try < 5; try++) {
398 /* Load the send data into the aux channel data registers */
399 for (i
= 0; i
< send_bytes
; i
+= 4)
400 I915_WRITE(ch_data
+ i
,
401 pack_aux(send
+ i
, send_bytes
- i
));
403 /* Send the command and wait for it to complete */
405 DP_AUX_CH_CTL_SEND_BUSY
|
406 DP_AUX_CH_CTL_TIME_OUT_400us
|
407 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
408 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
409 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
411 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
412 DP_AUX_CH_CTL_RECEIVE_ERROR
);
414 status
= I915_READ(ch_ctl
);
415 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
420 /* Clear done status and any errors */
424 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
425 DP_AUX_CH_CTL_RECEIVE_ERROR
);
426 if (status
& DP_AUX_CH_CTL_DONE
)
430 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
431 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
435 /* Check for timeout or receive error.
436 * Timeouts occur when the sink is not connected
438 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
439 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
443 /* Timeouts occur when the device isn't connected, so they're
444 * "normal" -- don't fill the kernel log with these */
445 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
446 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
450 /* Unload any bytes sent back from the other side */
451 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
452 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
453 if (recv_bytes
> recv_size
)
454 recv_bytes
= recv_size
;
456 for (i
= 0; i
< recv_bytes
; i
+= 4)
457 unpack_aux(I915_READ(ch_data
+ i
),
458 recv
+ i
, recv_bytes
- i
);
463 /* Write data to the aux channel in native mode */
465 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
466 uint16_t address
, uint8_t *send
, int send_bytes
)
473 intel_dp_check_edp(intel_dp
);
476 msg
[0] = AUX_NATIVE_WRITE
<< 4;
477 msg
[1] = address
>> 8;
478 msg
[2] = address
& 0xff;
479 msg
[3] = send_bytes
- 1;
480 memcpy(&msg
[4], send
, send_bytes
);
481 msg_bytes
= send_bytes
+ 4;
483 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
486 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
488 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
496 /* Write a single byte to the aux channel in native mode */
498 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
499 uint16_t address
, uint8_t byte
)
501 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
504 /* read bytes from a native aux channel */
506 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
507 uint16_t address
, uint8_t *recv
, int recv_bytes
)
516 intel_dp_check_edp(intel_dp
);
517 msg
[0] = AUX_NATIVE_READ
<< 4;
518 msg
[1] = address
>> 8;
519 msg
[2] = address
& 0xff;
520 msg
[3] = recv_bytes
- 1;
523 reply_bytes
= recv_bytes
+ 1;
526 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
533 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
534 memcpy(recv
, reply
+ 1, ret
- 1);
537 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
545 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
546 uint8_t write_byte
, uint8_t *read_byte
)
548 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
549 struct intel_dp
*intel_dp
= container_of(adapter
,
552 uint16_t address
= algo_data
->address
;
560 intel_dp_check_edp(intel_dp
);
561 /* Set up the command byte */
562 if (mode
& MODE_I2C_READ
)
563 msg
[0] = AUX_I2C_READ
<< 4;
565 msg
[0] = AUX_I2C_WRITE
<< 4;
567 if (!(mode
& MODE_I2C_STOP
))
568 msg
[0] |= AUX_I2C_MOT
<< 4;
570 msg
[1] = address
>> 8;
591 for (retry
= 0; retry
< 5; retry
++) {
592 ret
= intel_dp_aux_ch(intel_dp
,
596 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
600 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
601 case AUX_NATIVE_REPLY_ACK
:
602 /* I2C-over-AUX Reply field is only valid
603 * when paired with AUX ACK.
606 case AUX_NATIVE_REPLY_NACK
:
607 DRM_DEBUG_KMS("aux_ch native nack\n");
609 case AUX_NATIVE_REPLY_DEFER
:
613 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
618 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
619 case AUX_I2C_REPLY_ACK
:
620 if (mode
== MODE_I2C_READ
) {
621 *read_byte
= reply
[1];
623 return reply_bytes
- 1;
624 case AUX_I2C_REPLY_NACK
:
625 DRM_DEBUG_KMS("aux_i2c nack\n");
627 case AUX_I2C_REPLY_DEFER
:
628 DRM_DEBUG_KMS("aux_i2c defer\n");
632 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
637 DRM_ERROR("too many retries, giving up\n");
641 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
642 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
645 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
646 struct intel_connector
*intel_connector
, const char *name
)
650 DRM_DEBUG_KMS("i2c_init %s\n", name
);
651 intel_dp
->algo
.running
= false;
652 intel_dp
->algo
.address
= 0;
653 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
655 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
656 intel_dp
->adapter
.owner
= THIS_MODULE
;
657 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
658 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
659 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
660 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
661 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
663 ironlake_edp_panel_vdd_on(intel_dp
);
664 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
665 ironlake_edp_panel_vdd_off(intel_dp
, false);
670 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
671 struct drm_display_mode
*adjusted_mode
)
673 struct drm_device
*dev
= encoder
->dev
;
674 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
675 int lane_count
, clock
;
676 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
677 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
678 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
680 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
681 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
682 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
683 mode
, adjusted_mode
);
685 * the mode->clock is used to calculate the Data&Link M/N
686 * of the pipe. For the eDP the fixed clock should be used.
688 mode
->clock
= intel_dp
->panel_fixed_mode
->clock
;
691 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
692 for (clock
= 0; clock
<= max_clock
; clock
++) {
693 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
695 if (intel_dp_link_required(intel_dp
, mode
->clock
)
697 intel_dp
->link_bw
= bws
[clock
];
698 intel_dp
->lane_count
= lane_count
;
699 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
700 DRM_DEBUG_KMS("Display port link bw %02x lane "
701 "count %d clock %d\n",
702 intel_dp
->link_bw
, intel_dp
->lane_count
,
703 adjusted_mode
->clock
);
712 struct intel_dp_m_n
{
721 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
723 while (*num
> 0xffffff || *den
> 0xffffff) {
730 intel_dp_compute_m_n(int bpp
,
734 struct intel_dp_m_n
*m_n
)
737 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
738 m_n
->gmch_n
= link_clock
* nlanes
;
739 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
740 m_n
->link_m
= pixel_clock
;
741 m_n
->link_n
= link_clock
;
742 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
746 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
747 struct drm_display_mode
*adjusted_mode
)
749 struct drm_device
*dev
= crtc
->dev
;
750 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
751 struct drm_encoder
*encoder
;
752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
753 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
755 struct intel_dp_m_n m_n
;
756 int pipe
= intel_crtc
->pipe
;
759 * Find the lane count in the intel_encoder private
761 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
762 struct intel_dp
*intel_dp
;
764 if (encoder
->crtc
!= crtc
)
767 intel_dp
= enc_to_intel_dp(encoder
);
768 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
|| is_pch_edp(intel_dp
)) {
769 lane_count
= intel_dp
->lane_count
;
771 } else if (is_cpu_edp(intel_dp
)) {
772 lane_count
= dev_priv
->edp
.lanes
;
778 * Compute the GMCH and Link ratios. The '3' here is
779 * the number of bytes_per_pixel post-LUT, which we always
780 * set up for 8-bits of R/G/B, or 3 bytes total.
782 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
783 mode
->clock
, adjusted_mode
->clock
, &m_n
);
785 if (HAS_PCH_SPLIT(dev
)) {
786 I915_WRITE(TRANSDATA_M1(pipe
),
787 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
789 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
790 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
791 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
793 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
794 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
796 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
797 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
798 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
802 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
);
803 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
);
806 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
807 struct drm_display_mode
*adjusted_mode
)
809 struct drm_device
*dev
= encoder
->dev
;
810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
811 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
812 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
813 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
815 /* Turn on the eDP PLL if needed */
816 if (is_edp(intel_dp
)) {
817 if (!is_pch_edp(intel_dp
))
818 ironlake_edp_pll_on(encoder
);
820 ironlake_edp_pll_off(encoder
);
824 * There are three kinds of DP registers:
830 * IBX PCH and CPU are the same for almost everything,
831 * except that the CPU DP PLL is configured in this
834 * CPT PCH is quite different, having many bits moved
835 * to the TRANS_DP_CTL register instead. That
836 * configuration happens (oddly) in ironlake_pch_enable
839 /* Preserve the BIOS-computed detected bit. This is
840 * supposed to be read-only.
842 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
843 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
845 /* Handle DP bits in common between all three register formats */
847 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
849 switch (intel_dp
->lane_count
) {
851 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
854 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
857 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
860 if (intel_dp
->has_audio
) {
861 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
862 pipe_name(intel_crtc
->pipe
));
863 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
864 intel_write_eld(encoder
, adjusted_mode
);
866 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
867 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
868 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
869 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
871 * Check for DPCD version > 1.1 and enhanced framing support
873 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
874 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
875 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
878 /* Split out the IBX/CPU vs CPT settings */
880 if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
881 intel_dp
->DP
|= intel_dp
->color_range
;
883 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
884 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
885 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
886 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
887 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
889 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
890 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
892 if (intel_crtc
->pipe
== 1)
893 intel_dp
->DP
|= DP_PIPEB_SELECT
;
895 if (is_cpu_edp(intel_dp
)) {
896 /* don't miss out required setting for eDP */
897 intel_dp
->DP
|= DP_PLL_ENABLE
;
898 if (adjusted_mode
->clock
< 200000)
899 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
901 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
904 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
908 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
909 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
911 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
912 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
914 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
915 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
917 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
921 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
924 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
926 I915_READ(PCH_PP_STATUS
),
927 I915_READ(PCH_PP_CONTROL
));
929 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
930 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
931 I915_READ(PCH_PP_STATUS
),
932 I915_READ(PCH_PP_CONTROL
));
936 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
938 DRM_DEBUG_KMS("Wait for panel power on\n");
939 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
942 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
944 DRM_DEBUG_KMS("Wait for panel power off time\n");
945 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
948 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
950 DRM_DEBUG_KMS("Wait for panel power cycle\n");
951 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
955 /* Read the current pp_control value, unlocking the register if it
959 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
961 u32 control
= I915_READ(PCH_PP_CONTROL
);
963 control
&= ~PANEL_UNLOCK_MASK
;
964 control
|= PANEL_UNLOCK_REGS
;
968 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
970 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
974 if (!is_edp(intel_dp
))
976 DRM_DEBUG_KMS("Turn eDP VDD on\n");
978 WARN(intel_dp
->want_panel_vdd
,
979 "eDP VDD already requested on\n");
981 intel_dp
->want_panel_vdd
= true;
983 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
984 DRM_DEBUG_KMS("eDP VDD already on\n");
988 if (!ironlake_edp_have_panel_power(intel_dp
))
989 ironlake_wait_panel_power_cycle(intel_dp
);
991 pp
= ironlake_get_pp_control(dev_priv
);
993 I915_WRITE(PCH_PP_CONTROL
, pp
);
994 POSTING_READ(PCH_PP_CONTROL
);
995 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
996 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
999 * If the panel wasn't on, delay before accessing aux channel
1001 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1002 DRM_DEBUG_KMS("eDP was not running\n");
1003 msleep(intel_dp
->panel_power_up_delay
);
1007 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1009 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1013 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1014 pp
= ironlake_get_pp_control(dev_priv
);
1015 pp
&= ~EDP_FORCE_VDD
;
1016 I915_WRITE(PCH_PP_CONTROL
, pp
);
1017 POSTING_READ(PCH_PP_CONTROL
);
1019 /* Make sure sequencer is idle before allowing subsequent activity */
1020 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1021 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1023 msleep(intel_dp
->panel_power_down_delay
);
1027 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1029 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1030 struct intel_dp
, panel_vdd_work
);
1031 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1033 mutex_lock(&dev
->mode_config
.mutex
);
1034 ironlake_panel_vdd_off_sync(intel_dp
);
1035 mutex_unlock(&dev
->mode_config
.mutex
);
1038 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1040 if (!is_edp(intel_dp
))
1043 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1044 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1046 intel_dp
->want_panel_vdd
= false;
1049 ironlake_panel_vdd_off_sync(intel_dp
);
1052 * Queue the timer to fire a long
1053 * time from now (relative to the power down delay)
1054 * to keep the panel power up across a sequence of operations
1056 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1057 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1061 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1063 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1067 if (!is_edp(intel_dp
))
1070 DRM_DEBUG_KMS("Turn eDP power on\n");
1072 if (ironlake_edp_have_panel_power(intel_dp
)) {
1073 DRM_DEBUG_KMS("eDP power already on\n");
1077 ironlake_wait_panel_power_cycle(intel_dp
);
1079 pp
= ironlake_get_pp_control(dev_priv
);
1081 /* ILK workaround: disable reset around power sequence */
1082 pp
&= ~PANEL_POWER_RESET
;
1083 I915_WRITE(PCH_PP_CONTROL
, pp
);
1084 POSTING_READ(PCH_PP_CONTROL
);
1087 pp
|= POWER_TARGET_ON
;
1089 pp
|= PANEL_POWER_RESET
;
1091 I915_WRITE(PCH_PP_CONTROL
, pp
);
1092 POSTING_READ(PCH_PP_CONTROL
);
1094 ironlake_wait_panel_on(intel_dp
);
1097 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1098 I915_WRITE(PCH_PP_CONTROL
, pp
);
1099 POSTING_READ(PCH_PP_CONTROL
);
1103 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1105 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1109 if (!is_edp(intel_dp
))
1112 DRM_DEBUG_KMS("Turn eDP power off\n");
1114 WARN(intel_dp
->want_panel_vdd
, "Cannot turn power off while VDD is on\n");
1116 pp
= ironlake_get_pp_control(dev_priv
);
1117 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1118 I915_WRITE(PCH_PP_CONTROL
, pp
);
1119 POSTING_READ(PCH_PP_CONTROL
);
1121 ironlake_wait_panel_off(intel_dp
);
1124 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1126 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1130 if (!is_edp(intel_dp
))
1133 DRM_DEBUG_KMS("\n");
1135 * If we enable the backlight right away following a panel power
1136 * on, we may see slight flicker as the panel syncs with the eDP
1137 * link. So delay a bit to make sure the image is solid before
1138 * allowing it to appear.
1140 msleep(intel_dp
->backlight_on_delay
);
1141 pp
= ironlake_get_pp_control(dev_priv
);
1142 pp
|= EDP_BLC_ENABLE
;
1143 I915_WRITE(PCH_PP_CONTROL
, pp
);
1144 POSTING_READ(PCH_PP_CONTROL
);
1147 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1149 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1153 if (!is_edp(intel_dp
))
1156 DRM_DEBUG_KMS("\n");
1157 pp
= ironlake_get_pp_control(dev_priv
);
1158 pp
&= ~EDP_BLC_ENABLE
;
1159 I915_WRITE(PCH_PP_CONTROL
, pp
);
1160 POSTING_READ(PCH_PP_CONTROL
);
1161 msleep(intel_dp
->backlight_off_delay
);
1164 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
1166 struct drm_device
*dev
= encoder
->dev
;
1167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1170 DRM_DEBUG_KMS("\n");
1171 dpa_ctl
= I915_READ(DP_A
);
1172 dpa_ctl
|= DP_PLL_ENABLE
;
1173 I915_WRITE(DP_A
, dpa_ctl
);
1178 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
1180 struct drm_device
*dev
= encoder
->dev
;
1181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1184 dpa_ctl
= I915_READ(DP_A
);
1185 dpa_ctl
&= ~DP_PLL_ENABLE
;
1186 I915_WRITE(DP_A
, dpa_ctl
);
1191 /* If the sink supports it, try to set the power state appropriately */
1192 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1196 /* Should have a valid DPCD by this point */
1197 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1200 if (mode
!= DRM_MODE_DPMS_ON
) {
1201 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1204 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1207 * When turning on, we need to retry for 1ms to give the sink
1210 for (i
= 0; i
< 3; i
++) {
1211 ret
= intel_dp_aux_native_write_1(intel_dp
,
1221 static void intel_dp_prepare(struct drm_encoder
*encoder
)
1223 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1225 ironlake_edp_backlight_off(intel_dp
);
1226 ironlake_edp_panel_off(intel_dp
);
1228 /* Wake up the sink first */
1229 ironlake_edp_panel_vdd_on(intel_dp
);
1230 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1231 intel_dp_link_down(intel_dp
);
1232 ironlake_edp_panel_vdd_off(intel_dp
, false);
1234 /* Make sure the panel is off before trying to
1239 static void intel_dp_commit(struct drm_encoder
*encoder
)
1241 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1242 struct drm_device
*dev
= encoder
->dev
;
1243 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1245 ironlake_edp_panel_vdd_on(intel_dp
);
1246 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1247 intel_dp_start_link_train(intel_dp
);
1248 ironlake_edp_panel_on(intel_dp
);
1249 ironlake_edp_panel_vdd_off(intel_dp
, true);
1250 intel_dp_complete_link_train(intel_dp
);
1251 ironlake_edp_backlight_on(intel_dp
);
1253 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1255 if (HAS_PCH_CPT(dev
))
1256 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
1260 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
1262 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1263 struct drm_device
*dev
= encoder
->dev
;
1264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1265 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1267 if (mode
!= DRM_MODE_DPMS_ON
) {
1268 ironlake_edp_backlight_off(intel_dp
);
1269 ironlake_edp_panel_off(intel_dp
);
1271 ironlake_edp_panel_vdd_on(intel_dp
);
1272 intel_dp_sink_dpms(intel_dp
, mode
);
1273 intel_dp_link_down(intel_dp
);
1274 ironlake_edp_panel_vdd_off(intel_dp
, false);
1276 if (is_cpu_edp(intel_dp
))
1277 ironlake_edp_pll_off(encoder
);
1279 if (is_cpu_edp(intel_dp
))
1280 ironlake_edp_pll_on(encoder
);
1282 ironlake_edp_panel_vdd_on(intel_dp
);
1283 intel_dp_sink_dpms(intel_dp
, mode
);
1284 if (!(dp_reg
& DP_PORT_EN
)) {
1285 intel_dp_start_link_train(intel_dp
);
1286 ironlake_edp_panel_on(intel_dp
);
1287 ironlake_edp_panel_vdd_off(intel_dp
, true);
1288 intel_dp_complete_link_train(intel_dp
);
1290 ironlake_edp_panel_vdd_off(intel_dp
, false);
1291 ironlake_edp_backlight_on(intel_dp
);
1293 intel_dp
->dpms_mode
= mode
;
1297 * Native read with retry for link status and receiver capability reads for
1298 * cases where the sink may still be asleep.
1301 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1302 uint8_t *recv
, int recv_bytes
)
1307 * Sinks are *supposed* to come up within 1ms from an off state,
1308 * but we're also supposed to retry 3 times per the spec.
1310 for (i
= 0; i
< 3; i
++) {
1311 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1313 if (ret
== recv_bytes
)
1322 * Fetch AUX CH registers 0x202 - 0x207 which contain
1323 * link status information
1326 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1328 return intel_dp_aux_native_read_retry(intel_dp
,
1331 DP_LINK_STATUS_SIZE
);
1335 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1338 return link_status
[r
- DP_LANE0_1_STATUS
];
1342 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1345 int s
= ((lane
& 1) ?
1346 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1347 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1348 uint8_t l
= adjust_request
[lane
>>1];
1350 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1354 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1357 int s
= ((lane
& 1) ?
1358 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1359 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1360 uint8_t l
= adjust_request
[lane
>>1];
1362 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1367 static char *voltage_names
[] = {
1368 "0.4V", "0.6V", "0.8V", "1.2V"
1370 static char *pre_emph_names
[] = {
1371 "0dB", "3.5dB", "6dB", "9.5dB"
1373 static char *link_train_names
[] = {
1374 "pattern 1", "pattern 2", "idle", "off"
1379 * These are source-specific values; current Intel hardware supports
1380 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1382 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1383 #define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200
1386 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
1388 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1389 case DP_TRAIN_VOLTAGE_SWING_400
:
1390 return DP_TRAIN_PRE_EMPHASIS_6
;
1391 case DP_TRAIN_VOLTAGE_SWING_600
:
1392 return DP_TRAIN_PRE_EMPHASIS_6
;
1393 case DP_TRAIN_VOLTAGE_SWING_800
:
1394 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1395 case DP_TRAIN_VOLTAGE_SWING_1200
:
1397 return DP_TRAIN_PRE_EMPHASIS_0
;
1402 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1404 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1408 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1411 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1412 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1413 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1421 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1422 voltage_max
= I830_DP_VOLTAGE_MAX_CPT
;
1424 voltage_max
= I830_DP_VOLTAGE_MAX
;
1425 if (v
>= voltage_max
)
1426 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1428 if (p
>= intel_dp_pre_emphasis_max(v
))
1429 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1431 for (lane
= 0; lane
< 4; lane
++)
1432 intel_dp
->train_set
[lane
] = v
| p
;
1436 intel_dp_signal_levels(uint8_t train_set
)
1438 uint32_t signal_levels
= 0;
1440 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1441 case DP_TRAIN_VOLTAGE_SWING_400
:
1443 signal_levels
|= DP_VOLTAGE_0_4
;
1445 case DP_TRAIN_VOLTAGE_SWING_600
:
1446 signal_levels
|= DP_VOLTAGE_0_6
;
1448 case DP_TRAIN_VOLTAGE_SWING_800
:
1449 signal_levels
|= DP_VOLTAGE_0_8
;
1451 case DP_TRAIN_VOLTAGE_SWING_1200
:
1452 signal_levels
|= DP_VOLTAGE_1_2
;
1455 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1456 case DP_TRAIN_PRE_EMPHASIS_0
:
1458 signal_levels
|= DP_PRE_EMPHASIS_0
;
1460 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1461 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1463 case DP_TRAIN_PRE_EMPHASIS_6
:
1464 signal_levels
|= DP_PRE_EMPHASIS_6
;
1466 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1467 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1470 return signal_levels
;
1473 /* Gen6's DP voltage swing and pre-emphasis control */
1475 intel_gen6_edp_signal_levels(uint8_t train_set
)
1477 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1478 DP_TRAIN_PRE_EMPHASIS_MASK
);
1479 switch (signal_levels
) {
1480 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1481 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1482 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1483 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1484 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1485 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1486 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1487 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1488 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1489 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1490 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1491 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1492 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1493 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1495 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1496 "0x%x\n", signal_levels
);
1497 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1502 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1505 int s
= (lane
& 1) * 4;
1506 uint8_t l
= link_status
[lane
>>1];
1508 return (l
>> s
) & 0xf;
1511 /* Check for clock recovery is done on all channels */
1513 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1516 uint8_t lane_status
;
1518 for (lane
= 0; lane
< lane_count
; lane
++) {
1519 lane_status
= intel_get_lane_status(link_status
, lane
);
1520 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1526 /* Check to see if channel eq is done on all channels */
1527 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1528 DP_LANE_CHANNEL_EQ_DONE|\
1529 DP_LANE_SYMBOL_LOCKED)
1531 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1534 uint8_t lane_status
;
1537 lane_align
= intel_dp_link_status(link_status
,
1538 DP_LANE_ALIGN_STATUS_UPDATED
);
1539 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1541 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1542 lane_status
= intel_get_lane_status(link_status
, lane
);
1543 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1550 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1551 uint32_t dp_reg_value
,
1552 uint8_t dp_train_pat
)
1554 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1558 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1559 POSTING_READ(intel_dp
->output_reg
);
1561 intel_dp_aux_native_write_1(intel_dp
,
1562 DP_TRAINING_PATTERN_SET
,
1565 ret
= intel_dp_aux_native_write(intel_dp
,
1566 DP_TRAINING_LANE0_SET
,
1567 intel_dp
->train_set
, 4);
1574 /* Enable corresponding port and start training pattern 1 */
1576 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1578 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1580 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1583 bool clock_recovery
= false;
1584 int voltage_tries
, loop_tries
;
1586 uint32_t DP
= intel_dp
->DP
;
1589 * On CPT we have to enable the port in training pattern 1, which
1590 * will happen below in intel_dp_set_link_train. Otherwise, enable
1591 * the port and wait for it to become active.
1593 if (!HAS_PCH_CPT(dev
)) {
1594 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
1595 POSTING_READ(intel_dp
->output_reg
);
1596 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1599 /* Write the link configuration data */
1600 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1601 intel_dp
->link_configuration
,
1602 DP_LINK_CONFIGURATION_SIZE
);
1605 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1606 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1608 DP
&= ~DP_LINK_TRAIN_MASK
;
1609 memset(intel_dp
->train_set
, 0, 4);
1613 clock_recovery
= false;
1615 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1616 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1617 uint32_t signal_levels
;
1619 if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1620 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1621 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1623 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1624 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels
);
1625 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1628 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1629 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1631 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1633 if (!intel_dp_set_link_train(intel_dp
, reg
,
1634 DP_TRAINING_PATTERN_1
|
1635 DP_LINK_SCRAMBLING_DISABLE
))
1637 /* Set training pattern 1 */
1640 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1641 DRM_ERROR("failed to get link status\n");
1645 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1646 DRM_DEBUG_KMS("clock recovery OK\n");
1647 clock_recovery
= true;
1651 /* Check to see if we've tried the max voltage */
1652 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1653 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1655 if (i
== intel_dp
->lane_count
) {
1657 if (loop_tries
== 5) {
1658 DRM_DEBUG_KMS("too many full retries, give up\n");
1661 memset(intel_dp
->train_set
, 0, 4);
1666 /* Check to see if we've tried the same voltage 5 times */
1667 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1669 if (voltage_tries
== 5) {
1670 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1675 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1677 /* Compute new intel_dp->train_set as requested by target */
1678 intel_get_adjust_train(intel_dp
, link_status
);
1685 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1687 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1689 bool channel_eq
= false;
1690 int tries
, cr_tries
;
1692 uint32_t DP
= intel_dp
->DP
;
1694 /* channel equalization */
1699 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1700 uint32_t signal_levels
;
1701 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1704 DRM_ERROR("failed to train DP, aborting\n");
1705 intel_dp_link_down(intel_dp
);
1709 if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1710 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1711 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1713 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1714 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1717 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1718 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1720 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1722 /* channel eq pattern */
1723 if (!intel_dp_set_link_train(intel_dp
, reg
,
1724 DP_TRAINING_PATTERN_2
|
1725 DP_LINK_SCRAMBLING_DISABLE
))
1729 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1732 /* Make sure clock is still ok */
1733 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1734 intel_dp_start_link_train(intel_dp
);
1739 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1744 /* Try 5 times, then try clock recovery if that fails */
1746 intel_dp_link_down(intel_dp
);
1747 intel_dp_start_link_train(intel_dp
);
1753 /* Compute new intel_dp->train_set as requested by target */
1754 intel_get_adjust_train(intel_dp
, link_status
);
1758 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1759 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1761 reg
= DP
| DP_LINK_TRAIN_OFF
;
1763 I915_WRITE(intel_dp
->output_reg
, reg
);
1764 POSTING_READ(intel_dp
->output_reg
);
1765 intel_dp_aux_native_write_1(intel_dp
,
1766 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1770 intel_dp_link_down(struct intel_dp
*intel_dp
)
1772 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1774 uint32_t DP
= intel_dp
->DP
;
1776 if ((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1779 DRM_DEBUG_KMS("\n");
1781 if (is_edp(intel_dp
)) {
1782 DP
&= ~DP_PLL_ENABLE
;
1783 I915_WRITE(intel_dp
->output_reg
, DP
);
1784 POSTING_READ(intel_dp
->output_reg
);
1788 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
)) {
1789 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1790 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1792 DP
&= ~DP_LINK_TRAIN_MASK
;
1793 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1795 POSTING_READ(intel_dp
->output_reg
);
1799 if (is_edp(intel_dp
)) {
1800 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1801 DP
|= DP_LINK_TRAIN_OFF_CPT
;
1803 DP
|= DP_LINK_TRAIN_OFF
;
1806 if (!HAS_PCH_CPT(dev
) &&
1807 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1808 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1810 /* Hardware workaround: leaving our transcoder select
1811 * set to transcoder B while it's off will prevent the
1812 * corresponding HDMI output on transcoder A.
1814 * Combine this with another hardware workaround:
1815 * transcoder select bit can only be cleared while the
1818 DP
&= ~DP_PIPEB_SELECT
;
1819 I915_WRITE(intel_dp
->output_reg
, DP
);
1821 /* Changes to enable or select take place the vblank
1822 * after being written.
1825 /* We can arrive here never having been attached
1826 * to a CRTC, for instance, due to inheriting
1827 * random state from the BIOS.
1829 * If the pipe is not running, play safe and
1830 * wait for the clocks to stabilise before
1833 POSTING_READ(intel_dp
->output_reg
);
1836 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1839 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1840 POSTING_READ(intel_dp
->output_reg
);
1841 msleep(intel_dp
->panel_power_down_delay
);
1845 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
1847 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
1848 sizeof(intel_dp
->dpcd
)) &&
1849 (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)) {
1857 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
1861 ret
= intel_dp_aux_native_read_retry(intel_dp
,
1862 DP_DEVICE_SERVICE_IRQ_VECTOR
,
1863 sink_irq_vector
, 1);
1871 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
1873 /* NAK by default */
1874 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
1878 * According to DP spec
1881 * 2. Configure link according to Receiver Capabilities
1882 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1883 * 4. Check link status on receipt of hot-plug interrupt
1887 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
1890 u8 link_status
[DP_LINK_STATUS_SIZE
];
1892 if (intel_dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
1895 if (!intel_dp
->base
.base
.crtc
)
1898 /* Try to read receiver status if the link appears to be up */
1899 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1900 intel_dp_link_down(intel_dp
);
1904 /* Now read the DPCD to see if it's actually running */
1905 if (!intel_dp_get_dpcd(intel_dp
)) {
1906 intel_dp_link_down(intel_dp
);
1910 /* Try to read the source of the interrupt */
1911 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
1912 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
1913 /* Clear interrupt source */
1914 intel_dp_aux_native_write_1(intel_dp
,
1915 DP_DEVICE_SERVICE_IRQ_VECTOR
,
1918 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
1919 intel_dp_handle_test_request(intel_dp
);
1920 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
1921 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1924 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
1925 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1926 drm_get_encoder_name(&intel_dp
->base
.base
));
1927 intel_dp_start_link_train(intel_dp
);
1928 intel_dp_complete_link_train(intel_dp
);
1932 static enum drm_connector_status
1933 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
1935 if (intel_dp_get_dpcd(intel_dp
))
1936 return connector_status_connected
;
1937 return connector_status_disconnected
;
1940 static enum drm_connector_status
1941 ironlake_dp_detect(struct intel_dp
*intel_dp
)
1943 enum drm_connector_status status
;
1945 /* Can't disconnect eDP, but you can close the lid... */
1946 if (is_edp(intel_dp
)) {
1947 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
1948 if (status
== connector_status_unknown
)
1949 status
= connector_status_connected
;
1953 return intel_dp_detect_dpcd(intel_dp
);
1956 static enum drm_connector_status
1957 g4x_dp_detect(struct intel_dp
*intel_dp
)
1959 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1963 switch (intel_dp
->output_reg
) {
1965 bit
= DPB_HOTPLUG_INT_STATUS
;
1968 bit
= DPC_HOTPLUG_INT_STATUS
;
1971 bit
= DPD_HOTPLUG_INT_STATUS
;
1974 return connector_status_unknown
;
1977 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1979 if ((temp
& bit
) == 0)
1980 return connector_status_disconnected
;
1982 return intel_dp_detect_dpcd(intel_dp
);
1985 static struct edid
*
1986 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
1988 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1991 ironlake_edp_panel_vdd_on(intel_dp
);
1992 edid
= drm_get_edid(connector
, adapter
);
1993 ironlake_edp_panel_vdd_off(intel_dp
, false);
1998 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2000 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2003 ironlake_edp_panel_vdd_on(intel_dp
);
2004 ret
= intel_ddc_get_modes(connector
, adapter
);
2005 ironlake_edp_panel_vdd_off(intel_dp
, false);
2011 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2013 * \return true if DP port is connected.
2014 * \return false if DP port is disconnected.
2016 static enum drm_connector_status
2017 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2019 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2020 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2021 enum drm_connector_status status
;
2022 struct edid
*edid
= NULL
;
2024 intel_dp
->has_audio
= false;
2026 if (HAS_PCH_SPLIT(dev
))
2027 status
= ironlake_dp_detect(intel_dp
);
2029 status
= g4x_dp_detect(intel_dp
);
2031 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2032 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2033 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2034 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2036 if (status
!= connector_status_connected
)
2039 if (intel_dp
->force_audio
) {
2040 intel_dp
->has_audio
= intel_dp
->force_audio
> 0;
2042 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2044 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2045 connector
->display_info
.raw_edid
= NULL
;
2050 return connector_status_connected
;
2053 static int intel_dp_get_modes(struct drm_connector
*connector
)
2055 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2056 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2060 /* We should parse the EDID data and find out if it has an audio sink
2063 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2065 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2066 struct drm_display_mode
*newmode
;
2067 list_for_each_entry(newmode
, &connector
->probed_modes
,
2069 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2070 intel_dp
->panel_fixed_mode
=
2071 drm_mode_duplicate(dev
, newmode
);
2079 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2080 if (is_edp(intel_dp
)) {
2081 /* initialize panel mode from VBT if available for eDP */
2082 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2083 intel_dp
->panel_fixed_mode
=
2084 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2085 if (intel_dp
->panel_fixed_mode
) {
2086 intel_dp
->panel_fixed_mode
->type
|=
2087 DRM_MODE_TYPE_PREFERRED
;
2090 if (intel_dp
->panel_fixed_mode
) {
2091 struct drm_display_mode
*mode
;
2092 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2093 drm_mode_probed_add(connector
, mode
);
2101 intel_dp_detect_audio(struct drm_connector
*connector
)
2103 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2105 bool has_audio
= false;
2107 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2109 has_audio
= drm_detect_monitor_audio(edid
);
2111 connector
->display_info
.raw_edid
= NULL
;
2119 intel_dp_set_property(struct drm_connector
*connector
,
2120 struct drm_property
*property
,
2123 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2124 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2127 ret
= drm_connector_property_set_value(connector
, property
, val
);
2131 if (property
== dev_priv
->force_audio_property
) {
2135 if (i
== intel_dp
->force_audio
)
2138 intel_dp
->force_audio
= i
;
2141 has_audio
= intel_dp_detect_audio(connector
);
2145 if (has_audio
== intel_dp
->has_audio
)
2148 intel_dp
->has_audio
= has_audio
;
2152 if (property
== dev_priv
->broadcast_rgb_property
) {
2153 if (val
== !!intel_dp
->color_range
)
2156 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2163 if (intel_dp
->base
.base
.crtc
) {
2164 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2165 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
2174 intel_dp_destroy(struct drm_connector
*connector
)
2176 struct drm_device
*dev
= connector
->dev
;
2178 if (intel_dpd_is_edp(dev
))
2179 intel_panel_destroy_backlight(dev
);
2181 drm_sysfs_connector_remove(connector
);
2182 drm_connector_cleanup(connector
);
2186 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2188 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2190 i2c_del_adapter(&intel_dp
->adapter
);
2191 drm_encoder_cleanup(encoder
);
2192 if (is_edp(intel_dp
)) {
2193 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2194 ironlake_panel_vdd_off_sync(intel_dp
);
2199 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2200 .dpms
= intel_dp_dpms
,
2201 .mode_fixup
= intel_dp_mode_fixup
,
2202 .prepare
= intel_dp_prepare
,
2203 .mode_set
= intel_dp_mode_set
,
2204 .commit
= intel_dp_commit
,
2207 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2208 .dpms
= drm_helper_connector_dpms
,
2209 .detect
= intel_dp_detect
,
2210 .fill_modes
= drm_helper_probe_single_connector_modes
,
2211 .set_property
= intel_dp_set_property
,
2212 .destroy
= intel_dp_destroy
,
2215 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2216 .get_modes
= intel_dp_get_modes
,
2217 .mode_valid
= intel_dp_mode_valid
,
2218 .best_encoder
= intel_best_encoder
,
2221 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2222 .destroy
= intel_dp_encoder_destroy
,
2226 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2228 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2230 intel_dp_check_link_status(intel_dp
);
2233 /* Return which DP Port should be selected for Transcoder DP control */
2235 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2237 struct drm_device
*dev
= crtc
->dev
;
2238 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2239 struct drm_encoder
*encoder
;
2241 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
2242 struct intel_dp
*intel_dp
;
2244 if (encoder
->crtc
!= crtc
)
2247 intel_dp
= enc_to_intel_dp(encoder
);
2248 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2249 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2250 return intel_dp
->output_reg
;
2256 /* check the VBT to see whether the eDP is on DP-D port */
2257 bool intel_dpd_is_edp(struct drm_device
*dev
)
2259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2260 struct child_device_config
*p_child
;
2263 if (!dev_priv
->child_dev_num
)
2266 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2267 p_child
= dev_priv
->child_dev
+ i
;
2269 if (p_child
->dvo_port
== PORT_IDPD
&&
2270 p_child
->device_type
== DEVICE_TYPE_eDP
)
2277 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2279 intel_attach_force_audio_property(connector
);
2280 intel_attach_broadcast_rgb_property(connector
);
2284 intel_dp_init(struct drm_device
*dev
, int output_reg
)
2286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2287 struct drm_connector
*connector
;
2288 struct intel_dp
*intel_dp
;
2289 struct intel_encoder
*intel_encoder
;
2290 struct intel_connector
*intel_connector
;
2291 const char *name
= NULL
;
2294 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2298 intel_dp
->output_reg
= output_reg
;
2299 intel_dp
->dpms_mode
= -1;
2301 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2302 if (!intel_connector
) {
2306 intel_encoder
= &intel_dp
->base
;
2308 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2309 if (intel_dpd_is_edp(dev
))
2310 intel_dp
->is_pch_edp
= true;
2312 if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2313 type
= DRM_MODE_CONNECTOR_eDP
;
2314 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2316 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2317 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2320 connector
= &intel_connector
->base
;
2321 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2322 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2324 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2326 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
2327 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
2328 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
2329 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
2330 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
2331 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
2333 if (is_edp(intel_dp
)) {
2334 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
2335 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2336 ironlake_panel_vdd_work
);
2339 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2340 connector
->interlace_allowed
= true;
2341 connector
->doublescan_allowed
= 0;
2343 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2344 DRM_MODE_ENCODER_TMDS
);
2345 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2347 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2348 drm_sysfs_connector_add(connector
);
2350 /* Set up the DDC bus. */
2351 switch (output_reg
) {
2357 dev_priv
->hotplug_supported_mask
|=
2358 HDMIB_HOTPLUG_INT_STATUS
;
2363 dev_priv
->hotplug_supported_mask
|=
2364 HDMIC_HOTPLUG_INT_STATUS
;
2369 dev_priv
->hotplug_supported_mask
|=
2370 HDMID_HOTPLUG_INT_STATUS
;
2375 /* Cache some DPCD data in the eDP case */
2376 if (is_edp(intel_dp
)) {
2378 struct edp_power_seq cur
, vbt
;
2379 u32 pp_on
, pp_off
, pp_div
;
2381 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2382 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2383 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2385 /* Pull timing values out of registers */
2386 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2387 PANEL_POWER_UP_DELAY_SHIFT
;
2389 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2390 PANEL_LIGHT_ON_DELAY_SHIFT
;
2392 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2393 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2395 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2396 PANEL_POWER_DOWN_DELAY_SHIFT
;
2398 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2399 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2401 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2402 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2404 vbt
= dev_priv
->edp
.pps
;
2406 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2407 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2409 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2411 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2412 intel_dp
->backlight_on_delay
= get_delay(t8
);
2413 intel_dp
->backlight_off_delay
= get_delay(t9
);
2414 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2415 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2417 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2418 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2419 intel_dp
->panel_power_cycle_delay
);
2421 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2422 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2424 ironlake_edp_panel_vdd_on(intel_dp
);
2425 ret
= intel_dp_get_dpcd(intel_dp
);
2426 ironlake_edp_panel_vdd_off(intel_dp
, false);
2429 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2430 dev_priv
->no_aux_handshake
=
2431 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2432 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2434 /* if this fails, presume the device is a ghost */
2435 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2436 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2437 intel_dp_destroy(&intel_connector
->base
);
2442 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2444 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2446 if (is_edp(intel_dp
)) {
2447 dev_priv
->int_edp_connector
= connector
;
2448 intel_panel_setup_backlight(dev
);
2451 intel_dp_add_properties(intel_dp
, connector
);
2453 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2454 * 0xd. Failure to do so will result in spurious interrupts being
2455 * generated on the port when a cable is not attached.
2457 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2458 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2459 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);