2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
29 #include "dmaengine.h"
30 #define PL330_MAX_CHAN 8
31 #define PL330_MAX_IRQS 32
32 #define PL330_MAX_PERI 32
34 enum pl330_srccachectrl
{
35 SCCTRL0
, /* Noncacheable and nonbufferable */
36 SCCTRL1
, /* Bufferable only */
37 SCCTRL2
, /* Cacheable, but do not allocate */
38 SCCTRL3
, /* Cacheable and bufferable, but do not allocate */
41 SCCTRL6
, /* Cacheable write-through, allocate on reads only */
42 SCCTRL7
, /* Cacheable write-back, allocate on reads only */
45 enum pl330_dstcachectrl
{
46 DCCTRL0
, /* Noncacheable and nonbufferable */
47 DCCTRL1
, /* Bufferable only */
48 DCCTRL2
, /* Cacheable, but do not allocate */
49 DCCTRL3
, /* Cacheable and bufferable, but do not allocate */
50 DINVALID1
, /* AWCACHE = 0x1000 */
52 DCCTRL6
, /* Cacheable write-through, allocate on writes only */
53 DCCTRL7
, /* Cacheable write-back, allocate on writes only */
71 /* Register and Bit field Definitions */
73 #define DS_ST_STOP 0x0
74 #define DS_ST_EXEC 0x1
75 #define DS_ST_CMISS 0x2
76 #define DS_ST_UPDTPC 0x3
78 #define DS_ST_ATBRR 0x5
79 #define DS_ST_QBUSY 0x6
81 #define DS_ST_KILL 0x8
82 #define DS_ST_CMPLT 0x9
83 #define DS_ST_FLTCMP 0xe
84 #define DS_ST_FAULT 0xf
89 #define INTSTATUS 0x28
96 #define FTC(n) (_FTC + (n)*0x4)
99 #define CS(n) (_CS + (n)*0x8)
100 #define CS_CNS (1 << 21)
103 #define CPC(n) (_CPC + (n)*0x8)
106 #define SA(n) (_SA + (n)*0x20)
109 #define DA(n) (_DA + (n)*0x20)
112 #define CC(n) (_CC + (n)*0x20)
114 #define CC_SRCINC (1 << 0)
115 #define CC_DSTINC (1 << 14)
116 #define CC_SRCPRI (1 << 8)
117 #define CC_DSTPRI (1 << 22)
118 #define CC_SRCNS (1 << 9)
119 #define CC_DSTNS (1 << 23)
120 #define CC_SRCIA (1 << 10)
121 #define CC_DSTIA (1 << 24)
122 #define CC_SRCBRSTLEN_SHFT 4
123 #define CC_DSTBRSTLEN_SHFT 18
124 #define CC_SRCBRSTSIZE_SHFT 1
125 #define CC_DSTBRSTSIZE_SHFT 15
126 #define CC_SRCCCTRL_SHFT 11
127 #define CC_SRCCCTRL_MASK 0x7
128 #define CC_DSTCCTRL_SHFT 25
129 #define CC_DRCCCTRL_MASK 0x7
130 #define CC_SWAP_SHFT 28
133 #define LC0(n) (_LC0 + (n)*0x20)
136 #define LC1(n) (_LC1 + (n)*0x20)
138 #define DBGSTATUS 0xd00
139 #define DBG_BUSY (1 << 0)
142 #define DBGINST0 0xd08
143 #define DBGINST1 0xd0c
152 #define PERIPH_ID 0xfe0
153 #define PERIPH_REV_SHIFT 20
154 #define PERIPH_REV_MASK 0xf
155 #define PERIPH_REV_R0P0 0
156 #define PERIPH_REV_R1P0 1
157 #define PERIPH_REV_R1P1 2
158 #define PCELL_ID 0xff0
160 #define CR0_PERIPH_REQ_SET (1 << 0)
161 #define CR0_BOOT_EN_SET (1 << 1)
162 #define CR0_BOOT_MAN_NS (1 << 2)
163 #define CR0_NUM_CHANS_SHIFT 4
164 #define CR0_NUM_CHANS_MASK 0x7
165 #define CR0_NUM_PERIPH_SHIFT 12
166 #define CR0_NUM_PERIPH_MASK 0x1f
167 #define CR0_NUM_EVENTS_SHIFT 17
168 #define CR0_NUM_EVENTS_MASK 0x1f
170 #define CR1_ICACHE_LEN_SHIFT 0
171 #define CR1_ICACHE_LEN_MASK 0x7
172 #define CR1_NUM_ICACHELINES_SHIFT 4
173 #define CR1_NUM_ICACHELINES_MASK 0xf
175 #define CRD_DATA_WIDTH_SHIFT 0
176 #define CRD_DATA_WIDTH_MASK 0x7
177 #define CRD_WR_CAP_SHIFT 4
178 #define CRD_WR_CAP_MASK 0x7
179 #define CRD_WR_Q_DEP_SHIFT 8
180 #define CRD_WR_Q_DEP_MASK 0xf
181 #define CRD_RD_CAP_SHIFT 12
182 #define CRD_RD_CAP_MASK 0x7
183 #define CRD_RD_Q_DEP_SHIFT 16
184 #define CRD_RD_Q_DEP_MASK 0xf
185 #define CRD_DATA_BUFF_SHIFT 20
186 #define CRD_DATA_BUFF_MASK 0x3ff
189 #define DESIGNER 0x41
191 #define INTEG_CFG 0x0
192 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
194 #define PCELL_ID_VAL 0xb105f00d
196 #define PL330_STATE_STOPPED (1 << 0)
197 #define PL330_STATE_EXECUTING (1 << 1)
198 #define PL330_STATE_WFE (1 << 2)
199 #define PL330_STATE_FAULTING (1 << 3)
200 #define PL330_STATE_COMPLETING (1 << 4)
201 #define PL330_STATE_WFP (1 << 5)
202 #define PL330_STATE_KILLING (1 << 6)
203 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
204 #define PL330_STATE_CACHEMISS (1 << 8)
205 #define PL330_STATE_UPDTPC (1 << 9)
206 #define PL330_STATE_ATBARRIER (1 << 10)
207 #define PL330_STATE_QUEUEBUSY (1 << 11)
208 #define PL330_STATE_INVALID (1 << 15)
210 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
211 | PL330_STATE_WFE | PL330_STATE_FAULTING)
213 #define CMD_DMAADDH 0x54
214 #define CMD_DMAEND 0x00
215 #define CMD_DMAFLUSHP 0x35
216 #define CMD_DMAGO 0xa0
217 #define CMD_DMALD 0x04
218 #define CMD_DMALDP 0x25
219 #define CMD_DMALP 0x20
220 #define CMD_DMALPEND 0x28
221 #define CMD_DMAKILL 0x01
222 #define CMD_DMAMOV 0xbc
223 #define CMD_DMANOP 0x18
224 #define CMD_DMARMB 0x12
225 #define CMD_DMASEV 0x34
226 #define CMD_DMAST 0x08
227 #define CMD_DMASTP 0x29
228 #define CMD_DMASTZ 0x0c
229 #define CMD_DMAWFE 0x36
230 #define CMD_DMAWFP 0x30
231 #define CMD_DMAWMB 0x13
235 #define SZ_DMAFLUSHP 2
239 #define SZ_DMALPEND 2
253 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
254 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
256 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
257 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
260 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
261 * at 1byte/burst for P<->M and M<->M respectively.
262 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
263 * should be enough for P<->M and M<->M respectively.
265 #define MCODE_BUFF_PER_REQ 256
267 /* If the _pl330_req is available to the client */
268 #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
270 /* Use this _only_ to wait on transient states */
271 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
273 #ifdef PL330_DEBUG_MCGEN
274 static unsigned cmd_line
;
275 #define PL330_DBGCMD_DUMP(off, x...) do { \
276 printk("%x:", cmd_line); \
280 #define PL330_DBGMC_START(addr) (cmd_line = addr)
282 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
283 #define PL330_DBGMC_START(addr) do {} while (0)
286 /* The number of default descriptors */
288 #define NR_DEFAULT_DESC 16
290 /* Populated by the PL330 core driver for DMA API driver's info */
291 struct pl330_config
{
294 #define DMAC_MODE_NS (1 << 0)
296 unsigned int data_bus_width
:10; /* In number of bits */
297 unsigned int data_buf_dep
:10;
298 unsigned int num_chan
:4;
299 unsigned int num_peri
:6;
301 unsigned int num_events
:6;
305 /* Handle to the DMAC provided to the PL330 core */
309 /* Size of MicroCode buffers for each channel. */
311 /* ioremap'ed address of PL330 registers. */
313 /* Client can freely use it. */
315 /* PL330 core data, Client must not touch it. */
317 /* Populated by the PL330 core driver during pl330_add */
318 struct pl330_config pcfg
;
320 * If the DMAC has some reset mechanism, then the
321 * client may want to provide pointer to the method.
323 void (*dmac_reset
)(struct pl330_info
*pi
);
327 * Request Configuration.
328 * The PL330 core does not modify this and uses the last
329 * working configuration if the request doesn't provide any.
331 * The Client may want to provide this info only for the
332 * first request and a request with new settings.
334 struct pl330_reqcfg
{
335 /* Address Incrementing */
340 * For now, the SRC & DST protection levels
341 * and burst size/length are assumed same.
347 unsigned brst_size
:3; /* in power of 2 */
349 enum pl330_dstcachectrl dcctl
;
350 enum pl330_srccachectrl scctl
;
351 enum pl330_byteswap swap
;
352 struct pl330_config
*pcfg
;
356 * One cycle of DMAC operation.
357 * There may be more than one xfer in a request.
365 * Pointer to next xfer in the list.
366 * The last xfer in the req must point to NULL.
368 struct pl330_xfer
*next
;
371 /* The xfer callbacks are made with one of these arguments. */
373 /* The all xfers in the request were success. */
375 /* If req aborted due to global error. */
377 /* If req failed due to problem with Channel. */
381 /* A request defining Scatter-Gather List ending with NULL xfer. */
383 enum pl330_reqtype rqtype
;
384 /* Index of peripheral for the xfer. */
386 /* Unique token for this xfer, set by the client. */
388 /* Callback to be called after xfer. */
389 void (*xfer_cb
)(void *token
, enum pl330_op_err err
);
390 /* If NULL, req will be done at last set parameters. */
391 struct pl330_reqcfg
*cfg
;
392 /* Pointer to first xfer in the request. */
393 struct pl330_xfer
*x
;
394 /* Hook to attach to DMAC's list of reqs with due callback */
395 struct list_head rqd
;
399 * To know the status of the channel and DMAC, the client
400 * provides a pointer to this structure. The PL330 core
401 * fills it with current information.
403 struct pl330_chanstatus
{
405 * If the DMAC engine halted due to some error,
406 * the client should remove-add DMAC.
410 * If channel is halted due to some error,
411 * the client should ABORT/FLUSH and START the channel.
414 /* Location of last load */
416 /* Location of last store */
419 * Pointer to the currently active req, NULL if channel is
420 * inactive, even though the requests may be present.
422 struct pl330_req
*top_req
;
423 /* Pointer to req waiting second in the queue if any. */
424 struct pl330_req
*wait_req
;
428 /* Start the channel */
430 /* Abort the active xfer */
432 /* Stop xfer and flush queue */
439 struct pl330_xfer
*x
;
462 /* Number of bytes taken to setup MC for the req */
467 /* ToBeDone for tasklet */
475 struct pl330_thread
{
478 /* If the channel is not yet acquired by any client */
481 struct pl330_dmac
*dmac
;
482 /* Only two at a time */
483 struct _pl330_req req
[2];
484 /* Index of the last enqueued request */
486 /* Index of the last submitted request or -1 if the DMA is stopped */
490 enum pl330_dmac_state
{
499 /* Holds list of reqs with due callbacks */
500 struct list_head req_done
;
501 /* Pointer to platform specific stuff */
502 struct pl330_info
*pinfo
;
503 /* Maximum possible events/irqs */
505 /* BUS address of MicroCode buffer */
507 /* CPU address of MicroCode buffer */
509 /* List of all Channel threads */
510 struct pl330_thread
*channels
;
511 /* Pointer to the MANAGER thread */
512 struct pl330_thread
*manager
;
513 /* To handle bad news in interrupt */
514 struct tasklet_struct tasks
;
515 struct _pl330_tbd dmac_tbd
;
516 /* State of DMAC operation */
517 enum pl330_dmac_state state
;
521 /* In the DMAC pool */
524 * Allocated to some channel during prep_xxx
525 * Also may be sitting on the work_list.
529 * Sitting on the work_list and already submitted
530 * to the PL330 core. Not more than two descriptors
531 * of a channel can be BUSY at any time.
535 * Sitting on the channel work_list but xfer done
541 struct dma_pl330_chan
{
542 /* Schedule desc completion */
543 struct tasklet_struct task
;
545 /* DMA-Engine Channel */
546 struct dma_chan chan
;
548 /* List of to be xfered descriptors */
549 struct list_head work_list
;
551 /* Pointer to the DMAC that manages this channel,
552 * NULL if the channel is available to be acquired.
553 * As the parent, this DMAC also provides descriptors
556 struct dma_pl330_dmac
*dmac
;
558 /* To protect channel manipulation */
561 /* Token of a hardware channel thread of PL330 DMAC
562 * NULL if the channel is available to be acquired.
566 /* For D-to-M and M-to-D channels */
567 int burst_sz
; /* the peripheral fifo width */
568 int burst_len
; /* the number of burst */
569 dma_addr_t fifo_addr
;
571 /* for cyclic capability */
575 struct dma_pl330_dmac
{
576 struct pl330_info pif
;
578 /* DMA-Engine Device */
579 struct dma_device ddma
;
581 /* Pool of descriptors available for the DMAC's channels */
582 struct list_head desc_pool
;
583 /* To protect desc_pool manipulation */
584 spinlock_t pool_lock
;
586 /* Peripheral channels connected to this DMAC */
587 struct dma_pl330_chan
*peripherals
; /* keep at end */
590 struct dma_pl330_desc
{
591 /* To attach to a queue as child */
592 struct list_head node
;
594 /* Descriptor for the DMA Engine API */
595 struct dma_async_tx_descriptor txd
;
597 /* Xfer for PL330 core */
598 struct pl330_xfer px
;
600 struct pl330_reqcfg rqcfg
;
601 struct pl330_req req
;
603 enum desc_status status
;
605 /* The channel which currently holds this desc */
606 struct dma_pl330_chan
*pchan
;
609 static inline void _callback(struct pl330_req
*r
, enum pl330_op_err err
)
612 r
->xfer_cb(r
->token
, err
);
615 static inline bool _queue_empty(struct pl330_thread
*thrd
)
617 return (IS_FREE(&thrd
->req
[0]) && IS_FREE(&thrd
->req
[1]))
621 static inline bool _queue_full(struct pl330_thread
*thrd
)
623 return (IS_FREE(&thrd
->req
[0]) || IS_FREE(&thrd
->req
[1]))
627 static inline bool is_manager(struct pl330_thread
*thrd
)
629 struct pl330_dmac
*pl330
= thrd
->dmac
;
631 /* MANAGER is indexed at the end */
632 if (thrd
->id
== pl330
->pinfo
->pcfg
.num_chan
)
638 /* If manager of the thread is in Non-Secure mode */
639 static inline bool _manager_ns(struct pl330_thread
*thrd
)
641 struct pl330_dmac
*pl330
= thrd
->dmac
;
643 return (pl330
->pinfo
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
646 static inline u32
get_id(struct pl330_info
*pi
, u32 off
)
648 void __iomem
*regs
= pi
->base
;
651 id
|= (readb(regs
+ off
+ 0x0) << 0);
652 id
|= (readb(regs
+ off
+ 0x4) << 8);
653 id
|= (readb(regs
+ off
+ 0x8) << 16);
654 id
|= (readb(regs
+ off
+ 0xc) << 24);
659 static inline u32
get_revision(u32 periph_id
)
661 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
664 static inline u32
_emit_ADDH(unsigned dry_run
, u8 buf
[],
665 enum pl330_dst da
, u16 val
)
670 buf
[0] = CMD_DMAADDH
;
672 *((u16
*)&buf
[1]) = val
;
674 PL330_DBGCMD_DUMP(SZ_DMAADDH
, "\tDMAADDH %s %u\n",
675 da
== 1 ? "DA" : "SA", val
);
680 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
687 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
692 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
697 buf
[0] = CMD_DMAFLUSHP
;
703 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
708 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
716 buf
[0] |= (0 << 1) | (1 << 0);
717 else if (cond
== BURST
)
718 buf
[0] |= (1 << 1) | (1 << 0);
720 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
721 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
726 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
727 enum pl330_cond cond
, u8 peri
)
741 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
742 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
747 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
748 unsigned loop
, u8 cnt
)
758 cnt
--; /* DMAC increments by 1 internally */
761 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
767 enum pl330_cond cond
;
773 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
774 const struct _arg_LPEND
*arg
)
776 enum pl330_cond cond
= arg
->cond
;
777 bool forever
= arg
->forever
;
778 unsigned loop
= arg
->loop
;
779 u8 bjump
= arg
->bjump
;
784 buf
[0] = CMD_DMALPEND
;
793 buf
[0] |= (0 << 1) | (1 << 0);
794 else if (cond
== BURST
)
795 buf
[0] |= (1 << 1) | (1 << 0);
799 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
800 forever
? "FE" : "END",
801 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
808 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
813 buf
[0] = CMD_DMAKILL
;
818 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
819 enum dmamov_dst dst
, u32 val
)
826 *((u32
*)&buf
[2]) = val
;
828 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
829 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
834 static inline u32
_emit_NOP(unsigned dry_run
, u8 buf
[])
841 PL330_DBGCMD_DUMP(SZ_DMANOP
, "\tDMANOP\n");
846 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
853 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
858 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
869 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
874 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
882 buf
[0] |= (0 << 1) | (1 << 0);
883 else if (cond
== BURST
)
884 buf
[0] |= (1 << 1) | (1 << 0);
886 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
887 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
892 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
893 enum pl330_cond cond
, u8 peri
)
907 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
908 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
913 static inline u32
_emit_STZ(unsigned dry_run
, u8 buf
[])
920 PL330_DBGCMD_DUMP(SZ_DMASTZ
, "\tDMASTZ\n");
925 static inline u32
_emit_WFE(unsigned dry_run
, u8 buf
[], u8 ev
,
940 PL330_DBGCMD_DUMP(SZ_DMAWFE
, "\tDMAWFE %u%s\n",
941 ev
>> 3, invalidate
? ", I" : "");
946 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
947 enum pl330_cond cond
, u8 peri
)
955 buf
[0] |= (0 << 1) | (0 << 0);
956 else if (cond
== BURST
)
957 buf
[0] |= (1 << 1) | (0 << 0);
959 buf
[0] |= (0 << 1) | (1 << 0);
965 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
966 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
971 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
978 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
989 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
990 const struct _arg_GO
*arg
)
993 u32 addr
= arg
->addr
;
994 unsigned ns
= arg
->ns
;
1000 buf
[0] |= (ns
<< 1);
1002 buf
[1] = chan
& 0x7;
1004 *((u32
*)&buf
[2]) = addr
;
1009 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
1011 /* Returns Time-Out */
1012 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
1014 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1015 unsigned long loops
= msecs_to_loops(5);
1018 /* Until Manager is Idle */
1019 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
1031 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
1032 u8 insn
[], bool as_manager
)
1034 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1037 val
= (insn
[0] << 16) | (insn
[1] << 24);
1040 val
|= (thrd
->id
<< 8); /* Channel Number */
1042 writel(val
, regs
+ DBGINST0
);
1044 val
= *((u32
*)&insn
[2]);
1045 writel(val
, regs
+ DBGINST1
);
1047 /* If timed out due to halted state-machine */
1048 if (_until_dmac_idle(thrd
)) {
1049 dev_err(thrd
->dmac
->pinfo
->dev
, "DMAC halted!\n");
1054 writel(0, regs
+ DBGCMD
);
1058 * Mark a _pl330_req as free.
1059 * We do it by writing DMAEND as the first instruction
1060 * because no valid request is going to have DMAEND as
1061 * its first instruction to execute.
1063 static void mark_free(struct pl330_thread
*thrd
, int idx
)
1065 struct _pl330_req
*req
= &thrd
->req
[idx
];
1067 _emit_END(0, req
->mc_cpu
);
1070 thrd
->req_running
= -1;
1073 static inline u32
_state(struct pl330_thread
*thrd
)
1075 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1078 if (is_manager(thrd
))
1079 val
= readl(regs
+ DS
) & 0xf;
1081 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
1085 return PL330_STATE_STOPPED
;
1087 return PL330_STATE_EXECUTING
;
1089 return PL330_STATE_CACHEMISS
;
1091 return PL330_STATE_UPDTPC
;
1093 return PL330_STATE_WFE
;
1095 return PL330_STATE_FAULTING
;
1097 if (is_manager(thrd
))
1098 return PL330_STATE_INVALID
;
1100 return PL330_STATE_ATBARRIER
;
1102 if (is_manager(thrd
))
1103 return PL330_STATE_INVALID
;
1105 return PL330_STATE_QUEUEBUSY
;
1107 if (is_manager(thrd
))
1108 return PL330_STATE_INVALID
;
1110 return PL330_STATE_WFP
;
1112 if (is_manager(thrd
))
1113 return PL330_STATE_INVALID
;
1115 return PL330_STATE_KILLING
;
1117 if (is_manager(thrd
))
1118 return PL330_STATE_INVALID
;
1120 return PL330_STATE_COMPLETING
;
1122 if (is_manager(thrd
))
1123 return PL330_STATE_INVALID
;
1125 return PL330_STATE_FAULT_COMPLETING
;
1127 return PL330_STATE_INVALID
;
1131 static void _stop(struct pl330_thread
*thrd
)
1133 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1134 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1136 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
1137 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1139 /* Return if nothing needs to be done */
1140 if (_state(thrd
) == PL330_STATE_COMPLETING
1141 || _state(thrd
) == PL330_STATE_KILLING
1142 || _state(thrd
) == PL330_STATE_STOPPED
)
1145 _emit_KILL(0, insn
);
1147 /* Stop generating interrupts for SEV */
1148 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
1150 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
1153 /* Start doing req 'idx' of thread 'thrd' */
1154 static bool _trigger(struct pl330_thread
*thrd
)
1156 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1157 struct _pl330_req
*req
;
1158 struct pl330_req
*r
;
1161 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1164 /* Return if already ACTIVE */
1165 if (_state(thrd
) != PL330_STATE_STOPPED
)
1168 idx
= 1 - thrd
->lstenq
;
1169 if (!IS_FREE(&thrd
->req
[idx
]))
1170 req
= &thrd
->req
[idx
];
1173 if (!IS_FREE(&thrd
->req
[idx
]))
1174 req
= &thrd
->req
[idx
];
1179 /* Return if no request */
1180 if (!req
|| !req
->r
)
1186 ns
= r
->cfg
->nonsecure
? 1 : 0;
1187 else if (readl(regs
+ CS(thrd
->id
)) & CS_CNS
)
1192 /* See 'Abort Sources' point-4 at Page 2-25 */
1193 if (_manager_ns(thrd
) && !ns
)
1194 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Recipe for ABORT!\n",
1195 __func__
, __LINE__
);
1198 go
.addr
= req
->mc_bus
;
1200 _emit_GO(0, insn
, &go
);
1202 /* Set to generate interrupts for SEV */
1203 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1205 /* Only manager can execute GO */
1206 _execute_DBGINSN(thrd
, insn
, true);
1208 thrd
->req_running
= idx
;
1213 static bool _start(struct pl330_thread
*thrd
)
1215 switch (_state(thrd
)) {
1216 case PL330_STATE_FAULT_COMPLETING
:
1217 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1219 if (_state(thrd
) == PL330_STATE_KILLING
)
1220 UNTIL(thrd
, PL330_STATE_STOPPED
)
1222 case PL330_STATE_FAULTING
:
1225 case PL330_STATE_KILLING
:
1226 case PL330_STATE_COMPLETING
:
1227 UNTIL(thrd
, PL330_STATE_STOPPED
)
1229 case PL330_STATE_STOPPED
:
1230 return _trigger(thrd
);
1232 case PL330_STATE_WFP
:
1233 case PL330_STATE_QUEUEBUSY
:
1234 case PL330_STATE_ATBARRIER
:
1235 case PL330_STATE_UPDTPC
:
1236 case PL330_STATE_CACHEMISS
:
1237 case PL330_STATE_EXECUTING
:
1240 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1246 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1247 const struct _xfer_spec
*pxs
, int cyc
)
1250 struct pl330_config
*pcfg
= pxs
->r
->cfg
->pcfg
;
1252 /* check lock-up free version */
1253 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1255 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1256 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1260 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1261 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1262 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1263 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1270 static inline int _ldst_devtomem(unsigned dry_run
, u8 buf
[],
1271 const struct _xfer_spec
*pxs
, int cyc
)
1276 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1277 off
+= _emit_LDP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1278 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1279 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1285 static inline int _ldst_memtodev(unsigned dry_run
, u8 buf
[],
1286 const struct _xfer_spec
*pxs
, int cyc
)
1291 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1292 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1293 off
+= _emit_STP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1294 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1300 static int _bursts(unsigned dry_run
, u8 buf
[],
1301 const struct _xfer_spec
*pxs
, int cyc
)
1305 switch (pxs
->r
->rqtype
) {
1307 off
+= _ldst_memtodev(dry_run
, &buf
[off
], pxs
, cyc
);
1310 off
+= _ldst_devtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1313 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1316 off
+= 0x40000000; /* Scare off the Client */
1323 /* Returns bytes consumed and updates bursts */
1324 static inline int _loop(unsigned dry_run
, u8 buf
[],
1325 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1327 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1328 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1329 struct _arg_LPEND lpend
;
1331 /* Max iterations possible in DMALP is 256 */
1332 if (*bursts
>= 256*256) {
1335 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1336 } else if (*bursts
> 256) {
1338 lcnt0
= *bursts
/ lcnt1
;
1346 szlp
= _emit_LP(1, buf
, 0, 0);
1347 szbrst
= _bursts(1, buf
, pxs
, 1);
1349 lpend
.cond
= ALWAYS
;
1350 lpend
.forever
= false;
1353 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1361 * Max bursts that we can unroll due to limit on the
1362 * size of backward jump that can be encoded in DMALPEND
1363 * which is 8-bits and hence 255
1365 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1367 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1372 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1376 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1379 off
+= _bursts(dry_run
, &buf
[off
], pxs
, cyc
);
1381 lpend
.cond
= ALWAYS
;
1382 lpend
.forever
= false;
1384 lpend
.bjump
= off
- ljmp1
;
1385 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1388 lpend
.cond
= ALWAYS
;
1389 lpend
.forever
= false;
1391 lpend
.bjump
= off
- ljmp0
;
1392 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1395 *bursts
= lcnt1
* cyc
;
1402 static inline int _setup_loops(unsigned dry_run
, u8 buf
[],
1403 const struct _xfer_spec
*pxs
)
1405 struct pl330_xfer
*x
= pxs
->x
;
1407 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1412 off
+= _loop(dry_run
, &buf
[off
], &c
, pxs
);
1419 static inline int _setup_xfer(unsigned dry_run
, u8 buf
[],
1420 const struct _xfer_spec
*pxs
)
1422 struct pl330_xfer
*x
= pxs
->x
;
1425 /* DMAMOV SAR, x->src_addr */
1426 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1427 /* DMAMOV DAR, x->dst_addr */
1428 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1431 off
+= _setup_loops(dry_run
, &buf
[off
], pxs
);
1437 * A req is a sequence of one or more xfer units.
1438 * Returns the number of bytes taken to setup the MC for the req.
1440 static int _setup_req(unsigned dry_run
, struct pl330_thread
*thrd
,
1441 unsigned index
, struct _xfer_spec
*pxs
)
1443 struct _pl330_req
*req
= &thrd
->req
[index
];
1444 struct pl330_xfer
*x
;
1445 u8
*buf
= req
->mc_cpu
;
1448 PL330_DBGMC_START(req
->mc_bus
);
1450 /* DMAMOV CCR, ccr */
1451 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1455 /* Error if xfer length is not aligned at burst size */
1456 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1460 off
+= _setup_xfer(dry_run
, &buf
[off
], pxs
);
1465 /* DMASEV peripheral/event */
1466 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1468 off
+= _emit_END(dry_run
, &buf
[off
]);
1473 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1483 /* We set same protection levels for Src and DST for now */
1484 if (rqc
->privileged
)
1485 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1487 ccr
|= CC_SRCNS
| CC_DSTNS
;
1488 if (rqc
->insnaccess
)
1489 ccr
|= CC_SRCIA
| CC_DSTIA
;
1491 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1492 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1494 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1495 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1497 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1498 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1500 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1505 static inline bool _is_valid(u32 ccr
)
1507 enum pl330_dstcachectrl dcctl
;
1508 enum pl330_srccachectrl scctl
;
1510 dcctl
= (ccr
>> CC_DSTCCTRL_SHFT
) & CC_DRCCCTRL_MASK
;
1511 scctl
= (ccr
>> CC_SRCCCTRL_SHFT
) & CC_SRCCCTRL_MASK
;
1513 if (dcctl
== DINVALID1
|| dcctl
== DINVALID2
1514 || scctl
== SINVALID1
|| scctl
== SINVALID2
)
1521 * Submit a list of xfers after which the client wants notification.
1522 * Client is not notified after each xfer unit, just once after all
1523 * xfer units are done or some error occurs.
1525 static int pl330_submit_req(void *ch_id
, struct pl330_req
*r
)
1527 struct pl330_thread
*thrd
= ch_id
;
1528 struct pl330_dmac
*pl330
;
1529 struct pl330_info
*pi
;
1530 struct _xfer_spec xs
;
1531 unsigned long flags
;
1537 /* No Req or Unacquired Channel or DMAC */
1538 if (!r
|| !thrd
|| thrd
->free
)
1545 if (pl330
->state
== DYING
1546 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1547 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d\n",
1548 __func__
, __LINE__
);
1552 /* If request for non-existing peripheral */
1553 if (r
->rqtype
!= MEMTOMEM
&& r
->peri
>= pi
->pcfg
.num_peri
) {
1554 dev_info(thrd
->dmac
->pinfo
->dev
,
1555 "%s:%d Invalid peripheral(%u)!\n",
1556 __func__
, __LINE__
, r
->peri
);
1560 spin_lock_irqsave(&pl330
->lock
, flags
);
1562 if (_queue_full(thrd
)) {
1568 /* Use last settings, if not provided */
1570 /* Prefer Secure Channel */
1571 if (!_manager_ns(thrd
))
1572 r
->cfg
->nonsecure
= 0;
1574 r
->cfg
->nonsecure
= 1;
1576 ccr
= _prepare_ccr(r
->cfg
);
1578 ccr
= readl(regs
+ CC(thrd
->id
));
1581 /* If this req doesn't have valid xfer settings */
1582 if (!_is_valid(ccr
)) {
1584 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Invalid CCR(%x)!\n",
1585 __func__
, __LINE__
, ccr
);
1589 idx
= IS_FREE(&thrd
->req
[0]) ? 0 : 1;
1594 /* First dry run to check if req is acceptable */
1595 ret
= _setup_req(1, thrd
, idx
, &xs
);
1599 if (ret
> pi
->mcbufsz
/ 2) {
1600 dev_info(thrd
->dmac
->pinfo
->dev
,
1601 "%s:%d Trying increasing mcbufsz\n",
1602 __func__
, __LINE__
);
1607 /* Hook the request */
1609 thrd
->req
[idx
].mc_len
= _setup_req(0, thrd
, idx
, &xs
);
1610 thrd
->req
[idx
].r
= r
;
1615 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1620 static void pl330_dotask(unsigned long data
)
1622 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1623 struct pl330_info
*pi
= pl330
->pinfo
;
1624 unsigned long flags
;
1627 spin_lock_irqsave(&pl330
->lock
, flags
);
1629 /* The DMAC itself gone nuts */
1630 if (pl330
->dmac_tbd
.reset_dmac
) {
1631 pl330
->state
= DYING
;
1632 /* Reset the manager too */
1633 pl330
->dmac_tbd
.reset_mngr
= true;
1634 /* Clear the reset flag */
1635 pl330
->dmac_tbd
.reset_dmac
= false;
1638 if (pl330
->dmac_tbd
.reset_mngr
) {
1639 _stop(pl330
->manager
);
1640 /* Reset all channels */
1641 pl330
->dmac_tbd
.reset_chan
= (1 << pi
->pcfg
.num_chan
) - 1;
1642 /* Clear the reset flag */
1643 pl330
->dmac_tbd
.reset_mngr
= false;
1646 for (i
= 0; i
< pi
->pcfg
.num_chan
; i
++) {
1648 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1649 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1650 void __iomem
*regs
= pi
->base
;
1651 enum pl330_op_err err
;
1655 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1656 err
= PL330_ERR_FAIL
;
1658 err
= PL330_ERR_ABORT
;
1660 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1662 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, err
);
1663 _callback(thrd
->req
[thrd
->lstenq
].r
, err
);
1665 spin_lock_irqsave(&pl330
->lock
, flags
);
1667 thrd
->req
[0].r
= NULL
;
1668 thrd
->req
[1].r
= NULL
;
1672 /* Clear the reset flag */
1673 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1677 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1682 /* Returns 1 if state was updated, 0 otherwise */
1683 static int pl330_update(const struct pl330_info
*pi
)
1685 struct pl330_req
*rqdone
, *tmp
;
1686 struct pl330_dmac
*pl330
;
1687 unsigned long flags
;
1690 int id
, ev
, ret
= 0;
1692 if (!pi
|| !pi
->pl330_data
)
1696 pl330
= pi
->pl330_data
;
1698 spin_lock_irqsave(&pl330
->lock
, flags
);
1700 val
= readl(regs
+ FSM
) & 0x1;
1702 pl330
->dmac_tbd
.reset_mngr
= true;
1704 pl330
->dmac_tbd
.reset_mngr
= false;
1706 val
= readl(regs
+ FSC
) & ((1 << pi
->pcfg
.num_chan
) - 1);
1707 pl330
->dmac_tbd
.reset_chan
|= val
;
1710 while (i
< pi
->pcfg
.num_chan
) {
1711 if (val
& (1 << i
)) {
1713 "Reset Channel-%d\t CS-%x FTC-%x\n",
1714 i
, readl(regs
+ CS(i
)),
1715 readl(regs
+ FTC(i
)));
1716 _stop(&pl330
->channels
[i
]);
1722 /* Check which event happened i.e, thread notified */
1723 val
= readl(regs
+ ES
);
1724 if (pi
->pcfg
.num_events
< 32
1725 && val
& ~((1 << pi
->pcfg
.num_events
) - 1)) {
1726 pl330
->dmac_tbd
.reset_dmac
= true;
1727 dev_err(pi
->dev
, "%s:%d Unexpected!\n", __func__
, __LINE__
);
1732 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++) {
1733 if (val
& (1 << ev
)) { /* Event occurred */
1734 struct pl330_thread
*thrd
;
1735 u32 inten
= readl(regs
+ INTEN
);
1738 /* Clear the event */
1739 if (inten
& (1 << ev
))
1740 writel(1 << ev
, regs
+ INTCLR
);
1744 id
= pl330
->events
[ev
];
1746 thrd
= &pl330
->channels
[id
];
1748 active
= thrd
->req_running
;
1749 if (active
== -1) /* Aborted */
1752 /* Detach the req */
1753 rqdone
= thrd
->req
[active
].r
;
1754 thrd
->req
[active
].r
= NULL
;
1756 mark_free(thrd
, active
);
1758 /* Get going again ASAP */
1761 /* For now, just make a list of callbacks to be done */
1762 list_add_tail(&rqdone
->rqd
, &pl330
->req_done
);
1766 /* Now that we are in no hurry, do the callbacks */
1767 list_for_each_entry_safe(rqdone
, tmp
, &pl330
->req_done
, rqd
) {
1768 list_del(&rqdone
->rqd
);
1770 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1771 _callback(rqdone
, PL330_ERR_NONE
);
1772 spin_lock_irqsave(&pl330
->lock
, flags
);
1776 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1778 if (pl330
->dmac_tbd
.reset_dmac
1779 || pl330
->dmac_tbd
.reset_mngr
1780 || pl330
->dmac_tbd
.reset_chan
) {
1782 tasklet_schedule(&pl330
->tasks
);
1788 static int pl330_chan_ctrl(void *ch_id
, enum pl330_chan_op op
)
1790 struct pl330_thread
*thrd
= ch_id
;
1791 struct pl330_dmac
*pl330
;
1792 unsigned long flags
;
1793 int ret
= 0, active
;
1795 if (!thrd
|| thrd
->free
|| thrd
->dmac
->state
== DYING
)
1799 active
= thrd
->req_running
;
1801 spin_lock_irqsave(&pl330
->lock
, flags
);
1804 case PL330_OP_FLUSH
:
1805 /* Make sure the channel is stopped */
1808 thrd
->req
[0].r
= NULL
;
1809 thrd
->req
[1].r
= NULL
;
1814 case PL330_OP_ABORT
:
1815 /* Make sure the channel is stopped */
1818 /* ABORT is only for the active req */
1822 thrd
->req
[active
].r
= NULL
;
1823 mark_free(thrd
, active
);
1825 /* Start the next */
1826 case PL330_OP_START
:
1827 if ((active
== -1) && !_start(thrd
))
1835 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1839 /* Reserve an event */
1840 static inline int _alloc_event(struct pl330_thread
*thrd
)
1842 struct pl330_dmac
*pl330
= thrd
->dmac
;
1843 struct pl330_info
*pi
= pl330
->pinfo
;
1846 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++)
1847 if (pl330
->events
[ev
] == -1) {
1848 pl330
->events
[ev
] = thrd
->id
;
1855 static bool _chan_ns(const struct pl330_info
*pi
, int i
)
1857 return pi
->pcfg
.irq_ns
& (1 << i
);
1860 /* Upon success, returns IdentityToken for the
1861 * allocated channel, NULL otherwise.
1863 static void *pl330_request_channel(const struct pl330_info
*pi
)
1865 struct pl330_thread
*thrd
= NULL
;
1866 struct pl330_dmac
*pl330
;
1867 unsigned long flags
;
1870 if (!pi
|| !pi
->pl330_data
)
1873 pl330
= pi
->pl330_data
;
1875 if (pl330
->state
== DYING
)
1878 chans
= pi
->pcfg
.num_chan
;
1880 spin_lock_irqsave(&pl330
->lock
, flags
);
1882 for (i
= 0; i
< chans
; i
++) {
1883 thrd
= &pl330
->channels
[i
];
1884 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1886 thrd
->ev
= _alloc_event(thrd
);
1887 if (thrd
->ev
>= 0) {
1890 thrd
->req
[0].r
= NULL
;
1892 thrd
->req
[1].r
= NULL
;
1900 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1905 /* Release an event */
1906 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1908 struct pl330_dmac
*pl330
= thrd
->dmac
;
1909 struct pl330_info
*pi
= pl330
->pinfo
;
1911 /* If the event is valid and was held by the thread */
1912 if (ev
>= 0 && ev
< pi
->pcfg
.num_events
1913 && pl330
->events
[ev
] == thrd
->id
)
1914 pl330
->events
[ev
] = -1;
1917 static void pl330_release_channel(void *ch_id
)
1919 struct pl330_thread
*thrd
= ch_id
;
1920 struct pl330_dmac
*pl330
;
1921 unsigned long flags
;
1923 if (!thrd
|| thrd
->free
)
1928 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1929 _callback(thrd
->req
[thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1933 spin_lock_irqsave(&pl330
->lock
, flags
);
1934 _free_event(thrd
, thrd
->ev
);
1936 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1939 /* Initialize the structure for PL330 configuration, that can be used
1940 * by the client driver the make best use of the DMAC
1942 static void read_dmac_config(struct pl330_info
*pi
)
1944 void __iomem
*regs
= pi
->base
;
1947 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1948 val
&= CRD_DATA_WIDTH_MASK
;
1949 pi
->pcfg
.data_bus_width
= 8 * (1 << val
);
1951 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1952 val
&= CRD_DATA_BUFF_MASK
;
1953 pi
->pcfg
.data_buf_dep
= val
+ 1;
1955 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1956 val
&= CR0_NUM_CHANS_MASK
;
1958 pi
->pcfg
.num_chan
= val
;
1960 val
= readl(regs
+ CR0
);
1961 if (val
& CR0_PERIPH_REQ_SET
) {
1962 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1964 pi
->pcfg
.num_peri
= val
;
1965 pi
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1967 pi
->pcfg
.num_peri
= 0;
1970 val
= readl(regs
+ CR0
);
1971 if (val
& CR0_BOOT_MAN_NS
)
1972 pi
->pcfg
.mode
|= DMAC_MODE_NS
;
1974 pi
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1976 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1977 val
&= CR0_NUM_EVENTS_MASK
;
1979 pi
->pcfg
.num_events
= val
;
1981 pi
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1983 pi
->pcfg
.periph_id
= get_id(pi
, PERIPH_ID
);
1984 pi
->pcfg
.pcell_id
= get_id(pi
, PCELL_ID
);
1987 static inline void _reset_thread(struct pl330_thread
*thrd
)
1989 struct pl330_dmac
*pl330
= thrd
->dmac
;
1990 struct pl330_info
*pi
= pl330
->pinfo
;
1992 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1993 + (thrd
->id
* pi
->mcbufsz
);
1994 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1995 + (thrd
->id
* pi
->mcbufsz
);
1996 thrd
->req
[0].r
= NULL
;
1999 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
2001 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
2003 thrd
->req
[1].r
= NULL
;
2007 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
2009 struct pl330_info
*pi
= pl330
->pinfo
;
2010 int chans
= pi
->pcfg
.num_chan
;
2011 struct pl330_thread
*thrd
;
2014 /* Allocate 1 Manager and 'chans' Channel threads */
2015 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
2017 if (!pl330
->channels
)
2020 /* Init Channel threads */
2021 for (i
= 0; i
< chans
; i
++) {
2022 thrd
= &pl330
->channels
[i
];
2025 _reset_thread(thrd
);
2029 /* MANAGER is indexed at the end */
2030 thrd
= &pl330
->channels
[chans
];
2034 pl330
->manager
= thrd
;
2039 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
2041 struct pl330_info
*pi
= pl330
->pinfo
;
2042 int chans
= pi
->pcfg
.num_chan
;
2046 * Alloc MicroCode buffer for 'chans' Channel threads.
2047 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2049 pl330
->mcode_cpu
= dma_alloc_coherent(pi
->dev
,
2050 chans
* pi
->mcbufsz
,
2051 &pl330
->mcode_bus
, GFP_KERNEL
);
2052 if (!pl330
->mcode_cpu
) {
2053 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
2054 __func__
, __LINE__
);
2058 ret
= dmac_alloc_threads(pl330
);
2060 dev_err(pi
->dev
, "%s:%d Can't to create channels for DMAC!\n",
2061 __func__
, __LINE__
);
2062 dma_free_coherent(pi
->dev
,
2063 chans
* pi
->mcbufsz
,
2064 pl330
->mcode_cpu
, pl330
->mcode_bus
);
2071 static int pl330_add(struct pl330_info
*pi
)
2073 struct pl330_dmac
*pl330
;
2077 if (!pi
|| !pi
->dev
)
2080 /* If already added */
2085 * If the SoC can perform reset on the DMAC, then do it
2086 * before reading its configuration.
2093 /* Check if we can handle this DMAC */
2094 if ((get_id(pi
, PERIPH_ID
) & 0xfffff) != PERIPH_ID_VAL
2095 || get_id(pi
, PCELL_ID
) != PCELL_ID_VAL
) {
2096 dev_err(pi
->dev
, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n",
2097 get_id(pi
, PERIPH_ID
), get_id(pi
, PCELL_ID
));
2101 /* Read the configuration of the DMAC */
2102 read_dmac_config(pi
);
2104 if (pi
->pcfg
.num_events
== 0) {
2105 dev_err(pi
->dev
, "%s:%d Can't work without events!\n",
2106 __func__
, __LINE__
);
2110 pl330
= kzalloc(sizeof(*pl330
), GFP_KERNEL
);
2112 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
2113 __func__
, __LINE__
);
2117 /* Assign the info structure and private data */
2119 pi
->pl330_data
= pl330
;
2121 spin_lock_init(&pl330
->lock
);
2123 INIT_LIST_HEAD(&pl330
->req_done
);
2125 /* Use default MC buffer size if not provided */
2127 pi
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
2129 /* Mark all events as free */
2130 for (i
= 0; i
< pi
->pcfg
.num_events
; i
++)
2131 pl330
->events
[i
] = -1;
2133 /* Allocate resources needed by the DMAC */
2134 ret
= dmac_alloc_resources(pl330
);
2136 dev_err(pi
->dev
, "Unable to create channels for DMAC\n");
2141 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
2143 pl330
->state
= INIT
;
2148 static int dmac_free_threads(struct pl330_dmac
*pl330
)
2150 struct pl330_info
*pi
= pl330
->pinfo
;
2151 int chans
= pi
->pcfg
.num_chan
;
2152 struct pl330_thread
*thrd
;
2155 /* Release Channel threads */
2156 for (i
= 0; i
< chans
; i
++) {
2157 thrd
= &pl330
->channels
[i
];
2158 pl330_release_channel((void *)thrd
);
2162 kfree(pl330
->channels
);
2167 static void dmac_free_resources(struct pl330_dmac
*pl330
)
2169 struct pl330_info
*pi
= pl330
->pinfo
;
2170 int chans
= pi
->pcfg
.num_chan
;
2172 dmac_free_threads(pl330
);
2174 dma_free_coherent(pi
->dev
, chans
* pi
->mcbufsz
,
2175 pl330
->mcode_cpu
, pl330
->mcode_bus
);
2178 static void pl330_del(struct pl330_info
*pi
)
2180 struct pl330_dmac
*pl330
;
2182 if (!pi
|| !pi
->pl330_data
)
2185 pl330
= pi
->pl330_data
;
2187 pl330
->state
= UNINIT
;
2189 tasklet_kill(&pl330
->tasks
);
2191 /* Free DMAC resources */
2192 dmac_free_resources(pl330
);
2195 pi
->pl330_data
= NULL
;
2198 /* forward declaration */
2199 static struct amba_driver pl330_driver
;
2201 static inline struct dma_pl330_chan
*
2202 to_pchan(struct dma_chan
*ch
)
2207 return container_of(ch
, struct dma_pl330_chan
, chan
);
2210 static inline struct dma_pl330_desc
*
2211 to_desc(struct dma_async_tx_descriptor
*tx
)
2213 return container_of(tx
, struct dma_pl330_desc
, txd
);
2216 static inline void free_desc_list(struct list_head
*list
)
2218 struct dma_pl330_dmac
*pdmac
;
2219 struct dma_pl330_desc
*desc
;
2220 struct dma_pl330_chan
*pch
= NULL
;
2221 unsigned long flags
;
2223 /* Finish off the work list */
2224 list_for_each_entry(desc
, list
, node
) {
2225 dma_async_tx_callback callback
;
2228 /* All desc in a list belong to same channel */
2230 callback
= desc
->txd
.callback
;
2231 param
= desc
->txd
.callback_param
;
2239 /* pch will be unset if list was empty */
2245 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2246 list_splice_tail_init(list
, &pdmac
->desc_pool
);
2247 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2250 static inline void handle_cyclic_desc_list(struct list_head
*list
)
2252 struct dma_pl330_desc
*desc
;
2253 struct dma_pl330_chan
*pch
= NULL
;
2254 unsigned long flags
;
2256 list_for_each_entry(desc
, list
, node
) {
2257 dma_async_tx_callback callback
;
2259 /* Change status to reload it */
2260 desc
->status
= PREP
;
2262 callback
= desc
->txd
.callback
;
2264 callback(desc
->txd
.callback_param
);
2267 /* pch will be unset if list was empty */
2271 spin_lock_irqsave(&pch
->lock
, flags
);
2272 list_splice_tail_init(list
, &pch
->work_list
);
2273 spin_unlock_irqrestore(&pch
->lock
, flags
);
2276 static inline void fill_queue(struct dma_pl330_chan
*pch
)
2278 struct dma_pl330_desc
*desc
;
2281 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2283 /* If already submitted */
2284 if (desc
->status
== BUSY
)
2287 ret
= pl330_submit_req(pch
->pl330_chid
,
2290 desc
->status
= BUSY
;
2292 } else if (ret
== -EAGAIN
) {
2293 /* QFull or DMAC Dying */
2296 /* Unacceptable request */
2297 desc
->status
= DONE
;
2298 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Bad Desc(%d)\n",
2299 __func__
, __LINE__
, desc
->txd
.cookie
);
2300 tasklet_schedule(&pch
->task
);
2305 static void pl330_tasklet(unsigned long data
)
2307 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
2308 struct dma_pl330_desc
*desc
, *_dt
;
2309 unsigned long flags
;
2312 spin_lock_irqsave(&pch
->lock
, flags
);
2314 /* Pick up ripe tomatoes */
2315 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
2316 if (desc
->status
== DONE
) {
2318 dma_cookie_complete(&desc
->txd
);
2319 list_move_tail(&desc
->node
, &list
);
2322 /* Try to submit a req imm. next to the last completed cookie */
2325 /* Make sure the PL330 Channel thread is active */
2326 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_START
);
2328 spin_unlock_irqrestore(&pch
->lock
, flags
);
2331 handle_cyclic_desc_list(&list
);
2333 free_desc_list(&list
);
2336 static void dma_pl330_rqcb(void *token
, enum pl330_op_err err
)
2338 struct dma_pl330_desc
*desc
= token
;
2339 struct dma_pl330_chan
*pch
= desc
->pchan
;
2340 unsigned long flags
;
2342 /* If desc aborted */
2346 spin_lock_irqsave(&pch
->lock
, flags
);
2348 desc
->status
= DONE
;
2350 spin_unlock_irqrestore(&pch
->lock
, flags
);
2352 tasklet_schedule(&pch
->task
);
2355 bool pl330_filter(struct dma_chan
*chan
, void *param
)
2359 if (chan
->device
->dev
->driver
!= &pl330_driver
.drv
)
2363 if (chan
->device
->dev
->of_node
) {
2364 const __be32
*prop_value
;
2366 struct device_node
*node
;
2368 prop_value
= ((struct property
*)param
)->value
;
2369 phandle
= be32_to_cpup(prop_value
++);
2370 node
= of_find_node_by_phandle(phandle
);
2371 return ((chan
->private == node
) &&
2372 (chan
->chan_id
== be32_to_cpup(prop_value
)));
2376 peri_id
= chan
->private;
2377 return *peri_id
== (unsigned)param
;
2379 EXPORT_SYMBOL(pl330_filter
);
2381 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2383 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2384 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2385 unsigned long flags
;
2387 spin_lock_irqsave(&pch
->lock
, flags
);
2389 dma_cookie_init(chan
);
2390 pch
->cyclic
= false;
2392 pch
->pl330_chid
= pl330_request_channel(&pdmac
->pif
);
2393 if (!pch
->pl330_chid
) {
2394 spin_unlock_irqrestore(&pch
->lock
, flags
);
2398 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2400 spin_unlock_irqrestore(&pch
->lock
, flags
);
2405 static int pl330_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
, unsigned long arg
)
2407 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2408 struct dma_pl330_desc
*desc
, *_dt
;
2409 unsigned long flags
;
2410 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2411 struct dma_slave_config
*slave_config
;
2415 case DMA_TERMINATE_ALL
:
2416 spin_lock_irqsave(&pch
->lock
, flags
);
2418 /* FLUSH the PL330 Channel thread */
2419 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_FLUSH
);
2421 /* Mark all desc done */
2422 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
) {
2423 desc
->status
= DONE
;
2424 list_move_tail(&desc
->node
, &list
);
2427 list_splice_tail_init(&list
, &pdmac
->desc_pool
);
2428 spin_unlock_irqrestore(&pch
->lock
, flags
);
2430 case DMA_SLAVE_CONFIG
:
2431 slave_config
= (struct dma_slave_config
*)arg
;
2433 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2434 if (slave_config
->dst_addr
)
2435 pch
->fifo_addr
= slave_config
->dst_addr
;
2436 if (slave_config
->dst_addr_width
)
2437 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2438 if (slave_config
->dst_maxburst
)
2439 pch
->burst_len
= slave_config
->dst_maxburst
;
2440 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2441 if (slave_config
->src_addr
)
2442 pch
->fifo_addr
= slave_config
->src_addr
;
2443 if (slave_config
->src_addr_width
)
2444 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2445 if (slave_config
->src_maxburst
)
2446 pch
->burst_len
= slave_config
->src_maxburst
;
2450 dev_err(pch
->dmac
->pif
.dev
, "Not supported command.\n");
2457 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2459 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2460 unsigned long flags
;
2462 spin_lock_irqsave(&pch
->lock
, flags
);
2464 tasklet_kill(&pch
->task
);
2466 pl330_release_channel(pch
->pl330_chid
);
2467 pch
->pl330_chid
= NULL
;
2470 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2472 spin_unlock_irqrestore(&pch
->lock
, flags
);
2475 static enum dma_status
2476 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2477 struct dma_tx_state
*txstate
)
2479 return dma_cookie_status(chan
, cookie
, txstate
);
2482 static void pl330_issue_pending(struct dma_chan
*chan
)
2484 pl330_tasklet((unsigned long) to_pchan(chan
));
2488 * We returned the last one of the circular list of descriptor(s)
2489 * from prep_xxx, so the argument to submit corresponds to the last
2490 * descriptor of the list.
2492 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2494 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2495 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2496 dma_cookie_t cookie
;
2497 unsigned long flags
;
2499 spin_lock_irqsave(&pch
->lock
, flags
);
2501 /* Assign cookies to all nodes */
2502 while (!list_empty(&last
->node
)) {
2503 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2505 dma_cookie_assign(&desc
->txd
);
2507 list_move_tail(&desc
->node
, &pch
->work_list
);
2510 cookie
= dma_cookie_assign(&last
->txd
);
2511 list_add_tail(&last
->node
, &pch
->work_list
);
2512 spin_unlock_irqrestore(&pch
->lock
, flags
);
2517 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2520 desc
->req
.x
= &desc
->px
;
2521 desc
->req
.token
= desc
;
2522 desc
->rqcfg
.swap
= SWAP_NO
;
2523 desc
->rqcfg
.privileged
= 0;
2524 desc
->rqcfg
.insnaccess
= 0;
2525 desc
->rqcfg
.scctl
= SCCTRL0
;
2526 desc
->rqcfg
.dcctl
= DCCTRL0
;
2527 desc
->req
.cfg
= &desc
->rqcfg
;
2528 desc
->req
.xfer_cb
= dma_pl330_rqcb
;
2529 desc
->txd
.tx_submit
= pl330_tx_submit
;
2531 INIT_LIST_HEAD(&desc
->node
);
2534 /* Returns the number of descriptors added to the DMAC pool */
2535 static int add_desc(struct dma_pl330_dmac
*pdmac
, gfp_t flg
, int count
)
2537 struct dma_pl330_desc
*desc
;
2538 unsigned long flags
;
2544 desc
= kmalloc(count
* sizeof(*desc
), flg
);
2548 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2550 for (i
= 0; i
< count
; i
++) {
2551 _init_desc(&desc
[i
]);
2552 list_add_tail(&desc
[i
].node
, &pdmac
->desc_pool
);
2555 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2560 static struct dma_pl330_desc
*
2561 pluck_desc(struct dma_pl330_dmac
*pdmac
)
2563 struct dma_pl330_desc
*desc
= NULL
;
2564 unsigned long flags
;
2569 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2571 if (!list_empty(&pdmac
->desc_pool
)) {
2572 desc
= list_entry(pdmac
->desc_pool
.next
,
2573 struct dma_pl330_desc
, node
);
2575 list_del_init(&desc
->node
);
2577 desc
->status
= PREP
;
2578 desc
->txd
.callback
= NULL
;
2581 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2586 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2588 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2589 u8
*peri_id
= pch
->chan
.private;
2590 struct dma_pl330_desc
*desc
;
2592 /* Pluck one desc from the pool of DMAC */
2593 desc
= pluck_desc(pdmac
);
2595 /* If the DMAC pool is empty, alloc new */
2597 if (!add_desc(pdmac
, GFP_ATOMIC
, 1))
2601 desc
= pluck_desc(pdmac
);
2603 dev_err(pch
->dmac
->pif
.dev
,
2604 "%s:%d ALERT!\n", __func__
, __LINE__
);
2609 /* Initialize the descriptor */
2611 desc
->txd
.cookie
= 0;
2612 async_tx_ack(&desc
->txd
);
2614 desc
->req
.peri
= peri_id
? pch
->chan
.chan_id
: 0;
2615 desc
->rqcfg
.pcfg
= &pch
->dmac
->pif
.pcfg
;
2617 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2622 static inline void fill_px(struct pl330_xfer
*px
,
2623 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2631 static struct dma_pl330_desc
*
2632 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2633 dma_addr_t src
, size_t len
)
2635 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2638 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2639 __func__
, __LINE__
);
2644 * Ideally we should lookout for reqs bigger than
2645 * those that can be programmed with 256 bytes of
2646 * MC buffer, but considering a req size is seldom
2647 * going to be word-unaligned and more than 200MB,
2649 * Also, should the limit is reached we'd rather
2650 * have the platform increase MC buffer size than
2651 * complicating this API driver.
2653 fill_px(&desc
->px
, dst
, src
, len
);
2658 /* Call after fixing burst size */
2659 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2661 struct dma_pl330_chan
*pch
= desc
->pchan
;
2662 struct pl330_info
*pi
= &pch
->dmac
->pif
;
2665 burst_len
= pi
->pcfg
.data_bus_width
/ 8;
2666 burst_len
*= pi
->pcfg
.data_buf_dep
;
2667 burst_len
>>= desc
->rqcfg
.brst_size
;
2669 /* src/dst_burst_len can't be more than 16 */
2673 while (burst_len
> 1) {
2674 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2682 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2683 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2684 size_t period_len
, enum dma_transfer_direction direction
,
2685 unsigned long flags
, void *context
)
2687 struct dma_pl330_desc
*desc
;
2688 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2692 desc
= pl330_get_desc(pch
);
2694 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2695 __func__
, __LINE__
);
2699 switch (direction
) {
2700 case DMA_MEM_TO_DEV
:
2701 desc
->rqcfg
.src_inc
= 1;
2702 desc
->rqcfg
.dst_inc
= 0;
2703 desc
->req
.rqtype
= MEMTODEV
;
2705 dst
= pch
->fifo_addr
;
2707 case DMA_DEV_TO_MEM
:
2708 desc
->rqcfg
.src_inc
= 0;
2709 desc
->rqcfg
.dst_inc
= 1;
2710 desc
->req
.rqtype
= DEVTOMEM
;
2711 src
= pch
->fifo_addr
;
2715 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Invalid dma direction\n",
2716 __func__
, __LINE__
);
2720 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2721 desc
->rqcfg
.brst_len
= 1;
2725 fill_px(&desc
->px
, dst
, src
, period_len
);
2730 static struct dma_async_tx_descriptor
*
2731 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2732 dma_addr_t src
, size_t len
, unsigned long flags
)
2734 struct dma_pl330_desc
*desc
;
2735 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2736 struct pl330_info
*pi
;
2739 if (unlikely(!pch
|| !len
))
2742 pi
= &pch
->dmac
->pif
;
2744 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2748 desc
->rqcfg
.src_inc
= 1;
2749 desc
->rqcfg
.dst_inc
= 1;
2750 desc
->req
.rqtype
= MEMTOMEM
;
2752 /* Select max possible burst size */
2753 burst
= pi
->pcfg
.data_bus_width
/ 8;
2761 desc
->rqcfg
.brst_size
= 0;
2762 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2763 desc
->rqcfg
.brst_size
++;
2765 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2767 desc
->txd
.flags
= flags
;
2772 static struct dma_async_tx_descriptor
*
2773 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2774 unsigned int sg_len
, enum dma_transfer_direction direction
,
2775 unsigned long flg
, void *context
)
2777 struct dma_pl330_desc
*first
, *desc
= NULL
;
2778 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2779 struct scatterlist
*sg
;
2780 unsigned long flags
;
2784 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2787 addr
= pch
->fifo_addr
;
2791 for_each_sg(sgl
, sg
, sg_len
, i
) {
2793 desc
= pl330_get_desc(pch
);
2795 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2797 dev_err(pch
->dmac
->pif
.dev
,
2798 "%s:%d Unable to fetch desc\n",
2799 __func__
, __LINE__
);
2803 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2805 while (!list_empty(&first
->node
)) {
2806 desc
= list_entry(first
->node
.next
,
2807 struct dma_pl330_desc
, node
);
2808 list_move_tail(&desc
->node
, &pdmac
->desc_pool
);
2811 list_move_tail(&first
->node
, &pdmac
->desc_pool
);
2813 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2821 list_add_tail(&desc
->node
, &first
->node
);
2823 if (direction
== DMA_MEM_TO_DEV
) {
2824 desc
->rqcfg
.src_inc
= 1;
2825 desc
->rqcfg
.dst_inc
= 0;
2826 desc
->req
.rqtype
= MEMTODEV
;
2828 addr
, sg_dma_address(sg
), sg_dma_len(sg
));
2830 desc
->rqcfg
.src_inc
= 0;
2831 desc
->rqcfg
.dst_inc
= 1;
2832 desc
->req
.rqtype
= DEVTOMEM
;
2834 sg_dma_address(sg
), addr
, sg_dma_len(sg
));
2837 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2838 desc
->rqcfg
.brst_len
= 1;
2841 /* Return the last desc in the chain */
2842 desc
->txd
.flags
= flg
;
2846 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2848 if (pl330_update(data
))
2854 static int __devinit
2855 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2857 struct dma_pl330_platdata
*pdat
;
2858 struct dma_pl330_dmac
*pdmac
;
2859 struct dma_pl330_chan
*pch
;
2860 struct pl330_info
*pi
;
2861 struct dma_device
*pd
;
2862 struct resource
*res
;
2866 pdat
= adev
->dev
.platform_data
;
2868 /* Allocate a new DMAC and its Channels */
2869 pdmac
= kzalloc(sizeof(*pdmac
), GFP_KERNEL
);
2871 dev_err(&adev
->dev
, "unable to allocate mem\n");
2876 pi
->dev
= &adev
->dev
;
2877 pi
->pl330_data
= NULL
;
2878 pi
->mcbufsz
= pdat
? pdat
->mcbuf_sz
: 0;
2881 request_mem_region(res
->start
, resource_size(res
), "dma-pl330");
2883 pi
->base
= ioremap(res
->start
, resource_size(res
));
2889 amba_set_drvdata(adev
, pdmac
);
2892 ret
= request_irq(irq
, pl330_irq_handler
, 0,
2893 dev_name(&adev
->dev
), pi
);
2897 ret
= pl330_add(pi
);
2901 INIT_LIST_HEAD(&pdmac
->desc_pool
);
2902 spin_lock_init(&pdmac
->pool_lock
);
2904 /* Create a descriptor pool of default size */
2905 if (!add_desc(pdmac
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2906 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2909 INIT_LIST_HEAD(&pd
->channels
);
2911 /* Initialize channel parameters */
2913 num_chan
= max_t(int, pdat
->nr_valid_peri
, pi
->pcfg
.num_chan
);
2915 num_chan
= max_t(int, pi
->pcfg
.num_peri
, pi
->pcfg
.num_chan
);
2917 pdmac
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2918 if (!pdmac
->peripherals
) {
2920 dev_err(&adev
->dev
, "unable to allocate pdmac->peripherals\n");
2924 for (i
= 0; i
< num_chan
; i
++) {
2925 pch
= &pdmac
->peripherals
[i
];
2926 if (!adev
->dev
.of_node
)
2927 pch
->chan
.private = pdat
? &pdat
->peri_id
[i
] : NULL
;
2929 pch
->chan
.private = adev
->dev
.of_node
;
2931 INIT_LIST_HEAD(&pch
->work_list
);
2932 spin_lock_init(&pch
->lock
);
2933 pch
->pl330_chid
= NULL
;
2934 pch
->chan
.device
= pd
;
2937 /* Add the channel to the DMAC list */
2938 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2941 pd
->dev
= &adev
->dev
;
2943 pd
->cap_mask
= pdat
->cap_mask
;
2945 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2946 if (pi
->pcfg
.num_peri
) {
2947 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2948 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2949 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2953 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2954 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2955 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2956 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2957 pd
->device_tx_status
= pl330_tx_status
;
2958 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2959 pd
->device_control
= pl330_control
;
2960 pd
->device_issue_pending
= pl330_issue_pending
;
2962 ret
= dma_async_device_register(pd
);
2964 dev_err(&adev
->dev
, "unable to register DMAC\n");
2968 dev_info(&adev
->dev
,
2969 "Loaded driver for PL330 DMAC-%d\n", adev
->periphid
);
2970 dev_info(&adev
->dev
,
2971 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2972 pi
->pcfg
.data_buf_dep
,
2973 pi
->pcfg
.data_bus_width
/ 8, pi
->pcfg
.num_chan
,
2974 pi
->pcfg
.num_peri
, pi
->pcfg
.num_events
);
2985 release_mem_region(res
->start
, resource_size(res
));
2991 static int __devexit
pl330_remove(struct amba_device
*adev
)
2993 struct dma_pl330_dmac
*pdmac
= amba_get_drvdata(adev
);
2994 struct dma_pl330_chan
*pch
, *_p
;
2995 struct pl330_info
*pi
;
2996 struct resource
*res
;
3002 amba_set_drvdata(adev
, NULL
);
3005 list_for_each_entry_safe(pch
, _p
, &pdmac
->ddma
.channels
,
3008 /* Remove the channel */
3009 list_del(&pch
->chan
.device_node
);
3011 /* Flush the channel */
3012 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
3013 pl330_free_chan_resources(&pch
->chan
);
3026 release_mem_region(res
->start
, resource_size(res
));
3033 static struct amba_id pl330_ids
[] = {
3041 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
3043 static struct amba_driver pl330_driver
= {
3045 .owner
= THIS_MODULE
,
3046 .name
= "dma-pl330",
3048 .id_table
= pl330_ids
,
3049 .probe
= pl330_probe
,
3050 .remove
= pl330_remove
,
3053 module_amba_driver(pl330_driver
);
3055 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3056 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3057 MODULE_LICENSE("GPL");