2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/platform_device.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/map.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/i2c.h>
27 #include <linux/irq.h>
28 #include <mach/common.h>
29 #include <mach/hardware.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/time.h>
33 #include <asm/mach/map.h>
34 #include <mach/gpio.h>
35 #include <mach/imx-uart.h>
36 #include <mach/iomux-mx27.h>
37 #include <mach/mxc_nand.h>
39 #include <mach/imxfb.h>
45 * Base address of PBC controller, CS4
47 #define PBC_BASE_ADDRESS 0xf4300000
48 #define PBC_REG_ADDR(offset) (void __force __iomem *) \
49 (PBC_BASE_ADDRESS + (offset))
51 /* When the PBC address connection is fixed in h/w, defined as 1 */
54 /* Offsets for the PBC Controller register */
56 * PBC Board version register offset
58 #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
60 * PBC Board control register 1 set address.
62 #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
64 * PBC Board control register 1 clear address.
66 #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
68 /* PBC Board Control Register 1 bit definitions */
69 #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
71 /* to determine the correct external crystal reference */
72 #define CKIH_27MHZ_BIT_SET (1 << 3)
74 static unsigned int mx27ads_pins
[] = {
117 PD11_AOUT_FEC_TX_CLK
,
120 PD14_AOUT_FEC_RX_CLK
,
173 static struct mxc_nand_platform_data mx27ads_nand_board_info
= {
178 /* ADS's NOR flash */
179 static struct physmap_flash_data mx27ads_flash_data
= {
183 static struct resource mx27ads_flash_resource
= {
185 .end
= 0xc0000000 + 0x02000000 - 1,
186 .flags
= IORESOURCE_MEM
,
190 static struct platform_device mx27ads_nor_mtd_device
= {
191 .name
= "physmap-flash",
194 .platform_data
= &mx27ads_flash_data
,
197 .resource
= &mx27ads_flash_resource
,
200 static struct imxi2c_platform_data mx27ads_i2c_data
= {
204 static struct i2c_board_info mx27ads_i2c_devices
[] = {
207 void lcd_power(int on
)
210 __raw_writew(PBC_BCTRL1_LCDON
, PBC_BCTRL1_SET_REG
);
212 __raw_writew(PBC_BCTRL1_LCDON
, PBC_BCTRL1_CLEAR_REG
);
215 static struct imx_fb_videomode mx27ads_modes
[] = {
218 .name
= "Sharp-LQ035Q7",
222 .pixclock
= 188679, /* in ps (5.3MHz) */
235 static struct imx_fb_platform_data mx27ads_fb_data
= {
236 .mode
= mx27ads_modes
,
237 .num_modes
= ARRAY_SIZE(mx27ads_modes
),
240 * - HSYNC active high
241 * - VSYNC active high
242 * - clk notenabled while idle
244 * - data not inverted
245 * - data enable low active
246 * - enable sharp mode
252 .lcd_power
= lcd_power
,
255 static int mx27ads_sdhc1_init(struct device
*dev
, irq_handler_t detect_irq
,
258 return request_irq(IRQ_GPIOE(21), detect_irq
, IRQF_TRIGGER_RISING
,
259 "sdhc1-card-detect", data
);
262 static int mx27ads_sdhc2_init(struct device
*dev
, irq_handler_t detect_irq
,
265 return request_irq(IRQ_GPIOB(7), detect_irq
, IRQF_TRIGGER_RISING
,
266 "sdhc2-card-detect", data
);
269 static void mx27ads_sdhc1_exit(struct device
*dev
, void *data
)
271 free_irq(IRQ_GPIOE(21), data
);
274 static void mx27ads_sdhc2_exit(struct device
*dev
, void *data
)
276 free_irq(IRQ_GPIOB(7), data
);
279 static struct imxmmc_platform_data sdhc1_pdata
= {
280 .init
= mx27ads_sdhc1_init
,
281 .exit
= mx27ads_sdhc1_exit
,
284 static struct imxmmc_platform_data sdhc2_pdata
= {
285 .init
= mx27ads_sdhc2_init
,
286 .exit
= mx27ads_sdhc2_exit
,
289 static struct platform_device
*platform_devices
[] __initdata
= {
290 &mx27ads_nor_mtd_device
,
292 &mxc_w1_master_device
,
295 static struct imxuart_platform_data uart_pdata
[] = {
297 .flags
= IMXUART_HAVE_RTSCTS
,
299 .flags
= IMXUART_HAVE_RTSCTS
,
301 .flags
= IMXUART_HAVE_RTSCTS
,
303 .flags
= IMXUART_HAVE_RTSCTS
,
305 .flags
= IMXUART_HAVE_RTSCTS
,
307 .flags
= IMXUART_HAVE_RTSCTS
,
311 static void __init
mx27ads_board_init(void)
313 mxc_gpio_setup_multiple_pins(mx27ads_pins
, ARRAY_SIZE(mx27ads_pins
),
316 mxc_register_device(&mxc_uart_device0
, &uart_pdata
[0]);
317 mxc_register_device(&mxc_uart_device1
, &uart_pdata
[1]);
318 mxc_register_device(&mxc_uart_device2
, &uart_pdata
[2]);
319 mxc_register_device(&mxc_uart_device3
, &uart_pdata
[3]);
320 mxc_register_device(&mxc_uart_device4
, &uart_pdata
[4]);
321 mxc_register_device(&mxc_uart_device5
, &uart_pdata
[5]);
322 mxc_register_device(&imx27_nand_device
, &mx27ads_nand_board_info
);
324 /* only the i2c master 1 is used on this CPU card */
325 i2c_register_board_info(1, mx27ads_i2c_devices
,
326 ARRAY_SIZE(mx27ads_i2c_devices
));
327 mxc_register_device(&mxc_i2c_device1
, &mx27ads_i2c_data
);
328 mxc_register_device(&mxc_fb_device
, &mx27ads_fb_data
);
329 mxc_register_device(&mxc_sdhc_device0
, &sdhc1_pdata
);
330 mxc_register_device(&mxc_sdhc_device1
, &sdhc2_pdata
);
332 platform_add_devices(platform_devices
, ARRAY_SIZE(platform_devices
));
335 static void __init
mx27ads_timer_init(void)
337 unsigned long fref
= 26000000;
339 if ((__raw_readw(PBC_VERSION_REG
) & CKIH_27MHZ_BIT_SET
) == 0)
342 mx27_clocks_init(fref
);
345 static struct sys_timer mx27ads_timer
= {
346 .init
= mx27ads_timer_init
,
349 static struct map_desc mx27ads_io_desc
[] __initdata
= {
351 .virtual = PBC_BASE_ADDRESS
,
352 .pfn
= __phys_to_pfn(MX27_CS4_BASE_ADDR
),
358 static void __init
mx27ads_map_io(void)
361 iotable_init(mx27ads_io_desc
, ARRAY_SIZE(mx27ads_io_desc
));
364 MACHINE_START(MX27ADS
, "Freescale i.MX27ADS")
365 /* maintainer: Freescale Semiconductor, Inc. */
366 .phys_io
= MX27_AIPI_BASE_ADDR
,
367 .io_pg_offst
= ((MX27_AIPI_BASE_ADDR_VIRT
) >> 18) & 0xfffc,
368 .boot_params
= MX27_PHYS_OFFSET
+ 0x100,
369 .map_io
= mx27ads_map_io
,
370 .init_irq
= mx27_init_irq
,
371 .init_machine
= mx27ads_board_init
,
372 .timer
= &mx27ads_timer
,