| blob | ad3767095422a88f50cc361c215ac3a618fed2b9 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CLONE_BACKWARDS
11 select CPU_PM if (SUSPEND || CPU_IDLE)
12 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
13 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
14 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
15 select GENERIC_IDLE_POLL_SETUP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SCHED_CLOCK
20 select GENERIC_SMP_IDLE_THREAD
21 select GENERIC_STRNCPY_FROM_USER
22 select GENERIC_STRNLEN_USER
23 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_KGDB
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
28 select HAVE_BPF_JIT
29 select HAVE_CONTEXT_TRACKING
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_DEBUG_KMEMLEAK
32 select HAVE_DMA_API_DEBUG
33 select HAVE_DMA_ATTRS
34 select HAVE_DMA_CONTIGUOUS if MMU
35 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
36 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
37 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
38 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
39 select HAVE_GENERIC_DMA_COHERENT
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZ4
45 select HAVE_KERNEL_LZMA
46 select HAVE_KERNEL_LZO
47 select HAVE_KERNEL_XZ
48 select HAVE_KPROBES if !XIP_KERNEL
49 select HAVE_KRETPROBES if (HAVE_KPROBES)
50 select HAVE_MEMBLOCK
51 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
52 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
53 select HAVE_PERF_EVENTS
54 select HAVE_REGS_AND_STACK_ACCESS_API
55 select HAVE_SYSCALL_TRACEPOINTS
56 select HAVE_UID16
57 select IRQ_FORCED_THREADING
58 select KTIME_SCALAR
59 select MODULES_USE_ELF_REL
60 select OLD_SIGACTION
61 select OLD_SIGSUSPEND3
62 select PERF_USE_VMALLOC
63 select RTC_LIB
64 select SYS_SUPPORTS_APM_EMULATION
65 # Above selects are sorted alphabetically; please add new ones
66 # according to that. Thanks.
67 help
68 The ARM series is a line of low-power-consumption RISC chip designs
69 licensed by ARM Ltd and targeted at embedded applications and
70 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
71 manufactured, but legacy ARM-based PC hardware remains popular in
72 Europe. There is an ARM Linux project with a web page at
73 <http://www.arm.linux.org.uk/>.
75 config ARM_HAS_SG_CHAIN
76 bool
78 config NEED_SG_DMA_LENGTH
79 bool
81 config ARM_DMA_USE_IOMMU
82 bool
83 select ARM_HAS_SG_CHAIN
84 select NEED_SG_DMA_LENGTH
86 if ARM_DMA_USE_IOMMU
88 config ARM_DMA_IOMMU_ALIGNMENT
89 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
90 range 4 9
91 default 8
92 help
93 DMA mapping framework by default aligns all buffers to the smallest
94 PAGE_SIZE order which is greater than or equal to the requested buffer
95 size. This works well for buffers up to a few hundreds kilobytes, but
96 for larger buffers it just a waste of address space. Drivers which has
97 relatively small addressing window (like 64Mib) might run out of
98 virtual space with just a few allocations.
100 With this parameter you can specify the maximum PAGE_SIZE order for
101 DMA IOMMU buffers. Larger buffers will be aligned only to this
102 specified order. The order is expressed as a power of two multiplied
103 by the PAGE_SIZE.
105 endif
107 config HAVE_PWM
108 bool
110 config MIGHT_HAVE_PCI
111 bool
113 config SYS_SUPPORTS_APM_EMULATION
114 bool
116 config HAVE_TCM
117 bool
118 select GENERIC_ALLOCATOR
120 config HAVE_PROC_CPU
121 bool
123 config NO_IOPORT
124 bool
126 config EISA
127 bool
128 ---help---
129 The Extended Industry Standard Architecture (EISA) bus was
130 developed as an open alternative to the IBM MicroChannel bus.
132 The EISA bus provided some of the features of the IBM MicroChannel
133 bus while maintaining backward compatibility with cards made for
134 the older ISA bus. The EISA bus saw limited use between 1988 and
135 1995 when it was made obsolete by the PCI bus.
137 Say Y here if you are building a kernel for an EISA-based machine.
139 Otherwise, say N.
141 config SBUS
142 bool
144 config STACKTRACE_SUPPORT
145 bool
146 default y
148 config HAVE_LATENCYTOP_SUPPORT
149 bool
150 depends on !SMP
151 default y
153 config LOCKDEP_SUPPORT
154 bool
155 default y
157 config TRACE_IRQFLAGS_SUPPORT
158 bool
159 default y
161 config RWSEM_GENERIC_SPINLOCK
162 bool
163 default y
165 config RWSEM_XCHGADD_ALGORITHM
166 bool
168 config ARCH_HAS_ILOG2_U32
169 bool
171 config ARCH_HAS_ILOG2_U64
172 bool
174 config ARCH_HAS_CPUFREQ
175 bool
176 help
177 Internal node to signify that the ARCH has CPUFREQ support
178 and that the relevant menu configurations are displayed for
179 it.
181 config ARCH_HAS_BANDGAP
182 bool
184 config GENERIC_HWEIGHT
185 bool
186 default y
188 config GENERIC_CALIBRATE_DELAY
189 bool
190 default y
192 config ARCH_MAY_HAVE_PC_FDC
193 bool
195 config ZONE_DMA
196 bool
198 config NEED_DMA_MAP_STATE
199 def_bool y
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
202 bool
204 config GENERIC_ISA_DMA
205 bool
207 config FIQ
208 bool
210 config NEED_RET_TO_USER
211 bool
213 config ARCH_MTD_XIP
214 bool
216 config VECTORS_BASE
217 hex
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
220 default 0x00000000
221 help
222 The base address of exception vectors. This must be two pages
223 in size.
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
227 default y
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
230 help
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
243 bool
244 help
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
250 bool
251 help
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
257 bool
258 help
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
263 config PHYS_OFFSET
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
266 default DRAM_BASE if !MMU
267 help
268 Please provide the physical address corresponding to the
269 location of main memory in your system.
271 config GENERIC_BUG
272 def_bool y
273 depends on BUG
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
279 menu "System Type"
281 config MMU
282 bool "MMU-based Paged Memory Management Support"
283 default y
284 help
285 Select if you want MMU-based virtualised addressing space
286 support by paged memory management. If unsure, say 'Y'.
288 #
289 # The "ARM system type" choice list is ordered alphabetically by option
290 # text. Please add new entries in the option alphabetic order.
291 #
292 choice
293 prompt "ARM system type"
294 default ARCH_VERSATILE if !MMU
295 default ARCH_MULTIPLATFORM if MMU
297 config ARCH_MULTIPLATFORM
298 bool "Allow multiple platforms to be selected"
299 depends on MMU
300 select ARM_PATCH_PHYS_VIRT
301 select AUTO_ZRELADDR
302 select COMMON_CLK
303 select MULTI_IRQ_HANDLER
304 select SPARSE_IRQ
305 select USE_OF
307 config ARCH_INTEGRATOR
308 bool "ARM Ltd. Integrator family"
309 select ARCH_HAS_CPUFREQ
310 select ARM_AMBA
311 select COMMON_CLK
312 select COMMON_CLK_VERSATILE
313 select GENERIC_CLOCKEVENTS
314 select HAVE_TCM
315 select ICST
316 select MULTI_IRQ_HANDLER
317 select NEED_MACH_MEMORY_H
318 select PLAT_VERSATILE
319 select SPARSE_IRQ
320 select VERSATILE_FPGA_IRQ
321 help
322 Support for ARM's Integrator platform.
324 config ARCH_REALVIEW
325 bool "ARM Ltd. RealView family"
326 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select ARM_AMBA
328 select ARM_TIMER_SP804
329 select COMMON_CLK
330 select COMMON_CLK_VERSATILE
331 select GENERIC_CLOCKEVENTS
332 select GPIO_PL061 if GPIOLIB
333 select ICST
334 select NEED_MACH_MEMORY_H
335 select PLAT_VERSATILE
336 select PLAT_VERSATILE_CLCD
337 help
338 This enables support for ARM Ltd RealView boards.
340 config ARCH_VERSATILE
341 bool "ARM Ltd. Versatile family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_AMBA
344 select ARM_TIMER_SP804
345 select ARM_VIC
346 select CLKDEV_LOOKUP
347 select GENERIC_CLOCKEVENTS
348 select HAVE_MACH_CLKDEV
349 select ICST
350 select PLAT_VERSATILE
351 select PLAT_VERSATILE_CLCD
352 select PLAT_VERSATILE_CLOCK
353 select VERSATILE_FPGA_IRQ
354 help
355 This enables support for ARM Ltd Versatile board.
357 config ARCH_AT91
358 bool "Atmel AT91"
359 select ARCH_REQUIRE_GPIOLIB
360 select CLKDEV_LOOKUP
361 select HAVE_CLK
362 select IRQ_DOMAIN
363 select NEED_MACH_GPIO_H
364 select NEED_MACH_IO_H if PCCARD
365 select PINCTRL
366 select PINCTRL_AT91 if USE_OF
367 help
368 This enables support for systems based on Atmel
369 AT91RM9200 and AT91SAM9* processors.
371 config ARCH_CLPS711X
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
374 select AUTO_ZRELADDR
375 select CLKDEV_LOOKUP
376 select CLKSRC_MMIO
377 select COMMON_CLK
378 select CPU_ARM720T
379 select GENERIC_CLOCKEVENTS
380 select MFD_SYSCON
381 select MULTI_IRQ_HANDLER
382 select SPARSE_IRQ
383 help
384 Support for Cirrus Logic 711x/721x/731x based boards.
386 config ARCH_GEMINI
387 bool "Cortina Systems Gemini"
388 select ARCH_REQUIRE_GPIOLIB
389 select ARCH_USES_GETTIMEOFFSET
390 select CPU_FA526
391 select NEED_MACH_GPIO_H
392 help
393 Support for the Cortina Systems Gemini family SoCs
395 config ARCH_EBSA110
396 bool "EBSA-110"
397 select ARCH_USES_GETTIMEOFFSET
398 select CPU_SA110
399 select ISA
400 select NEED_MACH_IO_H
401 select NEED_MACH_MEMORY_H
402 select NO_IOPORT
403 help
404 This is an evaluation board for the StrongARM processor available
405 from Digital. It has limited hardware on-board, including an
406 Ethernet interface, two PCMCIA sockets, two serial ports and a
407 parallel port.
409 config ARCH_EP93XX
410 bool "EP93xx-based"
411 select ARCH_HAS_HOLES_MEMORYMODEL
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
414 select ARM_AMBA
415 select ARM_VIC
416 select CLKDEV_LOOKUP
417 select CPU_ARM920T
418 select NEED_MACH_MEMORY_H
419 help
420 This enables support for the Cirrus EP93xx series of CPUs.
422 config ARCH_FOOTBRIDGE
423 bool "FootBridge"
424 select CPU_SA110
425 select FOOTBRIDGE
426 select GENERIC_CLOCKEVENTS
427 select HAVE_IDE
428 select NEED_MACH_IO_H if !MMU
429 select NEED_MACH_MEMORY_H
430 help
431 Support for systems based on the DC21285 companion chip
432 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
434 config ARCH_NETX
435 bool "Hilscher NetX based"
436 select ARM_VIC
437 select CLKSRC_MMIO
438 select CPU_ARM926T
439 select GENERIC_CLOCKEVENTS
440 help
441 This enables support for systems based on the Hilscher NetX Soc
443 config ARCH_IOP13XX
444 bool "IOP13xx-based"
445 depends on MMU
446 select CPU_XSC3
447 select NEED_MACH_MEMORY_H
448 select NEED_RET_TO_USER
449 select PCI
450 select PLAT_IOP
451 select VMSPLIT_1G
452 help
453 Support for Intel's IOP13XX (XScale) family of processors.
455 config ARCH_IOP32X
456 bool "IOP32x-based"
457 depends on MMU
458 select ARCH_REQUIRE_GPIOLIB
459 select CPU_XSCALE
460 select NEED_MACH_GPIO_H
461 select NEED_RET_TO_USER
462 select PCI
463 select PLAT_IOP
464 help
465 Support for Intel's 80219 and IOP32X (XScale) family of
466 processors.
468 config ARCH_IOP33X
469 bool "IOP33x-based"
470 depends on MMU
471 select ARCH_REQUIRE_GPIOLIB
472 select CPU_XSCALE
473 select NEED_MACH_GPIO_H
474 select NEED_RET_TO_USER
475 select PCI
476 select PLAT_IOP
477 help
478 Support for Intel's IOP33X (XScale) family of processors.
480 config ARCH_IXP4XX
481 bool "IXP4xx-based"
482 depends on MMU
483 select ARCH_HAS_DMA_SET_COHERENT_MASK
484 select ARCH_REQUIRE_GPIOLIB
485 select CLKSRC_MMIO
486 select CPU_XSCALE
487 select DMABOUNCE if PCI
488 select GENERIC_CLOCKEVENTS
489 select MIGHT_HAVE_PCI
490 select NEED_MACH_IO_H
491 select USB_EHCI_BIG_ENDIAN_DESC
492 select USB_EHCI_BIG_ENDIAN_MMIO
493 help
494 Support for Intel's IXP4XX (XScale) family of processors.
496 config ARCH_DOVE
497 bool "Marvell Dove"
498 select ARCH_REQUIRE_GPIOLIB
499 select CPU_PJ4
500 select GENERIC_CLOCKEVENTS
501 select MIGHT_HAVE_PCI
502 select MVEBU_MBUS
503 select PINCTRL
504 select PINCTRL_DOVE
505 select PLAT_ORION_LEGACY
506 select USB_ARCH_HAS_EHCI
507 help
508 Support for the Marvell Dove SoC 88AP510
510 config ARCH_KIRKWOOD
511 bool "Marvell Kirkwood"
512 select ARCH_HAS_CPUFREQ
513 select ARCH_REQUIRE_GPIOLIB
514 select CPU_FEROCEON
515 select GENERIC_CLOCKEVENTS
516 select MVEBU_MBUS
517 select PCI
518 select PCI_QUIRKS
519 select PINCTRL
520 select PINCTRL_KIRKWOOD
521 select PLAT_ORION_LEGACY
522 help
523 Support for the following Marvell Kirkwood series SoCs:
524 88F6180, 88F6192 and 88F6281.
526 config ARCH_MV78XX0
527 bool "Marvell MV78xx0"
528 select ARCH_REQUIRE_GPIOLIB
529 select CPU_FEROCEON
530 select GENERIC_CLOCKEVENTS
531 select MVEBU_MBUS
532 select PCI
533 select PLAT_ORION_LEGACY
534 help
535 Support for the following Marvell MV78xx0 series SoCs:
536 MV781x0, MV782x0.
538 config ARCH_ORION5X
539 bool "Marvell Orion"
540 depends on MMU
541 select ARCH_REQUIRE_GPIOLIB
542 select CPU_FEROCEON
543 select GENERIC_CLOCKEVENTS
544 select MVEBU_MBUS
545 select PCI
546 select PLAT_ORION_LEGACY
547 help
548 Support for the following Marvell Orion 5x series SoCs:
549 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
550 Orion-2 (5281), Orion-1-90 (6183).
552 config ARCH_MMP
553 bool "Marvell PXA168/910/MMP2"
554 depends on MMU
555 select ARCH_REQUIRE_GPIOLIB
556 select CLKDEV_LOOKUP
557 select GENERIC_ALLOCATOR
558 select GENERIC_CLOCKEVENTS
559 select GPIO_PXA
560 select IRQ_DOMAIN
561 select MULTI_IRQ_HANDLER
562 select NEED_MACH_GPIO_H
563 select PINCTRL
564 select PLAT_PXA
565 select SPARSE_IRQ
566 help
567 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
569 config ARCH_KS8695
570 bool "Micrel/Kendin KS8695"
571 select ARCH_REQUIRE_GPIOLIB
572 select CLKSRC_MMIO
573 select CPU_ARM922T
574 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_MEMORY_H
576 help
577 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
578 System-on-Chip devices.
580 config ARCH_W90X900
581 bool "Nuvoton W90X900 CPU"
582 select ARCH_REQUIRE_GPIOLIB
583 select CLKDEV_LOOKUP
584 select CLKSRC_MMIO
585 select CPU_ARM926T
586 select GENERIC_CLOCKEVENTS
587 help
588 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
589 At present, the w90x900 has been renamed nuc900, regarding
590 the ARM series product line, you can login the following
591 link address to know more.
593 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
594 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 config ARCH_LPC32XX
597 bool "NXP LPC32XX"
598 select ARCH_REQUIRE_GPIOLIB
599 select ARM_AMBA
600 select CLKDEV_LOOKUP
601 select CLKSRC_MMIO
602 select CPU_ARM926T
603 select GENERIC_CLOCKEVENTS
604 select HAVE_IDE
605 select HAVE_PWM
606 select USB_ARCH_HAS_OHCI
607 select USE_OF
608 help
609 Support for the NXP LPC32XX family of processors
611 config ARCH_PXA
612 bool "PXA2xx/PXA3xx-based"
613 depends on MMU
614 select ARCH_HAS_CPUFREQ
615 select ARCH_MTD_XIP
616 select ARCH_REQUIRE_GPIOLIB
617 select ARM_CPU_SUSPEND if PM
618 select AUTO_ZRELADDR
619 select CLKDEV_LOOKUP
620 select CLKSRC_MMIO
621 select GENERIC_CLOCKEVENTS
622 select GPIO_PXA
623 select HAVE_IDE
624 select MULTI_IRQ_HANDLER
625 select NEED_MACH_GPIO_H
626 select PLAT_PXA
627 select SPARSE_IRQ
628 help
629 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
631 config ARCH_MSM
632 bool "Qualcomm MSM"
633 select ARCH_REQUIRE_GPIOLIB
634 select CLKDEV_LOOKUP
635 select CLKSRC_OF if OF
636 select COMMON_CLK
637 select GENERIC_CLOCKEVENTS
638 help
639 Support for Qualcomm MSM/QSD based systems. This runs on the
640 apps processor of the MSM/QSD and depends on a shared memory
641 interface to the modem processor which runs the baseband
642 stack and controls some vital subsystems
643 (clock and power control, etc).
645 config ARCH_SHMOBILE
646 bool "Renesas SH-Mobile / R-Mobile"
647 select ARM_PATCH_PHYS_VIRT
648 select CLKDEV_LOOKUP
649 select GENERIC_CLOCKEVENTS
650 select HAVE_ARM_SCU if SMP
651 select HAVE_ARM_TWD if SMP
652 select HAVE_CLK
653 select HAVE_MACH_CLKDEV
654 select HAVE_SMP
655 select MIGHT_HAVE_CACHE_L2X0
656 select MULTI_IRQ_HANDLER
657 select NO_IOPORT
658 select PINCTRL
659 select PM_GENERIC_DOMAINS if PM
660 select SPARSE_IRQ
661 help
662 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
664 config ARCH_RPC
665 bool "RiscPC"
666 select ARCH_ACORN
667 select ARCH_MAY_HAVE_PC_FDC
668 select ARCH_SPARSEMEM_ENABLE
669 select ARCH_USES_GETTIMEOFFSET
670 select FIQ
671 select HAVE_IDE
672 select HAVE_PATA_PLATFORM
673 select ISA_DMA_API
674 select NEED_MACH_IO_H
675 select NEED_MACH_MEMORY_H
676 select NO_IOPORT
677 select VIRT_TO_BUS
678 help
679 On the Acorn Risc-PC, Linux can support the internal IDE disk and
680 CD-ROM interface, serial and parallel port, and the floppy drive.
682 config ARCH_SA1100
683 bool "SA1100-based"
684 select ARCH_HAS_CPUFREQ
685 select ARCH_MTD_XIP
686 select ARCH_REQUIRE_GPIOLIB
687 select ARCH_SPARSEMEM_ENABLE
688 select CLKDEV_LOOKUP
689 select CLKSRC_MMIO
690 select CPU_FREQ
691 select CPU_SA1100
692 select GENERIC_CLOCKEVENTS
693 select HAVE_IDE
694 select ISA
695 select NEED_MACH_GPIO_H
696 select NEED_MACH_MEMORY_H
697 select SPARSE_IRQ
698 help
699 Support for StrongARM 11x0 based boards.
701 config ARCH_S3C24XX
702 bool "Samsung S3C24XX SoCs"
703 select ARCH_HAS_CPUFREQ
704 select ARCH_REQUIRE_GPIOLIB
705 select CLKDEV_LOOKUP
706 select CLKSRC_SAMSUNG_PWM
707 select GENERIC_CLOCKEVENTS
708 select GPIO_SAMSUNG
709 select HAVE_CLK
710 select HAVE_S3C2410_I2C if I2C
711 select HAVE_S3C2410_WATCHDOG if WATCHDOG
712 select HAVE_S3C_RTC if RTC_CLASS
713 select MULTI_IRQ_HANDLER
714 select NEED_MACH_GPIO_H
715 select NEED_MACH_IO_H
716 select SAMSUNG_ATAGS
717 help
718 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
719 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
720 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
721 Samsung SMDK2410 development board (and derivatives).
723 config ARCH_S3C64XX
724 bool "Samsung S3C64XX"
725 select ARCH_HAS_CPUFREQ
726 select ARCH_REQUIRE_GPIOLIB
727 select ARM_VIC
728 select CLKDEV_LOOKUP
729 select CLKSRC_SAMSUNG_PWM
730 select CPU_V6
731 select GENERIC_CLOCKEVENTS
732 select GPIO_SAMSUNG
733 select HAVE_CLK
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C2410_WATCHDOG if WATCHDOG
736 select HAVE_TCM
737 select NEED_MACH_GPIO_H
738 select NO_IOPORT
739 select PLAT_SAMSUNG
740 select S3C_DEV_NAND
741 select S3C_GPIO_TRACK
742 select SAMSUNG_ATAGS
743 select SAMSUNG_CLKSRC
744 select SAMSUNG_GPIOLIB_4BIT
745 select SAMSUNG_WDT_RESET
746 select USB_ARCH_HAS_OHCI
747 help
748 Samsung S3C64XX series based systems
750 config ARCH_S5P64X0
751 bool "Samsung S5P6440 S5P6450"
752 select CLKDEV_LOOKUP
753 select CLKSRC_SAMSUNG_PWM
754 select CPU_V6
755 select GENERIC_CLOCKEVENTS
756 select GPIO_SAMSUNG
757 select HAVE_CLK
758 select HAVE_S3C2410_I2C if I2C
759 select HAVE_S3C2410_WATCHDOG if WATCHDOG
760 select HAVE_S3C_RTC if RTC_CLASS
761 select NEED_MACH_GPIO_H
762 select SAMSUNG_ATAGS
763 select SAMSUNG_WDT_RESET
764 help
765 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
766 SMDK6450.
768 config ARCH_S5PC100
769 bool "Samsung S5PC100"
770 select ARCH_REQUIRE_GPIOLIB
771 select CLKDEV_LOOKUP
772 select CLKSRC_SAMSUNG_PWM
773 select CPU_V7
774 select GENERIC_CLOCKEVENTS
775 select GPIO_SAMSUNG
776 select HAVE_CLK
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
781 select SAMSUNG_ATAGS
782 select SAMSUNG_WDT_RESET
783 help
784 Samsung S5PC100 series based systems
786 config ARCH_S5PV210
787 bool "Samsung S5PV210/S5PC110"
788 select ARCH_HAS_CPUFREQ
789 select ARCH_HAS_HOLES_MEMORYMODEL
790 select ARCH_SPARSEMEM_ENABLE
791 select CLKDEV_LOOKUP
792 select CLKSRC_SAMSUNG_PWM
793 select CPU_V7
794 select GENERIC_CLOCKEVENTS
795 select GPIO_SAMSUNG
796 select HAVE_CLK
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select HAVE_S3C_RTC if RTC_CLASS
800 select NEED_MACH_GPIO_H
801 select NEED_MACH_MEMORY_H
802 select SAMSUNG_ATAGS
803 help
804 Samsung S5PV210/S5PC110 series based systems
806 config ARCH_EXYNOS
807 bool "Samsung EXYNOS"
808 select ARCH_HAS_CPUFREQ
809 select ARCH_HAS_HOLES_MEMORYMODEL
810 select ARCH_REQUIRE_GPIOLIB
811 select ARCH_SPARSEMEM_ENABLE
812 select ARM_GIC
813 select CLKDEV_LOOKUP
814 select COMMON_CLK
815 select CPU_V7
816 select GENERIC_CLOCKEVENTS
817 select HAVE_CLK
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select HAVE_S3C_RTC if RTC_CLASS
821 select NEED_MACH_MEMORY_H
822 select SPARSE_IRQ
823 select USE_OF
824 help
825 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
827 config ARCH_SHARK
828 bool "Shark"
829 select ARCH_USES_GETTIMEOFFSET
830 select CPU_SA110
831 select ISA
832 select ISA_DMA
833 select NEED_MACH_MEMORY_H
834 select PCI
835 select VIRT_TO_BUS
836 select ZONE_DMA
837 help
838 Support for the StrongARM based Digital DNARD machine, also known
839 as "Shark" (<http://www.shark-linux.de/shark.html>).
841 config ARCH_DAVINCI
842 bool "TI DaVinci"
843 select ARCH_HAS_HOLES_MEMORYMODEL
844 select ARCH_REQUIRE_GPIOLIB
845 select CLKDEV_LOOKUP
846 select GENERIC_ALLOCATOR
847 select GENERIC_CLOCKEVENTS
848 select GENERIC_IRQ_CHIP
849 select HAVE_IDE
850 select TI_PRIV_EDMA
851 select USE_OF
852 select ZONE_DMA
853 help
854 Support for TI's DaVinci platform.
856 config ARCH_OMAP1
857 bool "TI OMAP1"
858 depends on MMU
859 select ARCH_HAS_CPUFREQ
860 select ARCH_HAS_HOLES_MEMORYMODEL
861 select ARCH_OMAP
862 select ARCH_REQUIRE_GPIOLIB
863 select CLKDEV_LOOKUP
864 select CLKSRC_MMIO
865 select GENERIC_CLOCKEVENTS
866 select GENERIC_IRQ_CHIP
867 select HAVE_CLK
868 select HAVE_IDE
869 select IRQ_DOMAIN
870 select NEED_MACH_IO_H if PCCARD
871 select NEED_MACH_MEMORY_H
872 help
873 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
875 endchoice
877 menu "Multiple platform selection"
878 depends on ARCH_MULTIPLATFORM
880 comment "CPU Core family selection"
882 config ARCH_MULTI_V4T
883 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
884 depends on !ARCH_MULTI_V6_V7
885 select ARCH_MULTI_V4_V5
886 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
887 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
888 CPU_ARM925T || CPU_ARM940T)
890 config ARCH_MULTI_V5
891 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
892 depends on !ARCH_MULTI_V6_V7
893 select ARCH_MULTI_V4_V5
894 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
895 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
896 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
898 config ARCH_MULTI_V4_V5
899 bool
901 config ARCH_MULTI_V6
902 bool "ARMv6 based platforms (ARM11)"
903 select ARCH_MULTI_V6_V7
904 select CPU_V6
906 config ARCH_MULTI_V7
907 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
908 default y
909 select ARCH_MULTI_V6_V7
910 select CPU_V7
912 config ARCH_MULTI_V6_V7
913 bool
915 config ARCH_MULTI_CPU_AUTO
916 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
917 select ARCH_MULTI_V5
919 endmenu
921 #
922 # This is sorted alphabetically by mach-* pathname. However, plat-*
923 # Kconfigs may be included either alphabetically (according to the
924 # plat- suffix) or along side the corresponding mach-* source.
925 #
926 source "arch/arm/mach-mvebu/Kconfig"
928 source "arch/arm/mach-at91/Kconfig"
930 source "arch/arm/mach-bcm/Kconfig"
932 source "arch/arm/mach-bcm2835/Kconfig"
934 source "arch/arm/mach-clps711x/Kconfig"
936 source "arch/arm/mach-cns3xxx/Kconfig"
938 source "arch/arm/mach-davinci/Kconfig"
940 source "arch/arm/mach-dove/Kconfig"
942 source "arch/arm/mach-ep93xx/Kconfig"
944 source "arch/arm/mach-footbridge/Kconfig"
946 source "arch/arm/mach-gemini/Kconfig"
948 source "arch/arm/mach-highbank/Kconfig"
950 source "arch/arm/mach-integrator/Kconfig"
952 source "arch/arm/mach-iop32x/Kconfig"
954 source "arch/arm/mach-iop33x/Kconfig"
956 source "arch/arm/mach-iop13xx/Kconfig"
958 source "arch/arm/mach-ixp4xx/Kconfig"
960 source "arch/arm/mach-keystone/Kconfig"
962 source "arch/arm/mach-kirkwood/Kconfig"
964 source "arch/arm/mach-ks8695/Kconfig"
966 source "arch/arm/mach-msm/Kconfig"
968 source "arch/arm/mach-mv78xx0/Kconfig"
970 source "arch/arm/mach-imx/Kconfig"
972 source "arch/arm/mach-mxs/Kconfig"
974 source "arch/arm/mach-netx/Kconfig"
976 source "arch/arm/mach-nomadik/Kconfig"
978 source "arch/arm/mach-nspire/Kconfig"
980 source "arch/arm/plat-omap/Kconfig"
982 source "arch/arm/mach-omap1/Kconfig"
984 source "arch/arm/mach-omap2/Kconfig"
986 source "arch/arm/mach-orion5x/Kconfig"
988 source "arch/arm/mach-picoxcell/Kconfig"
990 source "arch/arm/mach-pxa/Kconfig"
991 source "arch/arm/plat-pxa/Kconfig"
993 source "arch/arm/mach-mmp/Kconfig"
995 source "arch/arm/mach-realview/Kconfig"
997 source "arch/arm/mach-rockchip/Kconfig"
999 source "arch/arm/mach-sa1100/Kconfig"
1001 source "arch/arm/plat-samsung/Kconfig"
1003 source "arch/arm/mach-socfpga/Kconfig"
1005 source "arch/arm/mach-spear/Kconfig"
1007 source "arch/arm/mach-sti/Kconfig"
1009 source "arch/arm/mach-s3c24xx/Kconfig"
1011 if ARCH_S3C64XX
1012 source "arch/arm/mach-s3c64xx/Kconfig"
1013 endif
1015 source "arch/arm/mach-s5p64x0/Kconfig"
1017 source "arch/arm/mach-s5pc100/Kconfig"
1019 source "arch/arm/mach-s5pv210/Kconfig"
1021 source "arch/arm/mach-exynos/Kconfig"
1023 source "arch/arm/mach-shmobile/Kconfig"
1025 source "arch/arm/mach-sunxi/Kconfig"
1027 source "arch/arm/mach-prima2/Kconfig"
1029 source "arch/arm/mach-tegra/Kconfig"
1031 source "arch/arm/mach-u300/Kconfig"
1033 source "arch/arm/mach-ux500/Kconfig"
1035 source "arch/arm/mach-versatile/Kconfig"
1037 source "arch/arm/mach-vexpress/Kconfig"
1038 source "arch/arm/plat-versatile/Kconfig"
1040 source "arch/arm/mach-virt/Kconfig"
1042 source "arch/arm/mach-vt8500/Kconfig"
1044 source "arch/arm/mach-w90x900/Kconfig"
1046 source "arch/arm/mach-zynq/Kconfig"
1048 # Definitions to make life easier
1049 config ARCH_ACORN
1050 bool
1052 config PLAT_IOP
1053 bool
1054 select GENERIC_CLOCKEVENTS
1056 config PLAT_ORION
1057 bool
1058 select CLKSRC_MMIO
1059 select COMMON_CLK
1060 select GENERIC_IRQ_CHIP
1061 select IRQ_DOMAIN
1063 config PLAT_ORION_LEGACY
1064 bool
1065 select PLAT_ORION
1067 config PLAT_PXA
1068 bool
1070 config PLAT_VERSATILE
1071 bool
1073 config ARM_TIMER_SP804
1074 bool
1075 select CLKSRC_MMIO
1076 select CLKSRC_OF if OF
1078 source arch/arm/mm/Kconfig
1080 config ARM_NR_BANKS
1081 int
1082 default 16 if ARCH_EP93XX
1083 default 8
1085 config IWMMXT
1086 bool "Enable iWMMXt support" if !CPU_PJ4
1087 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1088 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1089 help
1090 Enable support for iWMMXt context switching at run time if
1091 running on a CPU that supports it.
1093 config XSCALE_PMU
1094 bool
1095 depends on CPU_XSCALE
1096 default y
1098 config MULTI_IRQ_HANDLER
1099 bool
1100 help
1101 Allow each machine to specify it's own IRQ handler at run time.
1103 if !MMU
1104 source "arch/arm/Kconfig-nommu"
1105 endif
1107 config PJ4B_ERRATA_4742
1108 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1109 depends on CPU_PJ4B && MACH_ARMADA_370
1110 default y
1111 help
1112 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1113 Event (WFE) IDLE states, a specific timing sensitivity exists between
1114 the retiring WFI/WFE instructions and the newly issued subsequent
1115 instructions. This sensitivity can result in a CPU hang scenario.
1116 Workaround:
1117 The software must insert either a Data Synchronization Barrier (DSB)
1118 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1119 instruction
1121 config ARM_ERRATA_326103
1122 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1123 depends on CPU_V6
1124 help
1125 Executing a SWP instruction to read-only memory does not set bit 11
1126 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1127 treat the access as a read, preventing a COW from occurring and
1128 causing the faulting task to livelock.
1130 config ARM_ERRATA_411920
1131 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1132 depends on CPU_V6 || CPU_V6K
1133 help
1134 Invalidation of the Instruction Cache operation can
1135 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1136 It does not affect the MPCore. This option enables the ARM Ltd.
1137 recommended workaround.
1139 config ARM_ERRATA_430973
1140 bool "ARM errata: Stale prediction on replaced interworking branch"
1141 depends on CPU_V7
1142 help
1143 This option enables the workaround for the 430973 Cortex-A8
1144 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1145 interworking branch is replaced with another code sequence at the
1146 same virtual address, whether due to self-modifying code or virtual
1147 to physical address re-mapping, Cortex-A8 does not recover from the
1148 stale interworking branch prediction. This results in Cortex-A8
1149 executing the new code sequence in the incorrect ARM or Thumb state.
1150 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1151 and also flushes the branch target cache at every context switch.
1152 Note that setting specific bits in the ACTLR register may not be
1153 available in non-secure mode.
1155 config ARM_ERRATA_458693
1156 bool "ARM errata: Processor deadlock when a false hazard is created"
1157 depends on CPU_V7
1158 depends on !ARCH_MULTIPLATFORM
1159 help
1160 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1161 erratum. For very specific sequences of memory operations, it is
1162 possible for a hazard condition intended for a cache line to instead
1163 be incorrectly associated with a different cache line. This false
1164 hazard might then cause a processor deadlock. The workaround enables
1165 the L1 caching of the NEON accesses and disables the PLD instruction
1166 in the ACTLR register. Note that setting specific bits in the ACTLR
1167 register may not be available in non-secure mode.
1169 config ARM_ERRATA_460075
1170 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1171 depends on CPU_V7
1172 depends on !ARCH_MULTIPLATFORM
1173 help
1174 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1175 erratum. Any asynchronous access to the L2 cache may encounter a
1176 situation in which recent store transactions to the L2 cache are lost
1177 and overwritten with stale memory contents from external memory. The
1178 workaround disables the write-allocate mode for the L2 cache via the
1179 ACTLR register. Note that setting specific bits in the ACTLR register
1180 may not be available in non-secure mode.
1182 config ARM_ERRATA_742230
1183 bool "ARM errata: DMB operation may be faulty"
1184 depends on CPU_V7 && SMP
1185 depends on !ARCH_MULTIPLATFORM
1186 help
1187 This option enables the workaround for the 742230 Cortex-A9
1188 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1189 between two write operations may not ensure the correct visibility
1190 ordering of the two writes. This workaround sets a specific bit in
1191 the diagnostic register of the Cortex-A9 which causes the DMB
1192 instruction to behave as a DSB, ensuring the correct behaviour of
1193 the two writes.
1195 config ARM_ERRATA_742231
1196 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1197 depends on CPU_V7 && SMP
1198 depends on !ARCH_MULTIPLATFORM
1199 help
1200 This option enables the workaround for the 742231 Cortex-A9
1201 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1202 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1203 accessing some data located in the same cache line, may get corrupted
1204 data due to bad handling of the address hazard when the line gets
1205 replaced from one of the CPUs at the same time as another CPU is
1206 accessing it. This workaround sets specific bits in the diagnostic
1207 register of the Cortex-A9 which reduces the linefill issuing
1208 capabilities of the processor.
1210 config PL310_ERRATA_588369
1211 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1212 depends on CACHE_L2X0
1213 help
1214 The PL310 L2 cache controller implements three types of Clean &
1215 Invalidate maintenance operations: by Physical Address
1216 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1217 They are architecturally defined to behave as the execution of a
1218 clean operation followed immediately by an invalidate operation,
1219 both performing to the same memory location. This functionality
1220 is not correctly implemented in PL310 as clean lines are not
1221 invalidated as a result of these operations.
1223 config ARM_ERRATA_643719
1224 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1225 depends on CPU_V7 && SMP
1226 help
1227 This option enables the workaround for the 643719 Cortex-A9 (prior to
1228 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1229 register returns zero when it should return one. The workaround
1230 corrects this value, ensuring cache maintenance operations which use
1231 it behave as intended and avoiding data corruption.
1233 config ARM_ERRATA_720789
1234 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1235 depends on CPU_V7
1236 help
1237 This option enables the workaround for the 720789 Cortex-A9 (prior to
1238 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1239 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1240 As a consequence of this erratum, some TLB entries which should be
1241 invalidated are not, resulting in an incoherency in the system page
1242 tables. The workaround changes the TLB flushing routines to invalidate
1243 entries regardless of the ASID.
1245 config PL310_ERRATA_727915
1246 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1247 depends on CACHE_L2X0
1248 help
1249 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1250 operation (offset 0x7FC). This operation runs in background so that
1251 PL310 can handle normal accesses while it is in progress. Under very
1252 rare circumstances, due to this erratum, write data can be lost when
1253 PL310 treats a cacheable write transaction during a Clean &
1254 Invalidate by Way operation.
1256 config ARM_ERRATA_743622
1257 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1258 depends on CPU_V7
1259 depends on !ARCH_MULTIPLATFORM
1260 help
1261 This option enables the workaround for the 743622 Cortex-A9
1262 (r2p*) erratum. Under very rare conditions, a faulty
1263 optimisation in the Cortex-A9 Store Buffer may lead to data
1264 corruption. This workaround sets a specific bit in the diagnostic
1265 register of the Cortex-A9 which disables the Store Buffer
1266 optimisation, preventing the defect from occurring. This has no
1267 visible impact on the overall performance or power consumption of the
1268 processor.
1270 config ARM_ERRATA_751472
1271 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1272 depends on CPU_V7
1273 depends on !ARCH_MULTIPLATFORM
1274 help
1275 This option enables the workaround for the 751472 Cortex-A9 (prior
1276 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1277 completion of a following broadcasted operation if the second
1278 operation is received by a CPU before the ICIALLUIS has completed,
1279 potentially leading to corrupted entries in the cache or TLB.
1281 config PL310_ERRATA_753970
1282 bool "PL310 errata: cache sync operation may be faulty"
1283 depends on CACHE_PL310
1284 help
1285 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1287 Under some condition the effect of cache sync operation on
1288 the store buffer still remains when the operation completes.
1289 This means that the store buffer is always asked to drain and
1290 this prevents it from merging any further writes. The workaround
1291 is to replace the normal offset of cache sync operation (0x730)
1292 by another offset targeting an unmapped PL310 register 0x740.
1293 This has the same effect as the cache sync operation: store buffer
1294 drain and waiting for all buffers empty.
1296 config ARM_ERRATA_754322
1297 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1298 depends on CPU_V7
1299 help
1300 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1301 r3p*) erratum. A speculative memory access may cause a page table walk
1302 which starts prior to an ASID switch but completes afterwards. This
1303 can populate the micro-TLB with a stale entry which may be hit with
1304 the new ASID. This workaround places two dsb instructions in the mm
1305 switching code so that no page table walks can cross the ASID switch.
1307 config ARM_ERRATA_754327
1308 bool "ARM errata: no automatic Store Buffer drain"
1309 depends on CPU_V7 && SMP
1310 help
1311 This option enables the workaround for the 754327 Cortex-A9 (prior to
1312 r2p0) erratum. The Store Buffer does not have any automatic draining
1313 mechanism and therefore a livelock may occur if an external agent
1314 continuously polls a memory location waiting to observe an update.
1315 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1316 written polling loops from denying visibility of updates to memory.
1318 config ARM_ERRATA_364296
1319 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1320 depends on CPU_V6
1321 help
1322 This options enables the workaround for the 364296 ARM1136
1323 r0p2 erratum (possible cache data corruption with
1324 hit-under-miss enabled). It sets the undocumented bit 31 in
1325 the auxiliary control register and the FI bit in the control
1326 register, thus disabling hit-under-miss without putting the
1327 processor into full low interrupt latency mode. ARM11MPCore
1328 is not affected.
1330 config ARM_ERRATA_764369
1331 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1332 depends on CPU_V7 && SMP
1333 help
1334 This option enables the workaround for erratum 764369
1335 affecting Cortex-A9 MPCore with two or more processors (all
1336 current revisions). Under certain timing circumstances, a data
1337 cache line maintenance operation by MVA targeting an Inner
1338 Shareable memory region may fail to proceed up to either the
1339 Point of Coherency or to the Point of Unification of the
1340 system. This workaround adds a DSB instruction before the
1341 relevant cache maintenance functions and sets a specific bit
1342 in the diagnostic control register of the SCU.
1344 config PL310_ERRATA_769419
1345 bool "PL310 errata: no automatic Store Buffer drain"
1346 depends on CACHE_L2X0
1347 help
1348 On revisions of the PL310 prior to r3p2, the Store Buffer does
1349 not automatically drain. This can cause normal, non-cacheable
1350 writes to be retained when the memory system is idle, leading
1351 to suboptimal I/O performance for drivers using coherent DMA.
1352 This option adds a write barrier to the cpu_idle loop so that,
1353 on systems with an outer cache, the store buffer is drained
1354 explicitly.
1356 config ARM_ERRATA_775420
1357 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1358 depends on CPU_V7
1359 help
1360 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1361 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1362 operation aborts with MMU exception, it might cause the processor
1363 to deadlock. This workaround puts DSB before executing ISB if
1364 an abort may occur on cache maintenance.
1366 config ARM_ERRATA_798181
1367 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1368 depends on CPU_V7 && SMP
1369 help
1370 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1371 adequately shooting down all use of the old entries. This
1372 option enables the Linux kernel workaround for this erratum
1373 which sends an IPI to the CPUs that are running the same ASID
1374 as the one being invalidated.
1376 config ARM_ERRATA_773022
1377 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1378 depends on CPU_V7
1379 help
1380 This option enables the workaround for the 773022 Cortex-A15
1381 (up to r0p4) erratum. In certain rare sequences of code, the
1382 loop buffer may deliver incorrect instructions. This
1383 workaround disables the loop buffer to avoid the erratum.
1385 endmenu
1387 source "arch/arm/common/Kconfig"
1389 menu "Bus support"
1391 config ARM_AMBA
1392 bool
1394 config ISA
1395 bool
1396 help
1397 Find out whether you have ISA slots on your motherboard. ISA is the
1398 name of a bus system, i.e. the way the CPU talks to the other stuff
1399 inside your box. Other bus systems are PCI, EISA, MicroChannel
1400 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1401 newer boards don't support it. If you have ISA, say Y, otherwise N.
1403 # Select ISA DMA controller support
1404 config ISA_DMA
1405 bool
1406 select ISA_DMA_API
1408 # Select ISA DMA interface
1409 config ISA_DMA_API
1410 bool
1412 config PCI
1413 bool "PCI support" if MIGHT_HAVE_PCI
1414 help
1415 Find out whether you have a PCI motherboard. PCI is the name of a
1416 bus system, i.e. the way the CPU talks to the other stuff inside
1417 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1418 VESA. If you have PCI, say Y, otherwise N.
1420 config PCI_DOMAINS
1421 bool
1422 depends on PCI
1424 config PCI_NANOENGINE
1425 bool "BSE nanoEngine PCI support"
1426 depends on SA1100_NANOENGINE
1427 help
1428 Enable PCI on the BSE nanoEngine board.
1430 config PCI_SYSCALL
1431 def_bool PCI
1433 # Select the host bridge type
1434 config PCI_HOST_VIA82C505
1435 bool
1436 depends on PCI && ARCH_SHARK
1437 default y
1439 config PCI_HOST_ITE8152
1440 bool
1441 depends on PCI && MACH_ARMCORE
1442 default y
1443 select DMABOUNCE
1445 source "drivers/pci/Kconfig"
1446 source "drivers/pci/pcie/Kconfig"
1448 source "drivers/pcmcia/Kconfig"
1450 endmenu
1452 menu "Kernel Features"
1454 config HAVE_SMP
1455 bool
1456 help
1457 This option should be selected by machines which have an SMP-
1458 capable CPU.
1460 The only effect of this option is to make the SMP-related
1461 options available to the user for configuration.
1463 config SMP
1464 bool "Symmetric Multi-Processing"
1465 depends on CPU_V6K || CPU_V7
1466 depends on GENERIC_CLOCKEVENTS
1467 depends on HAVE_SMP
1468 depends on MMU || ARM_MPU
1469 select USE_GENERIC_SMP_HELPERS
1470 help
1471 This enables support for systems with more than one CPU. If you have
1472 a system with only one CPU, like most personal computers, say N. If
1473 you have a system with more than one CPU, say Y.
1475 If you say N here, the kernel will run on single and multiprocessor
1476 machines, but will use only one CPU of a multiprocessor machine. If
1477 you say Y here, the kernel will run on many, but not all, single
1478 processor machines. On a single processor machine, the kernel will
1479 run faster if you say N here.
1481 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1482 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1483 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1485 If you don't know what to do here, say N.
1487 config SMP_ON_UP
1488 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1489 depends on SMP && !XIP_KERNEL && MMU
1490 default y
1491 help
1492 SMP kernels contain instructions which fail on non-SMP processors.
1493 Enabling this option allows the kernel to modify itself to make
1494 these instructions safe. Disabling it allows about 1K of space
1495 savings.
1497 If you don't know what to do here, say Y.
1499 config ARM_CPU_TOPOLOGY
1500 bool "Support cpu topology definition"
1501 depends on SMP && CPU_V7
1502 default y
1503 help
1504 Support ARM cpu topology definition. The MPIDR register defines
1505 affinity between processors which is then used to describe the cpu
1506 topology of an ARM System.
1508 config SCHED_MC
1509 bool "Multi-core scheduler support"
1510 depends on ARM_CPU_TOPOLOGY
1511 help
1512 Multi-core scheduler support improves the CPU scheduler's decision
1513 making when dealing with multi-core CPU chips at a cost of slightly
1514 increased overhead in some places. If unsure say N here.
1516 config SCHED_SMT
1517 bool "SMT scheduler support"
1518 depends on ARM_CPU_TOPOLOGY
1519 help
1520 Improves the CPU scheduler's decision making when dealing with
1521 MultiThreading at a cost of slightly increased overhead in some
1522 places. If unsure say N here.
1524 config HAVE_ARM_SCU
1525 bool
1526 help
1527 This option enables support for the ARM system coherency unit
1529 config HAVE_ARM_ARCH_TIMER
1530 bool "Architected timer support"
1531 depends on CPU_V7
1532 select ARM_ARCH_TIMER
1533 help
1534 This option enables support for the ARM architected timer
1536 config HAVE_ARM_TWD
1537 bool
1538 depends on SMP
1539 select CLKSRC_OF if OF
1540 help
1541 This options enables support for the ARM timer and watchdog unit
1543 config MCPM
1544 bool "Multi-Cluster Power Management"
1545 depends on CPU_V7 && SMP
1546 help
1547 This option provides the common power management infrastructure
1548 for (multi-)cluster based systems, such as big.LITTLE based
1549 systems.
1551 choice
1552 prompt "Memory split"
1553 default VMSPLIT_3G
1554 help
1555 Select the desired split between kernel and user memory.
1557 If you are not absolutely sure what you are doing, leave this
1558 option alone!
1560 config VMSPLIT_3G
1561 bool "3G/1G user/kernel split"
1562 config VMSPLIT_2G
1563 bool "2G/2G user/kernel split"
1564 config VMSPLIT_1G
1565 bool "1G/3G user/kernel split"
1566 endchoice
1568 config PAGE_OFFSET
1569 hex
1570 default 0x40000000 if VMSPLIT_1G
1571 default 0x80000000 if VMSPLIT_2G
1572 default 0xC0000000
1574 config NR_CPUS
1575 int "Maximum number of CPUs (2-32)"
1576 range 2 32
1577 depends on SMP
1578 default "4"
1580 config HOTPLUG_CPU
1581 bool "Support for hot-pluggable CPUs"
1582 depends on SMP
1583 help
1584 Say Y here to experiment with turning CPUs off and on. CPUs
1585 can be controlled through /sys/devices/system/cpu.
1587 config ARM_PSCI
1588 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1589 depends on CPU_V7
1590 help
1591 Say Y here if you want Linux to communicate with system firmware
1592 implementing the PSCI specification for CPU-centric power
1593 management operations described in ARM document number ARM DEN
1594 0022A ("Power State Coordination Interface System Software on
1595 ARM processors").
1597 # The GPIO number here must be sorted by descending number. In case of
1598 # a multiplatform kernel, we just want the highest value required by the
1599 # selected platforms.
1600 config ARCH_NR_GPIO
1601 int
1602 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1603 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1604 default 392 if ARCH_U8500
1605 default 352 if ARCH_VT8500
1606 default 288 if ARCH_SUNXI
1607 default 264 if MACH_H4700
1608 default 0
1609 help
1610 Maximum number of GPIOs in the system.
1612 If unsure, leave the default value.
1614 source kernel/Kconfig.preempt
1616 config HZ_FIXED
1617 int
1618 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1619 ARCH_S5PV210 || ARCH_EXYNOS4
1620 default AT91_TIMER_HZ if ARCH_AT91
1621 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1622 default 0
1624 choice
1625 depends on HZ_FIXED = 0
1626 prompt "Timer frequency"
1628 config HZ_100
1629 bool "100 Hz"
1631 config HZ_200
1632 bool "200 Hz"
1634 config HZ_250
1635 bool "250 Hz"
1637 config HZ_300
1638 bool "300 Hz"
1640 config HZ_500
1641 bool "500 Hz"
1643 config HZ_1000
1644 bool "1000 Hz"
1646 endchoice
1648 config HZ
1649 int
1650 default HZ_FIXED if HZ_FIXED != 0
1651 default 100 if HZ_100
1652 default 200 if HZ_200
1653 default 250 if HZ_250
1654 default 300 if HZ_300
1655 default 500 if HZ_500
1656 default 1000
1658 config SCHED_HRTICK
1659 def_bool HIGH_RES_TIMERS
1661 config SCHED_HRTICK
1662 def_bool HIGH_RES_TIMERS
1664 config THUMB2_KERNEL
1665 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1666 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1667 default y if CPU_THUMBONLY
1668 select AEABI
1669 select ARM_ASM_UNIFIED
1670 select ARM_UNWIND
1671 help
1672 By enabling this option, the kernel will be compiled in
1673 Thumb-2 mode. A compiler/assembler that understand the unified
1674 ARM-Thumb syntax is needed.
1676 If unsure, say N.
1678 config THUMB2_AVOID_R_ARM_THM_JUMP11
1679 bool "Work around buggy Thumb-2 short branch relocations in gas"
1680 depends on THUMB2_KERNEL && MODULES
1681 default y
1682 help
1683 Various binutils versions can resolve Thumb-2 branches to
1684 locally-defined, preemptible global symbols as short-range "b.n"
1685 branch instructions.
1687 This is a problem, because there's no guarantee the final
1688 destination of the symbol, or any candidate locations for a
1689 trampoline, are within range of the branch. For this reason, the
1690 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1691 relocation in modules at all, and it makes little sense to add
1692 support.
1694 The symptom is that the kernel fails with an "unsupported
1695 relocation" error when loading some modules.
1697 Until fixed tools are available, passing
1698 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1699 code which hits this problem, at the cost of a bit of extra runtime
1700 stack usage in some cases.
1702 The problem is described in more detail at:
1703 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1705 Only Thumb-2 kernels are affected.
1707 Unless you are sure your tools don't have this problem, say Y.
1709 config ARM_ASM_UNIFIED
1710 bool
1712 config AEABI
1713 bool "Use the ARM EABI to compile the kernel"
1714 help
1715 This option allows for the kernel to be compiled using the latest
1716 ARM ABI (aka EABI). This is only useful if you are using a user
1717 space environment that is also compiled with EABI.
1719 Since there are major incompatibilities between the legacy ABI and
1720 EABI, especially with regard to structure member alignment, this
1721 option also changes the kernel syscall calling convention to
1722 disambiguate both ABIs and allow for backward compatibility support
1723 (selected with CONFIG_OABI_COMPAT).
1725 To use this you need GCC version 4.0.0 or later.
1727 config OABI_COMPAT
1728 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1729 depends on AEABI && !THUMB2_KERNEL
1730 default y
1731 help
1732 This option preserves the old syscall interface along with the
1733 new (ARM EABI) one. It also provides a compatibility layer to
1734 intercept syscalls that have structure arguments which layout
1735 in memory differs between the legacy ABI and the new ARM EABI
1736 (only for non "thumb" binaries). This option adds a tiny
1737 overhead to all syscalls and produces a slightly larger kernel.
1738 If you know you'll be using only pure EABI user space then you
1739 can say N here. If this option is not selected and you attempt
1740 to execute a legacy ABI binary then the result will be
1741 UNPREDICTABLE (in fact it can be predicted that it won't work
1742 at all). If in doubt say Y.
1744 config ARCH_HAS_HOLES_MEMORYMODEL
1745 bool
1747 config ARCH_SPARSEMEM_ENABLE
1748 bool
1750 config ARCH_SPARSEMEM_DEFAULT
1751 def_bool ARCH_SPARSEMEM_ENABLE
1753 config ARCH_SELECT_MEMORY_MODEL
1754 def_bool ARCH_SPARSEMEM_ENABLE
1756 config HAVE_ARCH_PFN_VALID
1757 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1759 config HIGHMEM
1760 bool "High Memory Support"
1761 depends on MMU
1762 help
1763 The address space of ARM processors is only 4 Gigabytes large
1764 and it has to accommodate user address space, kernel address
1765 space as well as some memory mapped IO. That means that, if you
1766 have a large amount of physical memory and/or IO, not all of the
1767 memory can be "permanently mapped" by the kernel. The physical
1768 memory that is not permanently mapped is called "high memory".
1770 Depending on the selected kernel/user memory split, minimum
1771 vmalloc space and actual amount of RAM, you may not need this
1772 option which should result in a slightly faster kernel.
1774 If unsure, say n.
1776 config HIGHPTE
1777 bool "Allocate 2nd-level pagetables from highmem"
1778 depends on HIGHMEM
1780 config HW_PERF_EVENTS
1781 bool "Enable hardware performance counter support for perf events"
1782 depends on PERF_EVENTS
1783 default y
1784 help
1785 Enable hardware performance counter support for perf events. If
1786 disabled, perf events will use software events only.
1788 config SYS_SUPPORTS_HUGETLBFS
1789 def_bool y
1790 depends on ARM_LPAE
1792 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1793 def_bool y
1794 depends on ARM_LPAE
1796 config ARCH_WANT_GENERAL_HUGETLB
1797 def_bool y
1799 source "mm/Kconfig"
1801 config FORCE_MAX_ZONEORDER
1802 int "Maximum zone order" if ARCH_SHMOBILE
1803 range 11 64 if ARCH_SHMOBILE
1804 default "12" if SOC_AM33XX
1805 default "9" if SA1111
1806 default "11"
1807 help
1808 The kernel memory allocator divides physically contiguous memory
1809 blocks into "zones", where each zone is a power of two number of
1810 pages. This option selects the largest power of two that the kernel
1811 keeps in the memory allocator. If you need to allocate very large
1812 blocks of physically contiguous memory, then you may need to
1813 increase this value.
1815 This config option is actually maximum order plus one. For example,
1816 a value of 11 means that the largest free memory block is 2^10 pages.
1818 config ALIGNMENT_TRAP
1819 bool
1820 depends on CPU_CP15_MMU
1821 default y if !ARCH_EBSA110
1822 select HAVE_PROC_CPU if PROC_FS
1823 help
1824 ARM processors cannot fetch/store information which is not
1825 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1826 address divisible by 4. On 32-bit ARM processors, these non-aligned
1827 fetch/store instructions will be emulated in software if you say
1828 here, which has a severe performance impact. This is necessary for
1829 correct operation of some network protocols. With an IP-only
1830 configuration it is safe to say N, otherwise say Y.
1832 config UACCESS_WITH_MEMCPY
1833 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1834 depends on MMU
1835 default y if CPU_FEROCEON
1836 help
1837 Implement faster copy_to_user and clear_user methods for CPU
1838 cores where a 8-word STM instruction give significantly higher
1839 memory write throughput than a sequence of individual 32bit stores.
1841 A possible side effect is a slight increase in scheduling latency
1842 between threads sharing the same address space if they invoke
1843 such copy operations with large buffers.
1845 However, if the CPU data cache is using a write-allocate mode,
1846 this option is unlikely to provide any performance gain.
1848 config SECCOMP
1849 bool
1850 prompt "Enable seccomp to safely compute untrusted bytecode"
1851 ---help---
1852 This kernel feature is useful for number crunching applications
1853 that may need to compute untrusted bytecode during their
1854 execution. By using pipes or other transports made available to
1855 the process as file descriptors supporting the read/write
1856 syscalls, it's possible to isolate those applications in
1857 their own address space using seccomp. Once seccomp is
1858 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1859 and the task is only allowed to execute a few safe syscalls
1860 defined by each seccomp mode.
1862 config CC_STACKPROTECTOR
1863 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1864 help
1865 This option turns on the -fstack-protector GCC feature. This
1866 feature puts, at the beginning of functions, a canary value on
1867 the stack just before the return address, and validates
1868 the value just before actually returning. Stack based buffer
1869 overflows (that need to overwrite this return address) now also
1870 overwrite the canary, which gets detected and the attack is then
1871 neutralized via a kernel panic.
1872 This feature requires gcc version 4.2 or above.
1874 config XEN_DOM0
1875 def_bool y
1876 depends on XEN
1878 config XEN
1879 bool "Xen guest support on ARM (EXPERIMENTAL)"
1880 depends on ARM && AEABI && OF
1881 depends on CPU_V7 && !CPU_V6
1882 depends on !GENERIC_ATOMIC64
1883 select ARM_PSCI
1884 help
1885 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1887 endmenu
1889 menu "Boot options"
1891 config USE_OF
1892 bool "Flattened Device Tree support"
1893 select IRQ_DOMAIN
1894 select OF
1895 select OF_EARLY_FLATTREE
1896 help
1897 Include support for flattened device tree machine descriptions.
1899 config ATAGS
1900 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1901 default y
1902 help
1903 This is the traditional way of passing data to the kernel at boot
1904 time. If you are solely relying on the flattened device tree (or
1905 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1906 to remove ATAGS support from your kernel binary. If unsure,
1907 leave this to y.
1909 config DEPRECATED_PARAM_STRUCT
1910 bool "Provide old way to pass kernel parameters"
1911 depends on ATAGS
1912 help
1913 This was deprecated in 2001 and announced to live on for 5 years.
1914 Some old boot loaders still use this way.
1916 # Compressed boot loader in ROM. Yes, we really want to ask about
1917 # TEXT and BSS so we preserve their values in the config files.
1918 config ZBOOT_ROM_TEXT
1919 hex "Compressed ROM boot loader base address"
1920 default "0"
1921 help
1922 The physical address at which the ROM-able zImage is to be
1923 placed in the target. Platforms which normally make use of
1924 ROM-able zImage formats normally set this to a suitable
1925 value in their defconfig file.
1927 If ZBOOT_ROM is not enabled, this has no effect.
1929 config ZBOOT_ROM_BSS
1930 hex "Compressed ROM boot loader BSS address"
1931 default "0"
1932 help
1933 The base address of an area of read/write memory in the target
1934 for the ROM-able zImage which must be available while the
1935 decompressor is running. It must be large enough to hold the
1936 entire decompressed kernel plus an additional 128 KiB.
1937 Platforms which normally make use of ROM-able zImage formats
1938 normally set this to a suitable value in their defconfig file.
1940 If ZBOOT_ROM is not enabled, this has no effect.
1942 config ZBOOT_ROM
1943 bool "Compressed boot loader in ROM/flash"
1944 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1945 help
1946 Say Y here if you intend to execute your compressed kernel image
1947 (zImage) directly from ROM or flash. If unsure, say N.
1949 choice
1950 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1951 depends on ZBOOT_ROM && ARCH_SH7372
1952 default ZBOOT_ROM_NONE
1953 help
1954 Include experimental SD/MMC loading code in the ROM-able zImage.
1955 With this enabled it is possible to write the ROM-able zImage
1956 kernel image to an MMC or SD card and boot the kernel straight
1957 from the reset vector. At reset the processor Mask ROM will load
1958 the first part of the ROM-able zImage which in turn loads the
1959 rest the kernel image to RAM.
1961 config ZBOOT_ROM_NONE
1962 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1963 help
1964 Do not load image from SD or MMC
1966 config ZBOOT_ROM_MMCIF
1967 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1968 help
1969 Load image from MMCIF hardware block.
1971 config ZBOOT_ROM_SH_MOBILE_SDHI
1972 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1973 help
1974 Load image from SDHI hardware block
1976 endchoice
1978 config ARM_APPENDED_DTB
1979 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1980 depends on OF && !ZBOOT_ROM
1981 help
1982 With this option, the boot code will look for a device tree binary
1983 (DTB) appended to zImage
1984 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1986 This is meant as a backward compatibility convenience for those
1987 systems with a bootloader that can't be upgraded to accommodate
1988 the documented boot protocol using a device tree.
1990 Beware that there is very little in terms of protection against
1991 this option being confused by leftover garbage in memory that might
1992 look like a DTB header after a reboot if no actual DTB is appended
1993 to zImage. Do not leave this option active in a production kernel
1994 if you don't intend to always append a DTB. Proper passing of the
1995 location into r2 of a bootloader provided DTB is always preferable
1996 to this option.
1998 config ARM_ATAG_DTB_COMPAT
1999 bool "Supplement the appended DTB with traditional ATAG information"
2000 depends on ARM_APPENDED_DTB
2001 help
2002 Some old bootloaders can't be updated to a DTB capable one, yet
2003 they provide ATAGs with memory configuration, the ramdisk address,
2004 the kernel cmdline string, etc. Such information is dynamically
2005 provided by the bootloader and can't always be stored in a static
2006 DTB. To allow a device tree enabled kernel to be used with such
2007 bootloaders, this option allows zImage to extract the information
2008 from the ATAG list and store it at run time into the appended DTB.
2010 choice
2011 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2012 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2014 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2015 bool "Use bootloader kernel arguments if available"
2016 help
2017 Uses the command-line options passed by the boot loader instead of
2018 the device tree bootargs property. If the boot loader doesn't provide
2019 any, the device tree bootargs property will be used.
2021 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2022 bool "Extend with bootloader kernel arguments"
2023 help
2024 The command-line arguments provided by the boot loader will be
2025 appended to the the device tree bootargs property.
2027 endchoice
2029 config CMDLINE
2030 string "Default kernel command string"
2031 default ""
2032 help
2033 On some architectures (EBSA110 and CATS), there is currently no way
2034 for the boot loader to pass arguments to the kernel. For these
2035 architectures, you should supply some command-line options at build
2036 time by entering them here. As a minimum, you should specify the
2037 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2039 choice
2040 prompt "Kernel command line type" if CMDLINE != ""
2041 default CMDLINE_FROM_BOOTLOADER
2042 depends on ATAGS
2044 config CMDLINE_FROM_BOOTLOADER
2045 bool "Use bootloader kernel arguments if available"
2046 help
2047 Uses the command-line options passed by the boot loader. If
2048 the boot loader doesn't provide any, the default kernel command
2049 string provided in CMDLINE will be used.
2051 config CMDLINE_EXTEND
2052 bool "Extend bootloader kernel arguments"
2053 help
2054 The command-line arguments provided by the boot loader will be
2055 appended to the default kernel command string.
2057 config CMDLINE_FORCE
2058 bool "Always use the default kernel command string"
2059 help
2060 Always use the default kernel command string, even if the boot
2061 loader passes other arguments to the kernel.
2062 This is useful if you cannot or don't want to change the
2063 command-line options your boot loader passes to the kernel.
2064 endchoice
2066 config XIP_KERNEL
2067 bool "Kernel Execute-In-Place from ROM"
2068 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2069 help
2070 Execute-In-Place allows the kernel to run from non-volatile storage
2071 directly addressable by the CPU, such as NOR flash. This saves RAM
2072 space since the text section of the kernel is not loaded from flash
2073 to RAM. Read-write sections, such as the data section and stack,
2074 are still copied to RAM. The XIP kernel is not compressed since
2075 it has to run directly from flash, so it will take more space to
2076 store it. The flash address used to link the kernel object files,
2077 and for storing it, is configuration dependent. Therefore, if you
2078 say Y here, you must know the proper physical address where to
2079 store the kernel image depending on your own flash memory usage.
2081 Also note that the make target becomes "make xipImage" rather than
2082 "make zImage" or "make Image". The final kernel binary to put in
2083 ROM memory will be arch/arm/boot/xipImage.
2085 If unsure, say N.
2087 config XIP_PHYS_ADDR
2088 hex "XIP Kernel Physical Location"
2089 depends on XIP_KERNEL
2090 default "0x00080000"
2091 help
2092 This is the physical address in your flash memory the kernel will
2093 be linked for and stored to. This address is dependent on your
2094 own flash usage.
2096 config KEXEC
2097 bool "Kexec system call (EXPERIMENTAL)"
2098 depends on (!SMP || PM_SLEEP_SMP)
2099 help
2100 kexec is a system call that implements the ability to shutdown your
2101 current kernel, and to start another kernel. It is like a reboot
2102 but it is independent of the system firmware. And like a reboot
2103 you can start any kernel with it, not just Linux.
2105 It is an ongoing process to be certain the hardware in a machine
2106 is properly shutdown, so do not be surprised if this code does not
2107 initially work for you.
2109 config ATAGS_PROC
2110 bool "Export atags in procfs"
2111 depends on ATAGS && KEXEC
2112 default y
2113 help
2114 Should the atags used to boot the kernel be exported in an "atags"
2115 file in procfs. Useful with kexec.
2117 config CRASH_DUMP
2118 bool "Build kdump crash kernel (EXPERIMENTAL)"
2119 help
2120 Generate crash dump after being started by kexec. This should
2121 be normally only set in special crash dump kernels which are
2122 loaded in the main kernel with kexec-tools into a specially
2123 reserved region and then later executed after a crash by
2124 kdump/kexec. The crash dump kernel must be compiled to a
2125 memory address not used by the main kernel
2127 For more details see Documentation/kdump/kdump.txt
2129 config AUTO_ZRELADDR
2130 bool "Auto calculation of the decompressed kernel image address"
2131 depends on !ZBOOT_ROM
2132 help
2133 ZRELADDR is the physical address where the decompressed kernel
2134 image will be placed. If AUTO_ZRELADDR is selected, the address
2135 will be determined at run-time by masking the current IP with
2136 0xf8000000. This assumes the zImage being placed in the first 128MB
2137 from start of memory.
2139 endmenu
2141 menu "CPU Power Management"
2143 if ARCH_HAS_CPUFREQ
2144 source "drivers/cpufreq/Kconfig"
2145 endif
2147 source "drivers/cpuidle/Kconfig"
2149 endmenu
2151 menu "Floating point emulation"
2153 comment "At least one emulation must be selected"
2155 config FPE_NWFPE
2156 bool "NWFPE math emulation"
2157 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2158 ---help---
2159 Say Y to include the NWFPE floating point emulator in the kernel.
2160 This is necessary to run most binaries. Linux does not currently
2161 support floating point hardware so you need to say Y here even if
2162 your machine has an FPA or floating point co-processor podule.
2164 You may say N here if you are going to load the Acorn FPEmulator
2165 early in the bootup.
2167 config FPE_NWFPE_XP
2168 bool "Support extended precision"
2169 depends on FPE_NWFPE
2170 help
2171 Say Y to include 80-bit support in the kernel floating-point
2172 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2173 Note that gcc does not generate 80-bit operations by default,
2174 so in most cases this option only enlarges the size of the
2175 floating point emulator without any good reason.
2177 You almost surely want to say N here.
2179 config FPE_FASTFPE
2180 bool "FastFPE math emulation (EXPERIMENTAL)"
2181 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2182 ---help---
2183 Say Y here to include the FAST floating point emulator in the kernel.
2184 This is an experimental much faster emulator which now also has full
2185 precision for the mantissa. It does not support any exceptions.
2186 It is very simple, and approximately 3-6 times faster than NWFPE.
2188 It should be sufficient for most programs. It may be not suitable
2189 for scientific calculations, but you have to check this for yourself.
2190 If you do not feel you need a faster FP emulation you should better
2191 choose NWFPE.
2193 config VFP
2194 bool "VFP-format floating point maths"
2195 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2196 help
2197 Say Y to include VFP support code in the kernel. This is needed
2198 if your hardware includes a VFP unit.
2200 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2201 release notes and additional status information.
2203 Say N if your target does not have VFP hardware.
2205 config VFPv3
2206 bool
2207 depends on VFP
2208 default y if CPU_V7
2210 config NEON
2211 bool "Advanced SIMD (NEON) Extension support"
2212 depends on VFPv3 && CPU_V7
2213 help
2214 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2215 Extension.
2217 config KERNEL_MODE_NEON
2218 bool "Support for NEON in kernel mode"
2219 default n
2220 depends on NEON
2221 help
2222 Say Y to include support for NEON in kernel mode.
2224 endmenu
2226 menu "Userspace binary formats"
2228 source "fs/Kconfig.binfmt"
2230 config ARTHUR
2231 tristate "RISC OS personality"
2232 depends on !AEABI
2233 help
2234 Say Y here to include the kernel code necessary if you want to run
2235 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2236 experimental; if this sounds frightening, say N and sleep in peace.
2237 You can also say M here to compile this support as a module (which
2238 will be called arthur).
2240 endmenu
2242 menu "Power management options"
2244 source "kernel/power/Kconfig"
2246 config ARCH_SUSPEND_POSSIBLE
2247 depends on !ARCH_S5PC100
2248 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2249 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2250 def_bool y
2252 config ARM_CPU_SUSPEND
2253 def_bool PM_SLEEP
2255 endmenu
2257 source "net/Kconfig"
2259 source "drivers/Kconfig"
2261 source "fs/Kconfig"
2263 source "arch/arm/Kconfig.debug"
2265 source "security/Kconfig"
2267 source "crypto/Kconfig"
2269 source "lib/Kconfig"
2271 source "arch/arm/kvm/Kconfig"