arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91_dbgu.h>
  22 #include <mach/at91sam9260.h>
  23 #include <mach/at91_pmc.h>
  24
  25 #include "at91_aic.h"
  26 #include "at91_rstc.h"
  27 #include "soc.h"
  28 #include "generic.h"
  29 #include "clock.h"
  30 #include "sam9_smc.h"
  31
  32 /* --------------------------------------------------------------------
  33  *  Clocks
  34  * -------------------------------------------------------------------- */
  35
  36 /*
  37  * The peripheral clocks.
  38  */
  39 static struct clk pioA_clk = {
  40         .name           = "pioA_clk",
  41         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  42         .type           = CLK_TYPE_PERIPHERAL,
  43 };
  44 static struct clk pioB_clk = {
  45         .name           = "pioB_clk",
  46         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  47         .type           = CLK_TYPE_PERIPHERAL,
  48 };
  49 static struct clk pioC_clk = {
  50         .name           = "pioC_clk",
  51         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  52         .type           = CLK_TYPE_PERIPHERAL,
  53 };
  54 static struct clk adc_clk = {
  55         .name           = "adc_clk",
  56         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  57         .type           = CLK_TYPE_PERIPHERAL,
  58 };
  59
  60 static struct clk adc_op_clk = {
  61         .name           = "adc_op_clk",
  62         .type           = CLK_TYPE_PERIPHERAL,
  63         .rate_hz        = 5000000,
  64 };
  65
  66 static struct clk usart0_clk = {
  67         .name           = "usart0_clk",
  68         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  69         .type           = CLK_TYPE_PERIPHERAL,
  70 };
  71 static struct clk usart1_clk = {
  72         .name           = "usart1_clk",
  73         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
  74         .type           = CLK_TYPE_PERIPHERAL,
  75 };
  76 static struct clk usart2_clk = {
  77         .name           = "usart2_clk",
  78         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
  79         .type           = CLK_TYPE_PERIPHERAL,
  80 };
  81 static struct clk mmc_clk = {
  82         .name           = "mci_clk",
  83         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
  84         .type           = CLK_TYPE_PERIPHERAL,
  85 };
  86 static struct clk udc_clk = {
  87         .name           = "udc_clk",
  88         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
  89         .type           = CLK_TYPE_PERIPHERAL,
  90 };
  91 static struct clk twi_clk = {
  92         .name           = "twi_clk",
  93         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
  94         .type           = CLK_TYPE_PERIPHERAL,
  95 };
  96 static struct clk spi0_clk = {
  97         .name           = "spi0_clk",
  98         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
  99         .type           = CLK_TYPE_PERIPHERAL,
 100 };
 101 static struct clk spi1_clk = {
 102         .name           = "spi1_clk",
 103         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 104         .type           = CLK_TYPE_PERIPHERAL,
 105 };
 106 static struct clk ssc_clk = {
 107         .name           = "ssc_clk",
 108         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 109         .type           = CLK_TYPE_PERIPHERAL,
 110 };
 111 static struct clk tc0_clk = {
 112         .name           = "tc0_clk",
 113         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 114         .type           = CLK_TYPE_PERIPHERAL,
 115 };
 116 static struct clk tc1_clk = {
 117         .name           = "tc1_clk",
 118         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 119         .type           = CLK_TYPE_PERIPHERAL,
 120 };
 121 static struct clk tc2_clk = {
 122         .name           = "tc2_clk",
 123         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 124         .type           = CLK_TYPE_PERIPHERAL,
 125 };
 126 static struct clk ohci_clk = {
 127         .name           = "ohci_clk",
 128         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 129         .type           = CLK_TYPE_PERIPHERAL,
 130 };
 131 static struct clk macb_clk = {
 132         .name           = "pclk",
 133         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 134         .type           = CLK_TYPE_PERIPHERAL,
 135 };
 136 static struct clk isi_clk = {
 137         .name           = "isi_clk",
 138         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 139         .type           = CLK_TYPE_PERIPHERAL,
 140 };
 141 static struct clk usart3_clk = {
 142         .name           = "usart3_clk",
 143         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 144         .type           = CLK_TYPE_PERIPHERAL,
 145 };
 146 static struct clk usart4_clk = {
 147         .name           = "usart4_clk",
 148         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 149         .type           = CLK_TYPE_PERIPHERAL,
 150 };
 151 static struct clk usart5_clk = {
 152         .name           = "usart5_clk",
 153         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 154         .type           = CLK_TYPE_PERIPHERAL,
 155 };
 156 static struct clk tc3_clk = {
 157         .name           = "tc3_clk",
 158         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 159         .type           = CLK_TYPE_PERIPHERAL,
 160 };
 161 static struct clk tc4_clk = {
 162         .name           = "tc4_clk",
 163         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 164         .type           = CLK_TYPE_PERIPHERAL,
 165 };
 166 static struct clk tc5_clk = {
 167         .name           = "tc5_clk",
 168         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 169         .type           = CLK_TYPE_PERIPHERAL,
 170 };
 171
 172 static struct clk *periph_clocks[] __initdata = {
 173         &pioA_clk,
 174         &pioB_clk,
 175         &pioC_clk,
 176         &adc_clk,
 177         &adc_op_clk,
 178         &usart0_clk,
 179         &usart1_clk,
 180         &usart2_clk,
 181         &mmc_clk,
 182         &udc_clk,
 183         &twi_clk,
 184         &spi0_clk,
 185         &spi1_clk,
 186         &ssc_clk,
 187         &tc0_clk,
 188         &tc1_clk,
 189         &tc2_clk,
 190         &ohci_clk,
 191         &macb_clk,
 192         &isi_clk,
 193         &usart3_clk,
 194         &usart4_clk,
 195         &usart5_clk,
 196         &tc3_clk,
 197         &tc4_clk,
 198         &tc5_clk,
 199         // irq0 .. irq2
 200 };
 201
 202 static struct clk_lookup periph_clocks_lookups[] = {
 203         /* One additional fake clock for macb_hclk */
 204         CLKDEV_CON_ID("hclk", &macb_clk),
 205         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 206         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 207         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 208         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 209         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 210         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 211         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 212         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 213         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
 214         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
 215         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
 216         /* more usart lookup table for DT entries */
 217         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 218         CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 219         CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
 220         CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
 221         CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
 222         CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
 223         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
 224         CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
 225         /* more tc lookup table for DT entries */
 226         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 227         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 228         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 229         CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
 230         CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 231         CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 232         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
 233         /* fake hclk clock */
 234         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 235         CLKDEV_CON_ID("pioA", &pioA_clk),
 236         CLKDEV_CON_ID("pioB", &pioB_clk),
 237         CLKDEV_CON_ID("pioC", &pioC_clk),
 238 };
 239
 240 static struct clk_lookup usart_clocks_lookups[] = {
 241         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 242         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 243         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 244         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 245         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 246         CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
 247         CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
 248 };
 249
 250 /*
 251  * The two programmable clocks.
 252  * You must configure pin multiplexing to bring these signals out.
 253  */
 254 static struct clk pck0 = {
 255         .name           = "pck0",
 256         .pmc_mask       = AT91_PMC_PCK0,
 257         .type           = CLK_TYPE_PROGRAMMABLE,
 258         .id             = 0,
 259 };
 260 static struct clk pck1 = {
 261         .name           = "pck1",
 262         .pmc_mask       = AT91_PMC_PCK1,
 263         .type           = CLK_TYPE_PROGRAMMABLE,
 264         .id             = 1,
 265 };
 266
 267 static void __init at91sam9260_register_clocks(void)
 268 {
 269         int i;
 270
 271         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 272                 clk_register(periph_clocks[i]);
 273
 274         clkdev_add_table(periph_clocks_lookups,
 275                          ARRAY_SIZE(periph_clocks_lookups));
 276         clkdev_add_table(usart_clocks_lookups,
 277                          ARRAY_SIZE(usart_clocks_lookups));
 278
 279         clk_register(&pck0);
 280         clk_register(&pck1);
 281 }
 282
 283 /* --------------------------------------------------------------------
 284  *  GPIO
 285  * -------------------------------------------------------------------- */
 286
 287 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
 288         {
 289                 .id             = AT91SAM9260_ID_PIOA,
 290                 .regbase        = AT91SAM9260_BASE_PIOA,
 291         }, {
 292                 .id             = AT91SAM9260_ID_PIOB,
 293                 .regbase        = AT91SAM9260_BASE_PIOB,
 294         }, {
 295                 .id             = AT91SAM9260_ID_PIOC,
 296                 .regbase        = AT91SAM9260_BASE_PIOC,
 297         }
 298 };
 299
 300 /* --------------------------------------------------------------------
 301  *  AT91SAM9260 processor initialization
 302  * -------------------------------------------------------------------- */
 303
 304 static void __init at91sam9xe_map_io(void)
 305 {
 306         unsigned long sram_size;
 307
 308         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 309                 case AT91_CIDR_SRAMSIZ_32K:
 310                         sram_size = 2 * SZ_16K;
 311                         break;
 312                 case AT91_CIDR_SRAMSIZ_16K:
 313                 default:
 314                         sram_size = SZ_16K;
 315         }
 316
 317         at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
 318 }
 319
 320 static void __init at91sam9260_map_io(void)
 321 {
 322         if (cpu_is_at91sam9xe())
 323                 at91sam9xe_map_io();
 324         else if (cpu_is_at91sam9g20())
 325                 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
 326         else
 327                 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 328 }
 329
 330 static void __init at91sam9260_ioremap_registers(void)
 331 {
 332         at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
 333         at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
 334         at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
 335         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
 336         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 337         at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 338 }
 339
 340 static void __init at91sam9260_initialize(void)
 341 {
 342         arm_pm_idle = at91sam9_idle;
 343         arm_pm_restart = at91sam9_alt_restart;
 344         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 345                         | (1 << AT91SAM9260_ID_IRQ2);
 346
 347         /* Register GPIO subsystem */
 348         at91_gpio_init(at91sam9260_gpio, 3);
 349 }
 350
 351 /* --------------------------------------------------------------------
 352  *  Interrupt initialization
 353  * -------------------------------------------------------------------- */
 354
 355 /*
 356  * The default interrupt priority levels (0 = lowest, 7 = highest).
 357  */
 358 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 359         7,      /* Advanced Interrupt Controller */
 360         7,      /* System Peripherals */
 361         1,      /* Parallel IO Controller A */
 362         1,      /* Parallel IO Controller B */
 363         1,      /* Parallel IO Controller C */
 364         0,      /* Analog-to-Digital Converter */
 365         5,      /* USART 0 */
 366         5,      /* USART 1 */
 367         5,      /* USART 2 */
 368         0,      /* Multimedia Card Interface */
 369         2,      /* USB Device Port */
 370         6,      /* Two-Wire Interface */
 371         5,      /* Serial Peripheral Interface 0 */
 372         5,      /* Serial Peripheral Interface 1 */
 373         5,      /* Serial Synchronous Controller */
 374         0,
 375         0,
 376         0,      /* Timer Counter 0 */
 377         0,      /* Timer Counter 1 */
 378         0,      /* Timer Counter 2 */
 379         2,      /* USB Host port */
 380         3,      /* Ethernet */
 381         0,      /* Image Sensor Interface */
 382         5,      /* USART 3 */
 383         5,      /* USART 4 */
 384         5,      /* USART 5 */
 385         0,      /* Timer Counter 3 */
 386         0,      /* Timer Counter 4 */
 387         0,      /* Timer Counter 5 */
 388         0,      /* Advanced Interrupt Controller */
 389         0,      /* Advanced Interrupt Controller */
 390         0,      /* Advanced Interrupt Controller */
 391 };
 392
 393 struct at91_init_soc __initdata at91sam9260_soc = {
 394         .map_io = at91sam9260_map_io,
 395         .default_irq_priority = at91sam9260_default_irq_priority,
 396         .ioremap_registers = at91sam9260_ioremap_registers,
 397         .register_clocks = at91sam9260_register_clocks,
 398         .init = at91sam9260_initialize,
 399 };