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Disintegrate asm/system.h for X86
[linux-2.6.git] / arch / x86 / include / asm / processor.h
blob78e30ea492b2b0f33236f251f9cd3376f517d2ae
1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/page.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23 #include <asm/special_insns.h>
24
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
33
34 /*
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
37 *
38 * Based on this we disable the IP header alignment in network drivers.
39 */
40 #define NET_IP_ALIGN 0
41
42 #define HBP_NUM 4
43 /*
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
46 */
47 static inline void *current_text_addr(void)
48 {
49 void *pc;
50
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
52
53 return pc;
54 }
55
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
59 #else
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
62 #endif
63
64 /*
65 * CPU type and hardware bug flags. Kept separately for each CPU.
66 * Members of this structure are referenced in head.S, so think twice
67 * before touching them. [mj]
68 */
69
70 struct cpuinfo_x86 {
71 __u8 x86; /* CPU family */
72 __u8 x86_vendor; /* CPU vendor */
73 __u8 x86_model;
74 __u8 x86_mask;
75 #ifdef CONFIG_X86_32
76 char wp_works_ok; /* It doesn't on 386's */
77
78 /* Problems on some 486Dx4's and old 386's: */
79 char hlt_works_ok;
80 char hard_math;
81 char rfu;
82 char fdiv_bug;
83 char f00f_bug;
84 char coma_bug;
85 char pad0;
86 #else
87 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
88 int x86_tlbsize;
89 #endif
90 __u8 x86_virt_bits;
91 __u8 x86_phys_bits;
92 /* CPUID returned core id bits: */
93 __u8 x86_coreid_bits;
94 /* Max extended CPUID function supported: */
95 __u32 extended_cpuid_level;
96 /* Maximum supported CPUID level, -1=no CPUID: */
97 int cpuid_level;
98 __u32 x86_capability[NCAPINTS];
99 char x86_vendor_id[16];
100 char x86_model_id[64];
101 /* in KB - valid for CPUS which support this call: */
102 int x86_cache_size;
103 int x86_cache_alignment; /* In bytes */
104 int x86_power;
105 unsigned long loops_per_jiffy;
106 /* cpuid returned max cores value: */
107 u16 x86_max_cores;
108 u16 apicid;
109 u16 initial_apicid;
110 u16 x86_clflush_size;
111 /* number of cores as seen by the OS: */
112 u16 booted_cores;
113 /* Physical processor id: */
114 u16 phys_proc_id;
115 /* Core id: */
116 u16 cpu_core_id;
117 /* Compute unit id */
118 u8 compute_unit_id;
119 /* Index into per_cpu list: */
120 u16 cpu_index;
121 u32 microcode;
122 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
123
124 #define X86_VENDOR_INTEL 0
125 #define X86_VENDOR_CYRIX 1
126 #define X86_VENDOR_AMD 2
127 #define X86_VENDOR_UMC 3
128 #define X86_VENDOR_CENTAUR 5
129 #define X86_VENDOR_TRANSMETA 7
130 #define X86_VENDOR_NSC 8
131 #define X86_VENDOR_NUM 9
132
133 #define X86_VENDOR_UNKNOWN 0xff
134
135 /*
136 * capabilities of CPUs
137 */
138 extern struct cpuinfo_x86 boot_cpu_data;
139 extern struct cpuinfo_x86 new_cpu_data;
140
141 extern struct tss_struct doublefault_tss;
142 extern __u32 cpu_caps_cleared[NCAPINTS];
143 extern __u32 cpu_caps_set[NCAPINTS];
144
145 #ifdef CONFIG_SMP
146 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
147 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
148 #else
149 #define cpu_info boot_cpu_data
150 #define cpu_data(cpu) boot_cpu_data
151 #endif
152
153 extern const struct seq_operations cpuinfo_op;
154
155 static inline int hlt_works(int cpu)
156 {
157 #ifdef CONFIG_X86_32
158 return cpu_data(cpu).hlt_works_ok;
159 #else
160 return 1;
161 #endif
162 }
163
164 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
165
166 extern void cpu_detect(struct cpuinfo_x86 *c);
167
168 extern struct pt_regs *idle_regs(struct pt_regs *);
169
170 extern void early_cpu_init(void);
171 extern void identify_boot_cpu(void);
172 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
173 extern void print_cpu_info(struct cpuinfo_x86 *);
174 void print_cpu_msr(struct cpuinfo_x86 *);
175 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
176 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
177 extern unsigned short num_cache_leaves;
178
179 extern void detect_extended_topology(struct cpuinfo_x86 *c);
180 extern void detect_ht(struct cpuinfo_x86 *c);
181
182 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
183 unsigned int *ecx, unsigned int *edx)
184 {
185 /* ecx is often an input as well as an output. */
186 asm volatile("cpuid"
187 : "=a" (*eax),
188 "=b" (*ebx),
189 "=c" (*ecx),
190 "=d" (*edx)
191 : "0" (*eax), "2" (*ecx)
192 : "memory");
193 }
194
195 static inline void load_cr3(pgd_t *pgdir)
196 {
197 write_cr3(__pa(pgdir));
198 }
199
200 #ifdef CONFIG_X86_32
201 /* This is the TSS defined by the hardware. */
202 struct x86_hw_tss {
203 unsigned short back_link, __blh;
204 unsigned long sp0;
205 unsigned short ss0, __ss0h;
206 unsigned long sp1;
207 /* ss1 caches MSR_IA32_SYSENTER_CS: */
208 unsigned short ss1, __ss1h;
209 unsigned long sp2;
210 unsigned short ss2, __ss2h;
211 unsigned long __cr3;
212 unsigned long ip;
213 unsigned long flags;
214 unsigned long ax;
215 unsigned long cx;
216 unsigned long dx;
217 unsigned long bx;
218 unsigned long sp;
219 unsigned long bp;
220 unsigned long si;
221 unsigned long di;
222 unsigned short es, __esh;
223 unsigned short cs, __csh;
224 unsigned short ss, __ssh;
225 unsigned short ds, __dsh;
226 unsigned short fs, __fsh;
227 unsigned short gs, __gsh;
228 unsigned short ldt, __ldth;
229 unsigned short trace;
230 unsigned short io_bitmap_base;
231
232 } __attribute__((packed));
233 #else
234 struct x86_hw_tss {
235 u32 reserved1;
236 u64 sp0;
237 u64 sp1;
238 u64 sp2;
239 u64 reserved2;
240 u64 ist[7];
241 u32 reserved3;
242 u32 reserved4;
243 u16 reserved5;
244 u16 io_bitmap_base;
245
246 } __attribute__((packed)) ____cacheline_aligned;
247 #endif
248
249 /*
250 * IO-bitmap sizes:
251 */
252 #define IO_BITMAP_BITS 65536
253 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
254 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
255 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
256 #define INVALID_IO_BITMAP_OFFSET 0x8000
257
258 struct tss_struct {
259 /*
260 * The hardware state:
261 */
262 struct x86_hw_tss x86_tss;
263
264 /*
265 * The extra 1 is there because the CPU will access an
266 * additional byte beyond the end of the IO permission
267 * bitmap. The extra byte must be all 1 bits, and must
268 * be within the limit.
269 */
270 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
271
272 /*
273 * .. and then another 0x100 bytes for the emergency kernel stack:
274 */
275 unsigned long stack[64];
276
277 } ____cacheline_aligned;
278
279 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
280
281 /*
282 * Save the original ist values for checking stack pointers during debugging
283 */
284 struct orig_ist {
285 unsigned long ist[7];
286 };
287
288 #define MXCSR_DEFAULT 0x1f80
289
290 struct i387_fsave_struct {
291 u32 cwd; /* FPU Control Word */
292 u32 swd; /* FPU Status Word */
293 u32 twd; /* FPU Tag Word */
294 u32 fip; /* FPU IP Offset */
295 u32 fcs; /* FPU IP Selector */
296 u32 foo; /* FPU Operand Pointer Offset */
297 u32 fos; /* FPU Operand Pointer Selector */
298
299 /* 8*10 bytes for each FP-reg = 80 bytes: */
300 u32 st_space[20];
301
302 /* Software status information [not touched by FSAVE ]: */
303 u32 status;
304 };
305
306 struct i387_fxsave_struct {
307 u16 cwd; /* Control Word */
308 u16 swd; /* Status Word */
309 u16 twd; /* Tag Word */
310 u16 fop; /* Last Instruction Opcode */
311 union {
312 struct {
313 u64 rip; /* Instruction Pointer */
314 u64 rdp; /* Data Pointer */
315 };
316 struct {
317 u32 fip; /* FPU IP Offset */
318 u32 fcs; /* FPU IP Selector */
319 u32 foo; /* FPU Operand Offset */
320 u32 fos; /* FPU Operand Selector */
321 };
322 };
323 u32 mxcsr; /* MXCSR Register State */
324 u32 mxcsr_mask; /* MXCSR Mask */
325
326 /* 8*16 bytes for each FP-reg = 128 bytes: */
327 u32 st_space[32];
328
329 /* 16*16 bytes for each XMM-reg = 256 bytes: */
330 u32 xmm_space[64];
331
332 u32 padding[12];
333
334 union {
335 u32 padding1[12];
336 u32 sw_reserved[12];
337 };
338
339 } __attribute__((aligned(16)));
340
341 struct i387_soft_struct {
342 u32 cwd;
343 u32 swd;
344 u32 twd;
345 u32 fip;
346 u32 fcs;
347 u32 foo;
348 u32 fos;
349 /* 8*10 bytes for each FP-reg = 80 bytes: */
350 u32 st_space[20];
351 u8 ftop;
352 u8 changed;
353 u8 lookahead;
354 u8 no_update;
355 u8 rm;
356 u8 alimit;
357 struct math_emu_info *info;
358 u32 entry_eip;
359 };
360
361 struct ymmh_struct {
362 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
363 u32 ymmh_space[64];
364 };
365
366 struct xsave_hdr_struct {
367 u64 xstate_bv;
368 u64 reserved1[2];
369 u64 reserved2[5];
370 } __attribute__((packed));
371
372 struct xsave_struct {
373 struct i387_fxsave_struct i387;
374 struct xsave_hdr_struct xsave_hdr;
375 struct ymmh_struct ymmh;
376 /* new processor state extensions will go here */
377 } __attribute__ ((packed, aligned (64)));
378
379 union thread_xstate {
380 struct i387_fsave_struct fsave;
381 struct i387_fxsave_struct fxsave;
382 struct i387_soft_struct soft;
383 struct xsave_struct xsave;
384 };
385
386 struct fpu {
387 unsigned int last_cpu;
388 unsigned int has_fpu;
389 union thread_xstate *state;
390 };
391
392 #ifdef CONFIG_X86_64
393 DECLARE_PER_CPU(struct orig_ist, orig_ist);
394
395 union irq_stack_union {
396 char irq_stack[IRQ_STACK_SIZE];
397 /*
398 * GCC hardcodes the stack canary as %gs:40. Since the
399 * irq_stack is the object at %gs:0, we reserve the bottom
400 * 48 bytes of the irq stack for the canary.
401 */
402 struct {
403 char gs_base[40];
404 unsigned long stack_canary;
405 };
406 };
407
408 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
409 DECLARE_INIT_PER_CPU(irq_stack_union);
410
411 DECLARE_PER_CPU(char *, irq_stack_ptr);
412 DECLARE_PER_CPU(unsigned int, irq_count);
413 extern unsigned long kernel_eflags;
414 extern asmlinkage void ignore_sysret(void);
415 #else /* X86_64 */
416 #ifdef CONFIG_CC_STACKPROTECTOR
417 /*
418 * Make sure stack canary segment base is cached-aligned:
419 * "For Intel Atom processors, avoid non zero segment base address
420 * that is not aligned to cache line boundary at all cost."
421 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
422 */
423 struct stack_canary {
424 char __pad[20]; /* canary at %gs:20 */
425 unsigned long canary;
426 };
427 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
428 #endif
429 #endif /* X86_64 */
430
431 extern unsigned int xstate_size;
432 extern void free_thread_xstate(struct task_struct *);
433 extern struct kmem_cache *task_xstate_cachep;
434
435 struct perf_event;
436
437 struct thread_struct {
438 /* Cached TLS descriptors: */
439 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
440 unsigned long sp0;
441 unsigned long sp;
442 #ifdef CONFIG_X86_32
443 unsigned long sysenter_cs;
444 #else
445 unsigned long usersp; /* Copy from PDA */
446 unsigned short es;
447 unsigned short ds;
448 unsigned short fsindex;
449 unsigned short gsindex;
450 #endif
451 #ifdef CONFIG_X86_32
452 unsigned long ip;
453 #endif
454 #ifdef CONFIG_X86_64
455 unsigned long fs;
456 #endif
457 unsigned long gs;
458 /* Save middle states of ptrace breakpoints */
459 struct perf_event *ptrace_bps[HBP_NUM];
460 /* Debug status used for traps, single steps, etc... */
461 unsigned long debugreg6;
462 /* Keep track of the exact dr7 value set by the user */
463 unsigned long ptrace_dr7;
464 /* Fault info: */
465 unsigned long cr2;
466 unsigned long trap_no;
467 unsigned long error_code;
468 /* floating point and extended processor state */
469 struct fpu fpu;
470 #ifdef CONFIG_X86_32
471 /* Virtual 86 mode info */
472 struct vm86_struct __user *vm86_info;
473 unsigned long screen_bitmap;
474 unsigned long v86flags;
475 unsigned long v86mask;
476 unsigned long saved_sp0;
477 unsigned int saved_fs;
478 unsigned int saved_gs;
479 #endif
480 /* IO permissions: */
481 unsigned long *io_bitmap_ptr;
482 unsigned long iopl;
483 /* Max allowed port in the bitmap, in bytes: */
484 unsigned io_bitmap_max;
485 };
486
487 static inline unsigned long native_get_debugreg(int regno)
488 {
489 unsigned long val = 0; /* Damn you, gcc! */
490
491 switch (regno) {
492 case 0:
493 asm("mov %%db0, %0" :"=r" (val));
494 break;
495 case 1:
496 asm("mov %%db1, %0" :"=r" (val));
497 break;
498 case 2:
499 asm("mov %%db2, %0" :"=r" (val));
500 break;
501 case 3:
502 asm("mov %%db3, %0" :"=r" (val));
503 break;
504 case 6:
505 asm("mov %%db6, %0" :"=r" (val));
506 break;
507 case 7:
508 asm("mov %%db7, %0" :"=r" (val));
509 break;
510 default:
511 BUG();
512 }
513 return val;
514 }
515
516 static inline void native_set_debugreg(int regno, unsigned long value)
517 {
518 switch (regno) {
519 case 0:
520 asm("mov %0, %%db0" ::"r" (value));
521 break;
522 case 1:
523 asm("mov %0, %%db1" ::"r" (value));
524 break;
525 case 2:
526 asm("mov %0, %%db2" ::"r" (value));
527 break;
528 case 3:
529 asm("mov %0, %%db3" ::"r" (value));
530 break;
531 case 6:
532 asm("mov %0, %%db6" ::"r" (value));
533 break;
534 case 7:
535 asm("mov %0, %%db7" ::"r" (value));
536 break;
537 default:
538 BUG();
539 }
540 }
541
542 /*
543 * Set IOPL bits in EFLAGS from given mask
544 */
545 static inline void native_set_iopl_mask(unsigned mask)
546 {
547 #ifdef CONFIG_X86_32
548 unsigned int reg;
549
550 asm volatile ("pushfl;"
551 "popl %0;"
552 "andl %1, %0;"
553 "orl %2, %0;"
554 "pushl %0;"
555 "popfl"
556 : "=&r" (reg)
557 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
558 #endif
559 }
560
561 static inline void
562 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
563 {
564 tss->x86_tss.sp0 = thread->sp0;
565 #ifdef CONFIG_X86_32
566 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
567 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
568 tss->x86_tss.ss1 = thread->sysenter_cs;
569 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
570 }
571 #endif
572 }
573
574 static inline void native_swapgs(void)
575 {
576 #ifdef CONFIG_X86_64
577 asm volatile("swapgs" ::: "memory");
578 #endif
579 }
580
581 #ifdef CONFIG_PARAVIRT
582 #include <asm/paravirt.h>
583 #else
584 #define __cpuid native_cpuid
585 #define paravirt_enabled() 0
586
587 /*
588 * These special macros can be used to get or set a debugging register
589 */
590 #define get_debugreg(var, register) \
591 (var) = native_get_debugreg(register)
592 #define set_debugreg(value, register) \
593 native_set_debugreg(register, value)
594
595 static inline void load_sp0(struct tss_struct *tss,
596 struct thread_struct *thread)
597 {
598 native_load_sp0(tss, thread);
599 }
600
601 #define set_iopl_mask native_set_iopl_mask
602 #endif /* CONFIG_PARAVIRT */
603
604 /*
605 * Save the cr4 feature set we're using (ie
606 * Pentium 4MB enable and PPro Global page
607 * enable), so that any CPU's that boot up
608 * after us can get the correct flags.
609 */
610 extern unsigned long mmu_cr4_features;
611
612 static inline void set_in_cr4(unsigned long mask)
613 {
614 unsigned long cr4;
615
616 mmu_cr4_features |= mask;
617 cr4 = read_cr4();
618 cr4 |= mask;
619 write_cr4(cr4);
620 }
621
622 static inline void clear_in_cr4(unsigned long mask)
623 {
624 unsigned long cr4;
625
626 mmu_cr4_features &= ~mask;
627 cr4 = read_cr4();
628 cr4 &= ~mask;
629 write_cr4(cr4);
630 }
631
632 typedef struct {
633 unsigned long seg;
634 } mm_segment_t;
635
636
637 /*
638 * create a kernel thread without removing it from tasklists
639 */
640 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
641
642 /* Free all resources held by a thread. */
643 extern void release_thread(struct task_struct *);
644
645 /* Prepare to copy thread state - unlazy all lazy state */
646 extern void prepare_to_copy(struct task_struct *tsk);
647
648 unsigned long get_wchan(struct task_struct *p);
649
650 /*
651 * Generic CPUID function
652 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
653 * resulting in stale register contents being returned.
654 */
655 static inline void cpuid(unsigned int op,
656 unsigned int *eax, unsigned int *ebx,
657 unsigned int *ecx, unsigned int *edx)
658 {
659 *eax = op;
660 *ecx = 0;
661 __cpuid(eax, ebx, ecx, edx);
662 }
663
664 /* Some CPUID calls want 'count' to be placed in ecx */
665 static inline void cpuid_count(unsigned int op, int count,
666 unsigned int *eax, unsigned int *ebx,
667 unsigned int *ecx, unsigned int *edx)
668 {
669 *eax = op;
670 *ecx = count;
671 __cpuid(eax, ebx, ecx, edx);
672 }
673
674 /*
675 * CPUID functions returning a single datum
676 */
677 static inline unsigned int cpuid_eax(unsigned int op)
678 {
679 unsigned int eax, ebx, ecx, edx;
680
681 cpuid(op, &eax, &ebx, &ecx, &edx);
682
683 return eax;
684 }
685
686 static inline unsigned int cpuid_ebx(unsigned int op)
687 {
688 unsigned int eax, ebx, ecx, edx;
689
690 cpuid(op, &eax, &ebx, &ecx, &edx);
691
692 return ebx;
693 }
694
695 static inline unsigned int cpuid_ecx(unsigned int op)
696 {
697 unsigned int eax, ebx, ecx, edx;
698
699 cpuid(op, &eax, &ebx, &ecx, &edx);
700
701 return ecx;
702 }
703
704 static inline unsigned int cpuid_edx(unsigned int op)
705 {
706 unsigned int eax, ebx, ecx, edx;
707
708 cpuid(op, &eax, &ebx, &ecx, &edx);
709
710 return edx;
711 }
712
713 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
714 static inline void rep_nop(void)
715 {
716 asm volatile("rep; nop" ::: "memory");
717 }
718
719 static inline void cpu_relax(void)
720 {
721 rep_nop();
722 }
723
724 /* Stop speculative execution and prefetching of modified code. */
725 static inline void sync_core(void)
726 {
727 int tmp;
728
729 #if defined(CONFIG_M386) || defined(CONFIG_M486)
730 if (boot_cpu_data.x86 < 5)
731 /* There is no speculative execution.
732 * jmp is a barrier to prefetching. */
733 asm volatile("jmp 1f\n1:\n" ::: "memory");
734 else
735 #endif
736 /* cpuid is a barrier to speculative execution.
737 * Prefetched instructions are automatically
738 * invalidated when modified. */
739 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
740 : "ebx", "ecx", "edx", "memory");
741 }
742
743 static inline void __monitor(const void *eax, unsigned long ecx,
744 unsigned long edx)
745 {
746 /* "monitor %eax, %ecx, %edx;" */
747 asm volatile(".byte 0x0f, 0x01, 0xc8;"
748 :: "a" (eax), "c" (ecx), "d"(edx));
749 }
750
751 static inline void __mwait(unsigned long eax, unsigned long ecx)
752 {
753 /* "mwait %eax, %ecx;" */
754 asm volatile(".byte 0x0f, 0x01, 0xc9;"
755 :: "a" (eax), "c" (ecx));
756 }
757
758 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
759 {
760 trace_hardirqs_on();
761 /* "mwait %eax, %ecx;" */
762 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
763 :: "a" (eax), "c" (ecx));
764 }
765
766 extern void select_idle_routine(const struct cpuinfo_x86 *c);
767 extern void init_amd_e400_c1e_mask(void);
768
769 extern unsigned long boot_option_idle_override;
770 extern bool amd_e400_c1e_detected;
771
772 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
773 IDLE_POLL, IDLE_FORCE_MWAIT};
774
775 extern void enable_sep_cpu(void);
776 extern int sysenter_setup(void);
777
778 extern void early_trap_init(void);
779
780 /* Defined in head.S */
781 extern struct desc_ptr early_gdt_descr;
782
783 extern void cpu_set_gdt(int);
784 extern void switch_to_new_gdt(int);
785 extern void load_percpu_segment(int);
786 extern void cpu_init(void);
787
788 static inline unsigned long get_debugctlmsr(void)
789 {
790 unsigned long debugctlmsr = 0;
791
792 #ifndef CONFIG_X86_DEBUGCTLMSR
793 if (boot_cpu_data.x86 < 6)
794 return 0;
795 #endif
796 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
797
798 return debugctlmsr;
799 }
800
801 static inline void update_debugctlmsr(unsigned long debugctlmsr)
802 {
803 #ifndef CONFIG_X86_DEBUGCTLMSR
804 if (boot_cpu_data.x86 < 6)
805 return;
806 #endif
807 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
808 }
809
810 /*
811 * from system description table in BIOS. Mostly for MCA use, but
812 * others may find it useful:
813 */
814 extern unsigned int machine_id;
815 extern unsigned int machine_submodel_id;
816 extern unsigned int BIOS_revision;
817
818 /* Boot loader type from the setup header: */
819 extern int bootloader_type;
820 extern int bootloader_version;
821
822 extern char ignore_fpu_irq;
823
824 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
825 #define ARCH_HAS_PREFETCHW
826 #define ARCH_HAS_SPINLOCK_PREFETCH
827
828 #ifdef CONFIG_X86_32
829 # define BASE_PREFETCH ASM_NOP4
830 # define ARCH_HAS_PREFETCH
831 #else
832 # define BASE_PREFETCH "prefetcht0 (%1)"
833 #endif
834
835 /*
836 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
837 *
838 * It's not worth to care about 3dnow prefetches for the K6
839 * because they are microcoded there and very slow.
840 */
841 static inline void prefetch(const void *x)
842 {
843 alternative_input(BASE_PREFETCH,
844 "prefetchnta (%1)",
845 X86_FEATURE_XMM,
846 "r" (x));
847 }
848
849 /*
850 * 3dnow prefetch to get an exclusive cache line.
851 * Useful for spinlocks to avoid one state transition in the
852 * cache coherency protocol:
853 */
854 static inline void prefetchw(const void *x)
855 {
856 alternative_input(BASE_PREFETCH,
857 "prefetchw (%1)",
858 X86_FEATURE_3DNOW,
859 "r" (x));
860 }
861
862 static inline void spin_lock_prefetch(const void *x)
863 {
864 prefetchw(x);
865 }
866
867 #ifdef CONFIG_X86_32
868 /*
869 * User space process size: 3GB (default).
870 */
871 #define TASK_SIZE PAGE_OFFSET
872 #define TASK_SIZE_MAX TASK_SIZE
873 #define STACK_TOP TASK_SIZE
874 #define STACK_TOP_MAX STACK_TOP
875
876 #define INIT_THREAD { \
877 .sp0 = sizeof(init_stack) + (long)&init_stack, \
878 .vm86_info = NULL, \
879 .sysenter_cs = __KERNEL_CS, \
880 .io_bitmap_ptr = NULL, \
881 }
882
883 /*
884 * Note that the .io_bitmap member must be extra-big. This is because
885 * the CPU will access an additional byte beyond the end of the IO
886 * permission bitmap. The extra byte must be all 1 bits, and must
887 * be within the limit.
888 */
889 #define INIT_TSS { \
890 .x86_tss = { \
891 .sp0 = sizeof(init_stack) + (long)&init_stack, \
892 .ss0 = __KERNEL_DS, \
893 .ss1 = __KERNEL_CS, \
894 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
895 }, \
896 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
897 }
898
899 extern unsigned long thread_saved_pc(struct task_struct *tsk);
900
901 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
902 #define KSTK_TOP(info) \
903 ({ \
904 unsigned long *__ptr = (unsigned long *)(info); \
905 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
906 })
907
908 /*
909 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
910 * This is necessary to guarantee that the entire "struct pt_regs"
911 * is accessible even if the CPU haven't stored the SS/ESP registers
912 * on the stack (interrupt gate does not save these registers
913 * when switching to the same priv ring).
914 * Therefore beware: accessing the ss/esp fields of the
915 * "struct pt_regs" is possible, but they may contain the
916 * completely wrong values.
917 */
918 #define task_pt_regs(task) \
919 ({ \
920 struct pt_regs *__regs__; \
921 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
922 __regs__ - 1; \
923 })
924
925 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
926
927 #else
928 /*
929 * User space process size. 47bits minus one guard page.
930 */
931 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
932
933 /* This decides where the kernel will search for a free chunk of vm
934 * space during mmap's.
935 */
936 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
937 0xc0000000 : 0xFFFFe000)
938
939 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
940 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
941 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
942 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
943
944 #define STACK_TOP TASK_SIZE
945 #define STACK_TOP_MAX TASK_SIZE_MAX
946
947 #define INIT_THREAD { \
948 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
949 }
950
951 #define INIT_TSS { \
952 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
953 }
954
955 /*
956 * Return saved PC of a blocked thread.
957 * What is this good for? it will be always the scheduler or ret_from_fork.
958 */
959 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
960
961 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
962 extern unsigned long KSTK_ESP(struct task_struct *task);
963 #endif /* CONFIG_X86_64 */
964
965 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
966 unsigned long new_sp);
967
968 /*
969 * This decides where the kernel will search for a free chunk of vm
970 * space during mmap's.
971 */
972 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
973
974 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
975
976 /* Get/set a process' ability to use the timestamp counter instruction */
977 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
978 #define SET_TSC_CTL(val) set_tsc_mode((val))
979
980 extern int get_tsc_mode(unsigned long adr);
981 extern int set_tsc_mode(unsigned int val);
982
983 extern int amd_get_nb_id(int cpu);
984
985 struct aperfmperf {
986 u64 aperf, mperf;
987 };
988
989 static inline void get_aperfmperf(struct aperfmperf *am)
990 {
991 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
992
993 rdmsrl(MSR_IA32_APERF, am->aperf);
994 rdmsrl(MSR_IA32_MPERF, am->mperf);
995 }
996
997 #define APERFMPERF_SHIFT 10
998
999 static inline
1000 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
1001 struct aperfmperf *new)
1002 {
1003 u64 aperf = new->aperf - old->aperf;
1004 u64 mperf = new->mperf - old->mperf;
1005 unsigned long ratio = aperf;
1006
1007 mperf >>= APERFMPERF_SHIFT;
1008 if (mperf)
1009 ratio = div64_u64(aperf, mperf);
1010
1011 return ratio;
1012 }
1013
1014 /*
1015 * AMD errata checking
1016 */
1017 #ifdef CONFIG_CPU_SUP_AMD
1018 extern const int amd_erratum_383[];
1019 extern const int amd_erratum_400[];
1020 extern bool cpu_has_amd_erratum(const int *);
1021
1022 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1023 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1024 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1025 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1026 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1027 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1028 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1029
1030 #else
1031 #define cpu_has_amd_erratum(x) (false)
1032 #endif /* CONFIG_CPU_SUP_AMD */
1033
1034 #ifdef CONFIG_X86_32
1035 /*
1036 * disable hlt during certain critical i/o operations
1037 */
1038 #define HAVE_DISABLE_HLT
1039 #endif
1040
1041 void disable_hlt(void);
1042 void enable_hlt(void);
1043
1044 void cpu_idle_wait(void);
1045
1046 extern unsigned long arch_align_stack(unsigned long sp);
1047 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
1048
1049 void default_idle(void);
1050 bool set_pm_idle_to_default(void);
1051
1052 void stop_this_cpu(void *dummy);
1053
1054 #endif /* _ASM_X86_PROCESSOR_H */
Linus' kernel tree