arch/x86/kernel/setup_64.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  */
   4
   5 /*
   6  * This file handles the architecture-dependent parts of initialization
   7  */
   8
   9 #include <linux/errno.h>
  10 #include <linux/sched.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/stddef.h>
  14 #include <linux/unistd.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/slab.h>
  17 #include <linux/user.h>
  18 #include <linux/screen_info.h>
  19 #include <linux/ioport.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/initrd.h>
  23 #include <linux/highmem.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/module.h>
  26 #include <asm/processor.h>
  27 #include <linux/console.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/crash_dump.h>
  30 #include <linux/root_dev.h>
  31 #include <linux/pci.h>
  32 #include <asm/pci-direct.h>
  33 #include <linux/efi.h>
  34 #include <linux/acpi.h>
  35 #include <linux/kallsyms.h>
  36 #include <linux/edd.h>
  37 #include <linux/iscsi_ibft.h>
  38 #include <linux/mmzone.h>
  39 #include <linux/kexec.h>
  40 #include <linux/cpufreq.h>
  41 #include <linux/dmi.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/ctype.h>
  44 #include <linux/sort.h>
  45 #include <linux/uaccess.h>
  46 #include <linux/init_ohci1394_dma.h>
  47
  48 #include <asm/mtrr.h>
  49 #include <asm/uaccess.h>
  50 #include <asm/system.h>
  51 #include <asm/vsyscall.h>
  52 #include <asm/io.h>
  53 #include <asm/smp.h>
  54 #include <asm/msr.h>
  55 #include <asm/desc.h>
  56 #include <video/edid.h>
  57 #include <asm/e820.h>
  58 #include <asm/dma.h>
  59 #include <asm/gart.h>
  60 #include <asm/mpspec.h>
  61 #include <asm/mmu_context.h>
  62 #include <asm/proto.h>
  63 #include <asm/setup.h>
  64 #include <asm/numa.h>
  65 #include <asm/sections.h>
  66 #include <asm/dmi.h>
  67 #include <asm/cacheflush.h>
  68 #include <asm/mce.h>
  69 #include <asm/ds.h>
  70 #include <asm/topology.h>
  71 #include <asm/trampoline.h>
  72
  73 #include <mach_apic.h>
  74 #ifdef CONFIG_PARAVIRT
  75 #include <asm/paravirt.h>
  76 #else
  77 #define ARCH_SETUP
  78 #endif
  79
  80 /*
  81  * Machine setup..
  82  */
  83
  84 struct cpuinfo_x86 boot_cpu_data __read_mostly;
  85 EXPORT_SYMBOL(boot_cpu_data);
  86
  87 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
  88
  89 unsigned long mmu_cr4_features;
  90
  91 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  92 int bootloader_type;
  93
  94 unsigned long saved_video_mode;
  95
  96 int force_mwait __cpuinitdata;
  97
  98 /*
  99  * Early DMI memory
 100  */
 101 int dmi_alloc_index;
 102 char dmi_alloc_data[DMI_MAX_DATA];
 103
 104 /*
 105  * Setup options
 106  */
 107 struct screen_info screen_info;
 108 EXPORT_SYMBOL(screen_info);
 109 struct sys_desc_table_struct {
 110         unsigned short length;
 111         unsigned char table[0];
 112 };
 113
 114 struct edid_info edid_info;
 115 EXPORT_SYMBOL_GPL(edid_info);
 116
 117 extern int root_mountflags;
 118
 119 char __initdata command_line[COMMAND_LINE_SIZE];
 120
 121 static struct resource standard_io_resources[] = {
 122         { .name = "dma1", .start = 0x00, .end = 0x1f,
 123                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 124         { .name = "pic1", .start = 0x20, .end = 0x21,
 125                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 126         { .name = "timer0", .start = 0x40, .end = 0x43,
 127                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 128         { .name = "timer1", .start = 0x50, .end = 0x53,
 129                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 130         { .name = "keyboard", .start = 0x60, .end = 0x6f,
 131                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 132         { .name = "dma page reg", .start = 0x80, .end = 0x8f,
 133                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 134         { .name = "pic2", .start = 0xa0, .end = 0xa1,
 135                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 136         { .name = "dma2", .start = 0xc0, .end = 0xdf,
 137                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 138         { .name = "fpu", .start = 0xf0, .end = 0xff,
 139                 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
 140 };
 141
 142 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
 143
 144 static struct resource data_resource = {
 145         .name = "Kernel data",
 146         .start = 0,
 147         .end = 0,
 148         .flags = IORESOURCE_RAM,
 149 };
 150 static struct resource code_resource = {
 151         .name = "Kernel code",
 152         .start = 0,
 153         .end = 0,
 154         .flags = IORESOURCE_RAM,
 155 };
 156 static struct resource bss_resource = {
 157         .name = "Kernel bss",
 158         .start = 0,
 159         .end = 0,
 160         .flags = IORESOURCE_RAM,
 161 };
 162
 163 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
 164
 165 #ifdef CONFIG_PROC_VMCORE
 166 /* elfcorehdr= specifies the location of elf core header
 167  * stored by the crashed kernel. This option will be passed
 168  * by kexec loader to the capture kernel.
 169  */
 170 static int __init setup_elfcorehdr(char *arg)
 171 {
 172         char *end;
 173         if (!arg)
 174                 return -EINVAL;
 175         elfcorehdr_addr = memparse(arg, &end);
 176         return end > arg ? 0 : -EINVAL;
 177 }
 178 early_param("elfcorehdr", setup_elfcorehdr);
 179 #endif
 180
 181 #ifndef CONFIG_NUMA
 182 static void __init
 183 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 184 {
 185         unsigned long bootmap_size, bootmap;
 186
 187         bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
 188         bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
 189                                  PAGE_SIZE);
 190         if (bootmap == -1L)
 191                 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
 192         bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
 193         e820_register_active_regions(0, start_pfn, end_pfn);
 194         free_bootmem_with_active_regions(0, end_pfn);
 195         early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
 196         reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
 197 }
 198 #endif
 199
 200 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 201 struct edd edd;
 202 #ifdef CONFIG_EDD_MODULE
 203 EXPORT_SYMBOL(edd);
 204 #endif
 205 /**
 206  * copy_edd() - Copy the BIOS EDD information
 207  *              from boot_params into a safe place.
 208  *
 209  */
 210 static inline void copy_edd(void)
 211 {
 212      memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
 213             sizeof(edd.mbr_signature));
 214      memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
 215      edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
 216      edd.edd_info_nr = boot_params.eddbuf_entries;
 217 }
 218 #else
 219 static inline void copy_edd(void)
 220 {
 221 }
 222 #endif
 223
 224 #ifdef CONFIG_KEXEC
 225 static void __init reserve_crashkernel(void)
 226 {
 227         unsigned long long total_mem;
 228         unsigned long long crash_size, crash_base;
 229         int ret;
 230
 231         total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
 232
 233         ret = parse_crashkernel(boot_command_line, total_mem,
 234                         &crash_size, &crash_base);
 235         if (ret == 0 && crash_size) {
 236                 if (crash_base <= 0) {
 237                         printk(KERN_INFO "crashkernel reservation failed - "
 238                                         "you have to specify a base address\n");
 239                         return;
 240                 }
 241
 242                 if (reserve_bootmem(crash_base, crash_size,
 243                                         BOOTMEM_EXCLUSIVE) < 0) {
 244                         printk(KERN_INFO "crashkernel reservation failed - "
 245                                         "memory is in use\n");
 246                         return;
 247                 }
 248
 249                 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
 250                                 "for crashkernel (System RAM: %ldMB)\n",
 251                                 (unsigned long)(crash_size >> 20),
 252                                 (unsigned long)(crash_base >> 20),
 253                                 (unsigned long)(total_mem >> 20));
 254                 crashk_res.start = crash_base;
 255                 crashk_res.end   = crash_base + crash_size - 1;
 256                 insert_resource(&iomem_resource, &crashk_res);
 257         }
 258 }
 259 #else
 260 static inline void __init reserve_crashkernel(void)
 261 {}
 262 #endif
 263
 264 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
 265 void __attribute__((weak)) __init memory_setup(void)
 266 {
 267        machine_specific_memory_setup();
 268 }
 269
 270 static void __init parse_setup_data(void)
 271 {
 272         struct setup_data *data;
 273         unsigned long pa_data;
 274
 275         if (boot_params.hdr.version < 0x0209)
 276                 return;
 277         pa_data = boot_params.hdr.setup_data;
 278         while (pa_data) {
 279                 data = early_ioremap(pa_data, PAGE_SIZE);
 280                 switch (data->type) {
 281                 default:
 282                         break;
 283                 }
 284 #ifndef CONFIG_DEBUG_BOOT_PARAMS
 285                 free_early(pa_data, pa_data+sizeof(*data)+data->len);
 286 #endif
 287                 pa_data = data->next;
 288                 early_iounmap(data, PAGE_SIZE);
 289         }
 290 }
 291
 292 /*
 293  * setup_arch - architecture-specific boot-time initializations
 294  *
 295  * Note: On x86_64, fixmaps are ready for use even before this is called.
 296  */
 297 void __init setup_arch(char **cmdline_p)
 298 {
 299         unsigned i;
 300
 301         printk(KERN_INFO "Command line: %s\n", boot_command_line);
 302
 303         ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
 304         screen_info = boot_params.screen_info;
 305         edid_info = boot_params.edid_info;
 306         saved_video_mode = boot_params.hdr.vid_mode;
 307         bootloader_type = boot_params.hdr.type_of_loader;
 308
 309 #ifdef CONFIG_BLK_DEV_RAM
 310         rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
 311         rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
 312         rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
 313 #endif
 314 #ifdef CONFIG_EFI
 315         if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
 316                      "EL64", 4))
 317                 efi_enabled = 1;
 318 #endif
 319
 320         ARCH_SETUP
 321
 322         memory_setup();
 323         copy_edd();
 324
 325         if (!boot_params.hdr.root_flags)
 326                 root_mountflags &= ~MS_RDONLY;
 327         init_mm.start_code = (unsigned long) &_text;
 328         init_mm.end_code = (unsigned long) &_etext;
 329         init_mm.end_data = (unsigned long) &_edata;
 330         init_mm.brk = (unsigned long) &_end;
 331
 332         code_resource.start = virt_to_phys(&_text);
 333         code_resource.end = virt_to_phys(&_etext)-1;
 334         data_resource.start = virt_to_phys(&_etext);
 335         data_resource.end = virt_to_phys(&_edata)-1;
 336         bss_resource.start = virt_to_phys(&__bss_start);
 337         bss_resource.end = virt_to_phys(&__bss_stop)-1;
 338
 339         early_identify_cpu(&boot_cpu_data);
 340
 341         strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 342         *cmdline_p = command_line;
 343
 344         parse_setup_data();
 345
 346         parse_early_param();
 347
 348 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
 349         if (init_ohci1394_dma_early)
 350                 init_ohci1394_dma_on_all_controllers();
 351 #endif
 352
 353         finish_e820_parsing();
 354
 355         /* after parse_early_param, so could debug it */
 356         insert_resource(&iomem_resource, &code_resource);
 357         insert_resource(&iomem_resource, &data_resource);
 358         insert_resource(&iomem_resource, &bss_resource);
 359
 360         early_gart_iommu_check();
 361
 362         e820_register_active_regions(0, 0, -1UL);
 363         /*
 364          * partially used pages are not usable - thus
 365          * we are rounding upwards:
 366          */
 367         end_pfn = e820_end_of_ram();
 368         /* update e820 for memory not covered by WB MTRRs */
 369         mtrr_bp_init();
 370         if (mtrr_trim_uncached_memory(end_pfn)) {
 371                 e820_register_active_regions(0, 0, -1UL);
 372                 end_pfn = e820_end_of_ram();
 373         }
 374
 375         num_physpages = end_pfn;
 376
 377         check_efer();
 378
 379         max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
 380         if (efi_enabled)
 381                 efi_init();
 382
 383         vsmp_init();
 384
 385         dmi_scan_machine();
 386
 387         io_delay_init();
 388
 389 #ifdef CONFIG_SMP
 390         /* setup to use the early static init tables during kernel startup */
 391         x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
 392         x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
 393 #ifdef CONFIG_NUMA
 394         x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
 395 #endif
 396 #endif
 397
 398 #ifdef CONFIG_ACPI
 399         /*
 400          * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
 401          * Call this early for SRAT node setup.
 402          */
 403         acpi_boot_table_init();
 404 #endif
 405
 406         /* How many end-of-memory variables you have, grandma! */
 407         max_low_pfn = end_pfn;
 408         max_pfn = end_pfn;
 409         high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
 410
 411         /* Remove active ranges so rediscovery with NUMA-awareness happens */
 412         remove_all_active_ranges();
 413
 414 #ifdef CONFIG_ACPI_NUMA
 415         /*
 416          * Parse SRAT to discover nodes.
 417          */
 418         acpi_numa_init();
 419 #endif
 420
 421 #ifdef CONFIG_NUMA
 422         numa_initmem_init(0, end_pfn);
 423 #else
 424         contig_initmem_init(0, end_pfn);
 425 #endif
 426
 427         dma32_reserve_bootmem();
 428
 429 #ifdef CONFIG_ACPI_SLEEP
 430         /*
 431          * Reserve low memory region for sleep support.
 432          */
 433        acpi_reserve_bootmem();
 434 #endif
 435
 436         if (efi_enabled)
 437                 efi_reserve_bootmem();
 438
 439        /*
 440         * Find and reserve possible boot-time SMP configuration:
 441         */
 442         find_smp_config();
 443 #ifdef CONFIG_BLK_DEV_INITRD
 444         if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
 445                 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
 446                 unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
 447                 unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
 448                 unsigned long end_of_mem    = end_pfn << PAGE_SHIFT;
 449
 450                 if (ramdisk_end <= end_of_mem) {
 451                         /*
 452                          * don't need to reserve again, already reserved early
 453                          * in x86_64_start_kernel, and early_res_to_bootmem
 454                          * convert that to reserved in bootmem
 455                          */
 456                         initrd_start = ramdisk_image + PAGE_OFFSET;
 457                         initrd_end = initrd_start+ramdisk_size;
 458                 } else {
 459                         free_bootmem(ramdisk_image, ramdisk_size);
 460                         printk(KERN_ERR "initrd extends beyond end of memory "
 461                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 462                                ramdisk_end, end_of_mem);
 463                         initrd_start = 0;
 464                 }
 465         }
 466 #endif
 467         reserve_crashkernel();
 468
 469         reserve_ibft_region();
 470
 471         paging_init();
 472         map_vsyscall();
 473
 474         early_quirks();
 475
 476 #ifdef CONFIG_ACPI
 477         /*
 478          * Read APIC and some other early information from ACPI tables.
 479          */
 480         acpi_boot_init();
 481 #endif
 482
 483         init_cpu_to_node();
 484
 485         /*
 486          * get boot-time SMP configuration:
 487          */
 488         if (smp_found_config)
 489                 get_smp_config();
 490         init_apic_mappings();
 491         ioapic_init_mappings();
 492
 493         /*
 494          * We trust e820 completely. No explicit ROM probing in memory.
 495          */
 496         e820_reserve_resources();
 497         e820_mark_nosave_regions();
 498
 499         /* request I/O space for devices used on all i[345]86 PCs */
 500         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 501                 request_resource(&ioport_resource, &standard_io_resources[i]);
 502
 503         e820_setup_gap();
 504
 505 #ifdef CONFIG_VT
 506 #if defined(CONFIG_VGA_CONSOLE)
 507         if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
 508                 conswitchp = &vga_con;
 509 #elif defined(CONFIG_DUMMY_CONSOLE)
 510         conswitchp = &dummy_con;
 511 #endif
 512 #endif
 513 }
 514
 515 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 516 {
 517         unsigned int *v;
 518
 519         if (c->extended_cpuid_level < 0x80000004)
 520                 return 0;
 521
 522         v = (unsigned int *) c->x86_model_id;
 523         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 524         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 525         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 526         c->x86_model_id[48] = 0;
 527         return 1;
 528 }
 529
 530
 531 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 532 {
 533         unsigned int n, dummy, eax, ebx, ecx, edx;
 534
 535         n = c->extended_cpuid_level;
 536
 537         if (n >= 0x80000005) {
 538                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 539                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
 540                        "D cache %dK (%d bytes/line)\n",
 541                        edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 542                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 543                 /* On K8 L1 TLB is inclusive, so don't count it */
 544                 c->x86_tlbsize = 0;
 545         }
 546
 547         if (n >= 0x80000006) {
 548                 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 549                 ecx = cpuid_ecx(0x80000006);
 550                 c->x86_cache_size = ecx >> 16;
 551                 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 552
 553                 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 554                 c->x86_cache_size, ecx & 0xFF);
 555         }
 556         if (n >= 0x80000008) {
 557                 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
 558                 c->x86_virt_bits = (eax >> 8) & 0xff;
 559                 c->x86_phys_bits = eax & 0xff;
 560         }
 561 }
 562
 563 #ifdef CONFIG_NUMA
 564 static int __cpuinit nearby_node(int apicid)
 565 {
 566         int i, node;
 567
 568         for (i = apicid - 1; i >= 0; i--) {
 569                 node = apicid_to_node[i];
 570                 if (node != NUMA_NO_NODE && node_online(node))
 571                         return node;
 572         }
 573         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
 574                 node = apicid_to_node[i];
 575                 if (node != NUMA_NO_NODE && node_online(node))
 576                         return node;
 577         }
 578         return first_node(node_online_map); /* Shouldn't happen */
 579 }
 580 #endif
 581
 582 #ifdef CONFIG_PCI_MMCONFIG
 583 struct pci_hostbridge_probe {
 584         u32 bus;
 585         u32 slot;
 586         u32 vendor;
 587         u32 device;
 588 };
 589
 590 static u64 __cpuinitdata fam10h_pci_mmconf_base;
 591 static int __cpuinitdata fam10h_pci_mmconf_base_status;
 592
 593 static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
 594         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
 595         { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
 596 };
 597
 598 struct range {
 599         u64 start;
 600         u64 end;
 601 };
 602
 603 static int __cpuinit cmp_range(const void *x1, const void *x2)
 604 {
 605         const struct range *r1 = x1;
 606         const struct range *r2 = x2;
 607         int start1, start2;
 608
 609         start1 = r1->start >> 32;
 610         start2 = r2->start >> 32;
 611
 612         return start1 - start2;
 613 }
 614
 615 /*[47:0] */
 616 /* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */
 617 #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
 618 #define BASE_VALID(b) ((b != (0xfdULL << 32)) && (b != (0xfeULL << 32)))
 619 static void __cpuinit get_fam10h_pci_mmconf_base(void)
 620 {
 621         int i;
 622         unsigned bus;
 623         unsigned slot;
 624         int found;
 625
 626         u64 val;
 627         u32 address;
 628         u64 tom2;
 629         u64 base = FAM10H_PCI_MMCONF_BASE;
 630
 631         int hi_mmio_num;
 632         struct range range[8];
 633
 634         /* only try to get setting from BSP */
 635         /* -1 or 1 */
 636         if (fam10h_pci_mmconf_base_status)
 637                 return;
 638
 639         if (!early_pci_allowed())
 640                 goto fail;
 641
 642         found = 0;
 643         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
 644                 u32 id;
 645                 u16 device;
 646                 u16 vendor;
 647
 648                 bus = pci_probes[i].bus;
 649                 slot = pci_probes[i].slot;
 650                 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
 651
 652                 vendor = id & 0xffff;
 653                 device = (id>>16) & 0xffff;
 654                 if (pci_probes[i].vendor == vendor &&
 655                     pci_probes[i].device == device) {
 656                         found = 1;
 657                         break;
 658                 }
 659         }
 660
 661         if (!found)
 662                 goto fail;
 663
 664         /* SYS_CFG */
 665         address = MSR_K8_SYSCFG;
 666         rdmsrl(address, val);
 667
 668         /* TOP_MEM2 is not enabled? */
 669         if (!(val & (1<<21))) {
 670                 tom2 = 0;
 671         } else {
 672                 /* TOP_MEM2 */
 673                 address = MSR_K8_TOP_MEM2;
 674                 rdmsrl(address, val);
 675                 tom2 = val & (0xffffULL<<32);
 676         }
 677
 678         if (base <= tom2)
 679                 base = tom2 + (1ULL<<32);
 680
 681         /*
 682          * need to check if the range is in the high mmio range that is
 683          * above 4G
 684          */
 685         hi_mmio_num = 0;
 686         for (i = 0; i < 8; i++) {
 687                 u32 reg;
 688                 u64 start;
 689                 u64 end;
 690                 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
 691                 if (!(reg & 3))
 692                         continue;
 693
 694                 start = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
 695                 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
 696                 end = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
 697
 698                 if (!end)
 699                         continue;
 700
 701                 range[hi_mmio_num].start = start;
 702                 range[hi_mmio_num].end = end;
 703                 hi_mmio_num++;
 704         }
 705
 706         if (!hi_mmio_num)
 707                 goto out;
 708
 709         /* sort the range */
 710         sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
 711
 712         if (range[hi_mmio_num - 1].end < base)
 713                 goto out;
 714         if (range[0].start > base)
 715                 goto out;
 716
 717         /* need to find one window */
 718         base = range[0].start - (1ULL << 32);
 719         if ((base > tom2) && BASE_VALID(base))
 720                 goto out;
 721         base = range[hi_mmio_num - 1].end + (1ULL << 32);
 722         if ((base > tom2) && BASE_VALID(base))
 723                 goto out;
 724         /* need to find window between ranges */
 725         if (hi_mmio_num > 1)
 726         for (i = 0; i < hi_mmio_num - 1; i++) {
 727                 if (range[i + 1].start > (range[i].end + (1ULL << 32))) {
 728                         base = range[i].end + (1ULL << 32);
 729                         if ((base > tom2) && BASE_VALID(base))
 730                                 goto out;
 731                 }
 732         }
 733
 734 fail:
 735         fam10h_pci_mmconf_base_status = -1;
 736         return;
 737 out:
 738         fam10h_pci_mmconf_base = base;
 739         fam10h_pci_mmconf_base_status = 1;
 740 }
 741 #endif
 742
 743 static void __cpuinit fam10h_check_enable_mmcfg(struct cpuinfo_x86 *c)
 744 {
 745 #ifdef CONFIG_PCI_MMCONFIG
 746         u64 val;
 747         u32 address;
 748
 749         address = MSR_FAM10H_MMIO_CONF_BASE;
 750         rdmsrl(address, val);
 751
 752         /* try to make sure that AP's setting is identical to BSP setting */
 753         if (val & FAM10H_MMIO_CONF_ENABLE) {
 754                 u64 base;
 755                 base = val & (0xffffULL << 32);
 756                 if (fam10h_pci_mmconf_base_status <= 0) {
 757                         fam10h_pci_mmconf_base = base;
 758                         fam10h_pci_mmconf_base_status = 1;
 759                         return;
 760                 } else if (fam10h_pci_mmconf_base ==  base)
 761                         return;
 762         }
 763
 764         /*
 765          * if it is not enabled, try to enable it and assume only one segment
 766          * with 256 buses
 767          */
 768         get_fam10h_pci_mmconf_base();
 769         if (fam10h_pci_mmconf_base_status <= 0)
 770                 return;
 771
 772         printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
 773         val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
 774              (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
 775         val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
 776                FAM10H_MMIO_CONF_ENABLE;
 777         wrmsrl(address, val);
 778 #endif
 779 }
 780
 781 /*
 782  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 783  * Assumes number of cores is a power of two.
 784  */
 785 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 786 {
 787 #ifdef CONFIG_SMP
 788         unsigned bits;
 789 #ifdef CONFIG_NUMA
 790         int cpu = smp_processor_id();
 791         int node = 0;
 792         unsigned apicid = hard_smp_processor_id();
 793 #endif
 794         bits = c->x86_coreid_bits;
 795
 796         /* Low order bits define the core id (index of core in socket) */
 797         c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
 798         /* Convert the initial APIC ID into the socket ID */
 799         c->phys_proc_id = c->initial_apicid >> bits;
 800
 801 #ifdef CONFIG_NUMA
 802         node = c->phys_proc_id;
 803         if (apicid_to_node[apicid] != NUMA_NO_NODE)
 804                 node = apicid_to_node[apicid];
 805         if (!node_online(node)) {
 806                 /* Two possibilities here:
 807                    - The CPU is missing memory and no node was created.
 808                    In that case try picking one from a nearby CPU
 809                    - The APIC IDs differ from the HyperTransport node IDs
 810                    which the K8 northbridge parsing fills in.
 811                    Assume they are all increased by a constant offset,
 812                    but in the same order as the HT nodeids.
 813                    If that doesn't result in a usable node fall back to the
 814                    path for the previous case.  */
 815
 816                 int ht_nodeid = c->initial_apicid;
 817
 818                 if (ht_nodeid >= 0 &&
 819                     apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
 820                         node = apicid_to_node[ht_nodeid];
 821                 /* Pick a nearby node */
 822                 if (!node_online(node))
 823                         node = nearby_node(apicid);
 824         }
 825         numa_set_node(cpu, node);
 826
 827         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 828 #endif
 829 #endif
 830 }
 831
 832 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 833 {
 834 #ifdef CONFIG_SMP
 835         unsigned bits, ecx;
 836
 837         /* Multi core CPU? */
 838         if (c->extended_cpuid_level < 0x80000008)
 839                 return;
 840
 841         ecx = cpuid_ecx(0x80000008);
 842
 843         c->x86_max_cores = (ecx & 0xff) + 1;
 844
 845         /* CPU telling us the core id bits shift? */
 846         bits = (ecx >> 12) & 0xF;
 847
 848         /* Otherwise recompute */
 849         if (bits == 0) {
 850                 while ((1 << bits) < c->x86_max_cores)
 851                         bits++;
 852         }
 853
 854         c->x86_coreid_bits = bits;
 855
 856 #endif
 857 }
 858
 859 #define ENABLE_C1E_MASK         0x18000000
 860 #define CPUID_PROCESSOR_SIGNATURE       1
 861 #define CPUID_XFAM              0x0ff00000
 862 #define CPUID_XFAM_K8           0x00000000
 863 #define CPUID_XFAM_10H          0x00100000
 864 #define CPUID_XFAM_11H          0x00200000
 865 #define CPUID_XMOD              0x000f0000
 866 #define CPUID_XMOD_REV_F        0x00040000
 867
 868 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
 869 static __cpuinit int amd_apic_timer_broken(void)
 870 {
 871         u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
 872
 873         switch (eax & CPUID_XFAM) {
 874         case CPUID_XFAM_K8:
 875                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
 876                         break;
 877         case CPUID_XFAM_10H:
 878         case CPUID_XFAM_11H:
 879                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
 880                 if (lo & ENABLE_C1E_MASK)
 881                         return 1;
 882                 break;
 883         default:
 884                 /* err on the side of caution */
 885                 return 1;
 886         }
 887         return 0;
 888 }
 889
 890 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 891 {
 892         early_init_amd_mc(c);
 893
 894         /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
 895         if (c->x86_power & (1<<8))
 896                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 897 }
 898
 899 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 900 {
 901         unsigned level;
 902
 903 #ifdef CONFIG_SMP
 904         unsigned long value;
 905
 906         /*
 907          * Disable TLB flush filter by setting HWCR.FFDIS on K8
 908          * bit 6 of msr C001_0015
 909          *
 910          * Errata 63 for SH-B3 steppings
 911          * Errata 122 for all steppings (F+ have it disabled by default)
 912          */
 913         if (c->x86 == 15) {
 914                 rdmsrl(MSR_K8_HWCR, value);
 915                 value |= 1 << 6;
 916                 wrmsrl(MSR_K8_HWCR, value);
 917         }
 918 #endif
 919
 920         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 921            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 922         clear_cpu_cap(c, 0*32+31);
 923
 924         /* On C+ stepping K8 rep microcode works well for copy/memset */
 925         level = cpuid_eax(1);
 926         if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
 927                              level >= 0x0f58))
 928                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 929         if (c->x86 == 0x10 || c->x86 == 0x11)
 930                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 931
 932         /* Enable workaround for FXSAVE leak */
 933         if (c->x86 >= 6)
 934                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 935
 936         level = get_model_name(c);
 937         if (!level) {
 938                 switch (c->x86) {
 939                 case 15:
 940                         /* Should distinguish Models here, but this is only
 941                            a fallback anyways. */
 942                         strcpy(c->x86_model_id, "Hammer");
 943                         break;
 944                 }
 945         }
 946         display_cacheinfo(c);
 947
 948         /* Multi core CPU? */
 949         if (c->extended_cpuid_level >= 0x80000008)
 950                 amd_detect_cmp(c);
 951
 952         if (c->extended_cpuid_level >= 0x80000006 &&
 953                 (cpuid_edx(0x80000006) & 0xf000))
 954                 num_cache_leaves = 4;
 955         else
 956                 num_cache_leaves = 3;
 957
 958         if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
 959                 set_cpu_cap(c, X86_FEATURE_K8);
 960
 961         /* MFENCE stops RDTSC speculation */
 962         set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 963
 964         if (c->x86 == 0x10)
 965                 fam10h_check_enable_mmcfg(c);
 966
 967         if (amd_apic_timer_broken())
 968                 disable_apic_timer = 1;
 969
 970         if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
 971                 unsigned long long tseg;
 972
 973                 /*
 974                  * Split up direct mapping around the TSEG SMM area.
 975                  * Don't do it for gbpages because there seems very little
 976                  * benefit in doing so.
 977                  */
 978                 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
 979                 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
 980                         set_memory_4k((unsigned long)__va(tseg), 1);
 981         }
 982 }
 983
 984 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 985 {
 986 #ifdef CONFIG_SMP
 987         u32 eax, ebx, ecx, edx;
 988         int index_msb, core_bits;
 989
 990         cpuid(1, &eax, &ebx, &ecx, &edx);
 991
 992
 993         if (!cpu_has(c, X86_FEATURE_HT))
 994                 return;
 995         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 996                 goto out;
 997
 998         smp_num_siblings = (ebx & 0xff0000) >> 16;
 999
1000         if (smp_num_siblings == 1) {
1001                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
1002         } else if (smp_num_siblings > 1) {
1003
1004                 if (smp_num_siblings > NR_CPUS) {
1005                         printk(KERN_WARNING "CPU: Unsupported number of "
1006                                "siblings %d", smp_num_siblings);
1007                         smp_num_siblings = 1;
1008                         return;
1009                 }
1010
1011                 index_msb = get_count_order(smp_num_siblings);
1012                 c->phys_proc_id = phys_pkg_id(index_msb);
1013
1014                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
1015
1016                 index_msb = get_count_order(smp_num_siblings);
1017
1018                 core_bits = get_count_order(c->x86_max_cores);
1019
1020                 c->cpu_core_id = phys_pkg_id(index_msb) &
1021                                                ((1 << core_bits) - 1);
1022         }
1023 out:
1024         if ((c->x86_max_cores * smp_num_siblings) > 1) {
1025                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
1026                        c->phys_proc_id);
1027                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
1028                        c->cpu_core_id);
1029         }
1030
1031 #endif
1032 }
1033
1034 /*
1035  * find out the number of processor cores on the die
1036  */
1037 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
1038 {
1039         unsigned int eax, t;
1040
1041         if (c->cpuid_level < 4)
1042                 return 1;
1043
1044         cpuid_count(4, 0, &eax, &t, &t, &t);
1045
1046         if (eax & 0x1f)
1047                 return ((eax >> 26) + 1);
1048         else
1049                 return 1;
1050 }
1051
1052 static void __cpuinit srat_detect_node(void)
1053 {
1054 #ifdef CONFIG_NUMA
1055         unsigned node;
1056         int cpu = smp_processor_id();
1057         int apicid = hard_smp_processor_id();
1058
1059         /* Don't do the funky fallback heuristics the AMD version employs
1060            for now. */
1061         node = apicid_to_node[apicid];
1062         if (node == NUMA_NO_NODE || !node_online(node))
1063                 node = first_node(node_online_map);
1064         numa_set_node(cpu, node);
1065
1066         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
1067 #endif
1068 }
1069
1070 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
1071 {
1072         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
1073             (c->x86 == 0x6 && c->x86_model >= 0x0e))
1074                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
1075 }
1076
1077 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1078 {
1079         /* Cache sizes */
1080         unsigned n;
1081
1082         init_intel_cacheinfo(c);
1083         if (c->cpuid_level > 9) {
1084                 unsigned eax = cpuid_eax(10);
1085                 /* Check for version and the number of counters */
1086                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
1087                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
1088         }
1089
1090         if (cpu_has_ds) {
1091                 unsigned int l1, l2;
1092                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
1093                 if (!(l1 & (1<<11)))
1094                         set_cpu_cap(c, X86_FEATURE_BTS);
1095                 if (!(l1 & (1<<12)))
1096                         set_cpu_cap(c, X86_FEATURE_PEBS);
1097         }
1098
1099
1100         if (cpu_has_bts)
1101                 ds_init_intel(c);
1102
1103         n = c->extended_cpuid_level;
1104         if (n >= 0x80000008) {
1105                 unsigned eax = cpuid_eax(0x80000008);
1106                 c->x86_virt_bits = (eax >> 8) & 0xff;
1107                 c->x86_phys_bits = eax & 0xff;
1108                 /* CPUID workaround for Intel 0F34 CPU */
1109                 if (c->x86_vendor == X86_VENDOR_INTEL &&
1110                     c->x86 == 0xF && c->x86_model == 0x3 &&
1111                     c->x86_mask == 0x4)
1112                         c->x86_phys_bits = 36;
1113         }
1114
1115         if (c->x86 == 15)
1116                 c->x86_cache_alignment = c->x86_clflush_size * 2;
1117         if (c->x86 == 6)
1118                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1119         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1120         c->x86_max_cores = intel_num_cpu_cores(c);
1121
1122         srat_detect_node();
1123 }
1124
1125 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
1126 {
1127         if (c->x86 == 0x6 && c->x86_model >= 0xf)
1128                 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
1129 }
1130
1131 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
1132 {
1133         /* Cache sizes */
1134         unsigned n;
1135
1136         n = c->extended_cpuid_level;
1137         if (n >= 0x80000008) {
1138                 unsigned eax = cpuid_eax(0x80000008);
1139                 c->x86_virt_bits = (eax >> 8) & 0xff;
1140                 c->x86_phys_bits = eax & 0xff;
1141         }
1142
1143         if (c->x86 == 0x6 && c->x86_model >= 0xf) {
1144                 c->x86_cache_alignment = c->x86_clflush_size * 2;
1145                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
1146                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1147         }
1148         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1149 }
1150
1151 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1152 {
1153         char *v = c->x86_vendor_id;
1154
1155         if (!strcmp(v, "AuthenticAMD"))
1156                 c->x86_vendor = X86_VENDOR_AMD;
1157         else if (!strcmp(v, "GenuineIntel"))
1158                 c->x86_vendor = X86_VENDOR_INTEL;
1159         else if (!strcmp(v, "CentaurHauls"))
1160                 c->x86_vendor = X86_VENDOR_CENTAUR;
1161         else
1162                 c->x86_vendor = X86_VENDOR_UNKNOWN;
1163 }
1164
1165 /* Do some early cpuid on the boot CPU to get some parameter that are
1166    needed before check_bugs. Everything advanced is in identify_cpu
1167    below. */
1168 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1169 {
1170         u32 tfms, xlvl;
1171
1172         c->loops_per_jiffy = loops_per_jiffy;
1173         c->x86_cache_size = -1;
1174         c->x86_vendor = X86_VENDOR_UNKNOWN;
1175         c->x86_model = c->x86_mask = 0; /* So far unknown... */
1176         c->x86_vendor_id[0] = '\0'; /* Unset */
1177         c->x86_model_id[0] = '\0';  /* Unset */
1178         c->x86_clflush_size = 64;
1179         c->x86_cache_alignment = c->x86_clflush_size;
1180         c->x86_max_cores = 1;
1181         c->x86_coreid_bits = 0;
1182         c->extended_cpuid_level = 0;
1183         memset(&c->x86_capability, 0, sizeof c->x86_capability);
1184
1185         /* Get vendor name */
1186         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1187               (unsigned int *)&c->x86_vendor_id[0],
1188               (unsigned int *)&c->x86_vendor_id[8],
1189               (unsigned int *)&c->x86_vendor_id[4]);
1190
1191         get_cpu_vendor(c);
1192
1193         /* Initialize the standard set of capabilities */
1194         /* Note that the vendor-specific code below might override */
1195
1196         /* Intel-defined flags: level 0x00000001 */
1197         if (c->cpuid_level >= 0x00000001) {
1198                 __u32 misc;
1199                 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1200                       &c->x86_capability[0]);
1201                 c->x86 = (tfms >> 8) & 0xf;
1202                 c->x86_model = (tfms >> 4) & 0xf;
1203                 c->x86_mask = tfms & 0xf;
1204                 if (c->x86 == 0xf)
1205                         c->x86 += (tfms >> 20) & 0xff;
1206                 if (c->x86 >= 0x6)
1207                         c->x86_model += ((tfms >> 16) & 0xF) << 4;
1208                 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1209                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1210         } else {
1211                 /* Have CPUID level 0 only - unheard of */
1212                 c->x86 = 4;
1213         }
1214
1215         c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1216 #ifdef CONFIG_SMP
1217         c->phys_proc_id = c->initial_apicid;
1218 #endif
1219         /* AMD-defined flags: level 0x80000001 */
1220         xlvl = cpuid_eax(0x80000000);
1221         c->extended_cpuid_level = xlvl;
1222         if ((xlvl & 0xffff0000) == 0x80000000) {
1223                 if (xlvl >= 0x80000001) {
1224                         c->x86_capability[1] = cpuid_edx(0x80000001);
1225                         c->x86_capability[6] = cpuid_ecx(0x80000001);
1226                 }
1227                 if (xlvl >= 0x80000004)
1228                         get_model_name(c); /* Default name */
1229         }
1230
1231         /* Transmeta-defined flags: level 0x80860001 */
1232         xlvl = cpuid_eax(0x80860000);
1233         if ((xlvl & 0xffff0000) == 0x80860000) {
1234                 /* Don't set x86_cpuid_level here for now to not confuse. */
1235                 if (xlvl >= 0x80860001)
1236                         c->x86_capability[2] = cpuid_edx(0x80860001);
1237         }
1238
1239         c->extended_cpuid_level = cpuid_eax(0x80000000);
1240         if (c->extended_cpuid_level >= 0x80000007)
1241                 c->x86_power = cpuid_edx(0x80000007);
1242
1243
1244         clear_cpu_cap(c, X86_FEATURE_PAT);
1245
1246         switch (c->x86_vendor) {
1247         case X86_VENDOR_AMD:
1248                 early_init_amd(c);
1249                 if (c->x86 >= 0xf && c->x86 <= 0x11)
1250                         set_cpu_cap(c, X86_FEATURE_PAT);
1251                 break;
1252         case X86_VENDOR_INTEL:
1253                 early_init_intel(c);
1254                 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
1255                         set_cpu_cap(c, X86_FEATURE_PAT);
1256                 break;
1257         case X86_VENDOR_CENTAUR:
1258                 early_init_centaur(c);
1259                 break;
1260         }
1261
1262 }
1263
1264 /*
1265  * This does the hard work of actually picking apart the CPU stuff...
1266  */
1267 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1268 {
1269         int i;
1270
1271         early_identify_cpu(c);
1272
1273         init_scattered_cpuid_features(c);
1274
1275         c->apicid = phys_pkg_id(0);
1276
1277         /*
1278          * Vendor-specific initialization.  In this section we
1279          * canonicalize the feature flags, meaning if there are
1280          * features a certain CPU supports which CPUID doesn't
1281          * tell us, CPUID claiming incorrect flags, or other bugs,
1282          * we handle them here.
1283          *
1284          * At the end of this section, c->x86_capability better
1285          * indicate the features this CPU genuinely supports!
1286          */
1287         switch (c->x86_vendor) {
1288         case X86_VENDOR_AMD:
1289                 init_amd(c);
1290                 break;
1291
1292         case X86_VENDOR_INTEL:
1293                 init_intel(c);
1294                 break;
1295
1296         case X86_VENDOR_CENTAUR:
1297                 init_centaur(c);
1298                 break;
1299
1300         case X86_VENDOR_UNKNOWN:
1301         default:
1302                 display_cacheinfo(c);
1303                 break;
1304         }
1305
1306         detect_ht(c);
1307
1308         /*
1309          * On SMP, boot_cpu_data holds the common feature set between
1310          * all CPUs; so make sure that we indicate which features are
1311          * common between the CPUs.  The first time this routine gets
1312          * executed, c == &boot_cpu_data.
1313          */
1314         if (c != &boot_cpu_data) {
1315                 /* AND the already accumulated flags with these */
1316                 for (i = 0; i < NCAPINTS; i++)
1317                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1318         }
1319
1320         /* Clear all flags overriden by options */
1321         for (i = 0; i < NCAPINTS; i++)
1322                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1323
1324 #ifdef CONFIG_X86_MCE
1325         mcheck_init(c);
1326 #endif
1327         select_idle_routine(c);
1328
1329 #ifdef CONFIG_NUMA
1330         numa_add_cpu(smp_processor_id());
1331 #endif
1332
1333 }
1334
1335 void __cpuinit identify_boot_cpu(void)
1336 {
1337         identify_cpu(&boot_cpu_data);
1338 }
1339
1340 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1341 {
1342         BUG_ON(c == &boot_cpu_data);
1343         identify_cpu(c);
1344         mtrr_ap_init();
1345 }
1346
1347 static __init int setup_noclflush(char *arg)
1348 {
1349         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1350         return 1;
1351 }
1352 __setup("noclflush", setup_noclflush);
1353
1354 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1355 {
1356         if (c->x86_model_id[0])
1357                 printk(KERN_CONT "%s", c->x86_model_id);
1358
1359         if (c->x86_mask || c->cpuid_level >= 0)
1360                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1361         else
1362                 printk(KERN_CONT "\n");
1363 }
1364
1365 static __init int setup_disablecpuid(char *arg)
1366 {
1367         int bit;
1368         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1369                 setup_clear_cpu_cap(bit);
1370         else
1371                 return 0;
1372         return 1;
1373 }
1374 __setup("clearcpuid=", setup_disablecpuid);