arch/arm/mach-msm/timer.c

   1 /*
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clocksource.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <asm/mach/time.h>
  28 #include <asm/localtimer.h>
  29 #include <asm/sched_clock.h>
  30
  31 #include "common.h"
  32
  33 #define TIMER_MATCH_VAL         0x0000
  34 #define TIMER_COUNT_VAL         0x0004
  35 #define TIMER_ENABLE            0x0008
  36 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
  37 #define TIMER_ENABLE_EN                 BIT(0)
  38 #define TIMER_CLEAR             0x000C
  39 #define DGT_CLK_CTL             0x10
  40 #define DGT_CLK_CTL_DIV_4       0x3
  41
  42 #define GPT_HZ 32768
  43
  44 #define MSM_DGT_SHIFT 5
  45
  46 static void __iomem *event_base;
  47
  48 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  49 {
  50         struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
  51         /* Stop the timer tick */
  52         if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  53                 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  54                 ctrl &= ~TIMER_ENABLE_EN;
  55                 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  56         }
  57         evt->event_handler(evt);
  58         return IRQ_HANDLED;
  59 }
  60
  61 static int msm_timer_set_next_event(unsigned long cycles,
  62                                     struct clock_event_device *evt)
  63 {
  64         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  65
  66         writel_relaxed(0, event_base + TIMER_CLEAR);
  67         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
  68         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
  69         return 0;
  70 }
  71
  72 static void msm_timer_set_mode(enum clock_event_mode mode,
  73                               struct clock_event_device *evt)
  74 {
  75         u32 ctrl;
  76
  77         ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  78         ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
  79
  80         switch (mode) {
  81         case CLOCK_EVT_MODE_RESUME:
  82         case CLOCK_EVT_MODE_PERIODIC:
  83                 break;
  84         case CLOCK_EVT_MODE_ONESHOT:
  85                 /* Timer is enabled in set_next_event */
  86                 break;
  87         case CLOCK_EVT_MODE_UNUSED:
  88         case CLOCK_EVT_MODE_SHUTDOWN:
  89                 break;
  90         }
  91         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  92 }
  93
  94 static struct clock_event_device msm_clockevent = {
  95         .name           = "gp_timer",
  96         .features       = CLOCK_EVT_FEAT_ONESHOT,
  97         .rating         = 200,
  98         .set_next_event = msm_timer_set_next_event,
  99         .set_mode       = msm_timer_set_mode,
 100 };
 101
 102 static union {
 103         struct clock_event_device *evt;
 104         struct clock_event_device * __percpu *percpu_evt;
 105 } msm_evt;
 106
 107 static void __iomem *source_base;
 108
 109 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
 110 {
 111         return readl_relaxed(source_base + TIMER_COUNT_VAL);
 112 }
 113
 114 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
 115 {
 116         /*
 117          * Shift timer count down by a constant due to unreliable lower bits
 118          * on some targets.
 119          */
 120         return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
 121 }
 122
 123 static struct clocksource msm_clocksource = {
 124         .name   = "dg_timer",
 125         .rating = 300,
 126         .read   = msm_read_timer_count,
 127         .mask   = CLOCKSOURCE_MASK(32),
 128         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 129 };
 130
 131 #ifdef CONFIG_LOCAL_TIMERS
 132 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
 133 {
 134         /* Use existing clock_event for cpu 0 */
 135         if (!smp_processor_id())
 136                 return 0;
 137
 138         writel_relaxed(0, event_base + TIMER_ENABLE);
 139         writel_relaxed(0, event_base + TIMER_CLEAR);
 140         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
 141         evt->irq = msm_clockevent.irq;
 142         evt->name = "local_timer";
 143         evt->features = msm_clockevent.features;
 144         evt->rating = msm_clockevent.rating;
 145         evt->set_mode = msm_timer_set_mode;
 146         evt->set_next_event = msm_timer_set_next_event;
 147
 148         *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
 149         clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
 150         enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
 151         return 0;
 152 }
 153
 154 static void msm_local_timer_stop(struct clock_event_device *evt)
 155 {
 156         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 157         disable_percpu_irq(evt->irq);
 158 }
 159
 160 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
 161         .setup  = msm_local_timer_setup,
 162         .stop   = msm_local_timer_stop,
 163 };
 164 #endif /* CONFIG_LOCAL_TIMERS */
 165
 166 static notrace u32 msm_sched_clock_read(void)
 167 {
 168         return msm_clocksource.read(&msm_clocksource);
 169 }
 170
 171 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
 172                                   bool percpu)
 173 {
 174         struct clock_event_device *ce = &msm_clockevent;
 175         struct clocksource *cs = &msm_clocksource;
 176         int res;
 177
 178         writel_relaxed(0, event_base + TIMER_ENABLE);
 179         writel_relaxed(0, event_base + TIMER_CLEAR);
 180         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
 181         ce->cpumask = cpumask_of(0);
 182         ce->irq = irq;
 183
 184         clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
 185         if (percpu) {
 186                 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
 187                 if (!msm_evt.percpu_evt) {
 188                         pr_err("memory allocation failed for %s\n", ce->name);
 189                         goto err;
 190                 }
 191                 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
 192                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
 193                                          ce->name, msm_evt.percpu_evt);
 194                 if (!res) {
 195                         enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
 196 #ifdef CONFIG_LOCAL_TIMERS
 197                         local_timer_register(&msm_local_timer_ops);
 198 #endif
 199                 }
 200         } else {
 201                 msm_evt.evt = ce;
 202                 res = request_irq(ce->irq, msm_timer_interrupt,
 203                                   IRQF_TIMER | IRQF_NOBALANCING |
 204                                   IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
 205         }
 206
 207         if (res)
 208                 pr_err("request_irq failed for %s\n", ce->name);
 209 err:
 210         writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
 211         res = clocksource_register_hz(cs, dgt_hz);
 212         if (res)
 213                 pr_err("clocksource_register failed\n");
 214         setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
 215 }
 216
 217 #ifdef CONFIG_OF
 218 static const struct of_device_id msm_timer_match[] __initconst = {
 219         { .compatible = "qcom,kpss-timer" },
 220         { .compatible = "qcom,scss-timer" },
 221         { },
 222 };
 223
 224 void __init msm_dt_timer_init(void)
 225 {
 226         struct device_node *np;
 227         u32 freq;
 228         int irq;
 229         struct resource res;
 230         u32 percpu_offset;
 231         void __iomem *base;
 232         void __iomem *cpu0_base;
 233
 234         np = of_find_matching_node(NULL, msm_timer_match);
 235         if (!np) {
 236                 pr_err("Can't find msm timer DT node\n");
 237                 return;
 238         }
 239
 240         base = of_iomap(np, 0);
 241         if (!base) {
 242                 pr_err("Failed to map event base\n");
 243                 return;
 244         }
 245
 246         /* We use GPT0 for the clockevent */
 247         irq = irq_of_parse_and_map(np, 1);
 248         if (irq <= 0) {
 249                 pr_err("Can't get irq\n");
 250                 return;
 251         }
 252
 253         /* We use CPU0's DGT for the clocksource */
 254         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
 255                 percpu_offset = 0;
 256
 257         if (of_address_to_resource(np, 0, &res)) {
 258                 pr_err("Failed to parse DGT resource\n");
 259                 return;
 260         }
 261
 262         cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
 263         if (!cpu0_base) {
 264                 pr_err("Failed to map source base\n");
 265                 return;
 266         }
 267
 268         if (of_property_read_u32(np, "clock-frequency", &freq)) {
 269                 pr_err("Unknown frequency\n");
 270                 return;
 271         }
 272         of_node_put(np);
 273
 274         event_base = base + 0x4;
 275         source_base = cpu0_base + 0x24;
 276         freq /= 4;
 277         writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
 278
 279         msm_timer_init(freq, 32, irq, !!percpu_offset);
 280 }
 281 #endif
 282
 283 static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source)
 284 {
 285         void __iomem *base;
 286
 287         base = ioremap(addr, SZ_256);
 288         if (!base) {
 289                 pr_err("Failed to map timer base\n");
 290                 return -ENOMEM;
 291         }
 292         event_base = base + event;
 293         source_base = base + source;
 294
 295         return 0;
 296 }
 297
 298 void __init msm7x01_timer_init(void)
 299 {
 300         struct clocksource *cs = &msm_clocksource;
 301
 302         if (msm_timer_map(0xc0100000, 0x0, 0x10))
 303                 return;
 304         cs->read = msm_read_timer_count_shift;
 305         cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
 306         /* 600 KHz */
 307         msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
 308                         false);
 309 }
 310
 311 void __init msm7x30_timer_init(void)
 312 {
 313         if (msm_timer_map(0xc0100000, 0x4, 0x24))
 314                 return;
 315         msm_timer_init(24576000 / 4, 32, 1, false);
 316 }
 317
 318 void __init qsd8x50_timer_init(void)
 319 {
 320         if (msm_timer_map(0xAC100000, 0x0, 0x10))
 321                 return;
 322         msm_timer_init(19200000 / 4, 32, 7, false);
 323 }