2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
19 /include/ "skeleton64.dtsi"
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada-370-xp";
34 compatible = "marvell,sheeva-v7";
43 compatible = "simple-bus";
44 interrupt-parent = <&mpic>;
45 ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
46 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
49 compatible = "simple-bus";
54 mpic: interrupt-controller@20000 {
55 compatible = "marvell,mpic";
56 #interrupt-cells = <1>;
61 coherency-fabric@20200 {
62 compatible = "marvell,coherency-fabric";
63 reg = <0x20200 0xb0>, <0x21810 0x1c>;
67 compatible = "snps,dw-apb-uart";
68 reg = <0x12000 0x100>;
75 compatible = "snps,dw-apb-uart";
76 reg = <0x12100 0x100>;
84 compatible = "marvell,armada-370-xp-timer";
85 reg = <0x20300 0x30>, <0x21040 0x30>;
86 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
87 clocks = <&coreclk 2>;
91 compatible = "marvell,orion-sata";
92 reg = <0xa0000 0x5000>;
94 clocks = <&gateclk 15>, <&gateclk 30>;
95 clock-names = "0", "1";
100 #address-cells = <1>;
102 compatible = "marvell,orion-mdio";
106 eth0: ethernet@70000 {
107 compatible = "marvell,armada-370-neta";
108 reg = <0x70000 0x4000>;
110 clocks = <&gateclk 4>;
114 eth1: ethernet@74000 {
115 compatible = "marvell,armada-370-neta";
116 reg = <0x74000 0x4000>;
118 clocks = <&gateclk 3>;
123 compatible = "marvell,mv64xxx-i2c";
124 reg = <0x11000 0x20>;
125 #address-cells = <1>;
129 clocks = <&coreclk 0>;
134 compatible = "marvell,mv64xxx-i2c";
135 reg = <0x11100 0x20>;
136 #address-cells = <1>;
140 clocks = <&coreclk 0>;
145 compatible = "marvell,orion-rtc";
146 reg = <0x10300 0x20>;
151 compatible = "marvell,orion-sdio";
152 reg = <0xd4000 0x200>;
154 clocks = <&gateclk 17>;
163 compatible = "marvell,orion-ehci";
164 reg = <0x50000 0x500>;
170 compatible = "marvell,orion-ehci";
171 reg = <0x51000 0x500>;
177 compatible = "marvell,orion-spi";
178 reg = <0x10600 0x28>;
179 #address-cells = <1>;
183 clocks = <&coreclk 0>;
188 compatible = "marvell,orion-spi";
189 reg = <0x10680 0x28>;
190 #address-cells = <1>;
194 clocks = <&coreclk 0>;
198 devbus-bootcs@10400 {
199 compatible = "marvell,mvebu-devbus";
201 #address-cells = <1>;
203 clocks = <&coreclk 0>;
208 compatible = "marvell,mvebu-devbus";
210 #address-cells = <1>;
212 clocks = <&coreclk 0>;
217 compatible = "marvell,mvebu-devbus";
219 #address-cells = <1>;
221 clocks = <&coreclk 0>;
226 compatible = "marvell,mvebu-devbus";
228 #address-cells = <1>;
230 clocks = <&coreclk 0>;
235 compatible = "marvell,mvebu-devbus";
237 #address-cells = <1>;
239 clocks = <&coreclk 0>;