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powerpc: Convert to new irq_* function names
[linux-2.6.git] / arch / powerpc / sysdev / mpic.c
blobf91c065bed5a21be3f1a7fd6e186a27d72b3e6de
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/irq.h>
36 #include <asm/machdep.h>
37 #include <asm/mpic.h>
38 #include <asm/smp.h>
39
40 #include "mpic.h"
41
42 #ifdef DEBUG
43 #define DBG(fmt...) printk(fmt)
44 #else
45 #define DBG(fmt...)
46 #endif
47
48 static struct mpic *mpics;
49 static struct mpic *mpic_primary;
50 static DEFINE_RAW_SPINLOCK(mpic_lock);
51
52 #ifdef CONFIG_PPC32 /* XXX for now */
53 #ifdef CONFIG_IRQ_ALL_CPUS
54 #define distribute_irqs (1)
55 #else
56 #define distribute_irqs (0)
57 #endif
58 #endif
59
60 #ifdef CONFIG_MPIC_WEIRD
61 static u32 mpic_infos[][MPIC_IDX_END] = {
62 [0] = { /* Original OpenPIC compatible MPIC */
63 MPIC_GREG_BASE,
64 MPIC_GREG_FEATURE_0,
65 MPIC_GREG_GLOBAL_CONF_0,
66 MPIC_GREG_VENDOR_ID,
67 MPIC_GREG_IPI_VECTOR_PRI_0,
68 MPIC_GREG_IPI_STRIDE,
69 MPIC_GREG_SPURIOUS,
70 MPIC_GREG_TIMER_FREQ,
71
72 MPIC_TIMER_BASE,
73 MPIC_TIMER_STRIDE,
74 MPIC_TIMER_CURRENT_CNT,
75 MPIC_TIMER_BASE_CNT,
76 MPIC_TIMER_VECTOR_PRI,
77 MPIC_TIMER_DESTINATION,
78
79 MPIC_CPU_BASE,
80 MPIC_CPU_STRIDE,
81 MPIC_CPU_IPI_DISPATCH_0,
82 MPIC_CPU_IPI_DISPATCH_STRIDE,
83 MPIC_CPU_CURRENT_TASK_PRI,
84 MPIC_CPU_WHOAMI,
85 MPIC_CPU_INTACK,
86 MPIC_CPU_EOI,
87 MPIC_CPU_MCACK,
88
89 MPIC_IRQ_BASE,
90 MPIC_IRQ_STRIDE,
91 MPIC_IRQ_VECTOR_PRI,
92 MPIC_VECPRI_VECTOR_MASK,
93 MPIC_VECPRI_POLARITY_POSITIVE,
94 MPIC_VECPRI_POLARITY_NEGATIVE,
95 MPIC_VECPRI_SENSE_LEVEL,
96 MPIC_VECPRI_SENSE_EDGE,
97 MPIC_VECPRI_POLARITY_MASK,
98 MPIC_VECPRI_SENSE_MASK,
99 MPIC_IRQ_DESTINATION
100 },
101 [1] = { /* Tsi108/109 PIC */
102 TSI108_GREG_BASE,
103 TSI108_GREG_FEATURE_0,
104 TSI108_GREG_GLOBAL_CONF_0,
105 TSI108_GREG_VENDOR_ID,
106 TSI108_GREG_IPI_VECTOR_PRI_0,
107 TSI108_GREG_IPI_STRIDE,
108 TSI108_GREG_SPURIOUS,
109 TSI108_GREG_TIMER_FREQ,
110
111 TSI108_TIMER_BASE,
112 TSI108_TIMER_STRIDE,
113 TSI108_TIMER_CURRENT_CNT,
114 TSI108_TIMER_BASE_CNT,
115 TSI108_TIMER_VECTOR_PRI,
116 TSI108_TIMER_DESTINATION,
117
118 TSI108_CPU_BASE,
119 TSI108_CPU_STRIDE,
120 TSI108_CPU_IPI_DISPATCH_0,
121 TSI108_CPU_IPI_DISPATCH_STRIDE,
122 TSI108_CPU_CURRENT_TASK_PRI,
123 TSI108_CPU_WHOAMI,
124 TSI108_CPU_INTACK,
125 TSI108_CPU_EOI,
126 TSI108_CPU_MCACK,
127
128 TSI108_IRQ_BASE,
129 TSI108_IRQ_STRIDE,
130 TSI108_IRQ_VECTOR_PRI,
131 TSI108_VECPRI_VECTOR_MASK,
132 TSI108_VECPRI_POLARITY_POSITIVE,
133 TSI108_VECPRI_POLARITY_NEGATIVE,
134 TSI108_VECPRI_SENSE_LEVEL,
135 TSI108_VECPRI_SENSE_EDGE,
136 TSI108_VECPRI_POLARITY_MASK,
137 TSI108_VECPRI_SENSE_MASK,
138 TSI108_IRQ_DESTINATION
139 },
140 };
141
142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
143
144 #else /* CONFIG_MPIC_WEIRD */
145
146 #define MPIC_INFO(name) MPIC_##name
147
148 #endif /* CONFIG_MPIC_WEIRD */
149
150 static inline unsigned int mpic_processor_id(struct mpic *mpic)
151 {
152 unsigned int cpu = 0;
153
154 if (mpic->flags & MPIC_PRIMARY)
155 cpu = hard_smp_processor_id();
156
157 return cpu;
158 }
159
160 /*
161 * Register accessor functions
162 */
163
164
165 static inline u32 _mpic_read(enum mpic_reg_type type,
166 struct mpic_reg_bank *rb,
167 unsigned int reg)
168 {
169 switch(type) {
170 #ifdef CONFIG_PPC_DCR
171 case mpic_access_dcr:
172 return dcr_read(rb->dhost, reg);
173 #endif
174 case mpic_access_mmio_be:
175 return in_be32(rb->base + (reg >> 2));
176 case mpic_access_mmio_le:
177 default:
178 return in_le32(rb->base + (reg >> 2));
179 }
180 }
181
182 static inline void _mpic_write(enum mpic_reg_type type,
183 struct mpic_reg_bank *rb,
184 unsigned int reg, u32 value)
185 {
186 switch(type) {
187 #ifdef CONFIG_PPC_DCR
188 case mpic_access_dcr:
189 dcr_write(rb->dhost, reg, value);
190 break;
191 #endif
192 case mpic_access_mmio_be:
193 out_be32(rb->base + (reg >> 2), value);
194 break;
195 case mpic_access_mmio_le:
196 default:
197 out_le32(rb->base + (reg >> 2), value);
198 break;
199 }
200 }
201
202 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
203 {
204 enum mpic_reg_type type = mpic->reg_type;
205 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
206 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
207
208 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
209 type = mpic_access_mmio_be;
210 return _mpic_read(type, &mpic->gregs, offset);
211 }
212
213 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
214 {
215 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
216 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
217
218 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
219 }
220
221 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
222 {
223 unsigned int cpu = mpic_processor_id(mpic);
224
225 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
226 }
227
228 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
229 {
230 unsigned int cpu = mpic_processor_id(mpic);
231
232 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
233 }
234
235 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
236 {
237 unsigned int isu = src_no >> mpic->isu_shift;
238 unsigned int idx = src_no & mpic->isu_mask;
239 unsigned int val;
240
241 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
242 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
243 #ifdef CONFIG_MPIC_BROKEN_REGREAD
244 if (reg == 0)
245 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
246 mpic->isu_reg0_shadow[src_no];
247 #endif
248 return val;
249 }
250
251 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
252 unsigned int reg, u32 value)
253 {
254 unsigned int isu = src_no >> mpic->isu_shift;
255 unsigned int idx = src_no & mpic->isu_mask;
256
257 _mpic_write(mpic->reg_type, &mpic->isus[isu],
258 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
259
260 #ifdef CONFIG_MPIC_BROKEN_REGREAD
261 if (reg == 0)
262 mpic->isu_reg0_shadow[src_no] =
263 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
264 #endif
265 }
266
267 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
268 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
269 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
270 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
271 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
272 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
273 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
274 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
275
276
277 /*
278 * Low level utility functions
279 */
280
281
282 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
283 struct mpic_reg_bank *rb, unsigned int offset,
284 unsigned int size)
285 {
286 rb->base = ioremap(phys_addr + offset, size);
287 BUG_ON(rb->base == NULL);
288 }
289
290 #ifdef CONFIG_PPC_DCR
291 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
292 struct mpic_reg_bank *rb,
293 unsigned int offset, unsigned int size)
294 {
295 const u32 *dbasep;
296
297 dbasep = of_get_property(node, "dcr-reg", NULL);
298
299 rb->dhost = dcr_map(node, *dbasep + offset, size);
300 BUG_ON(!DCR_MAP_OK(rb->dhost));
301 }
302
303 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
304 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
305 unsigned int offset, unsigned int size)
306 {
307 if (mpic->flags & MPIC_USES_DCR)
308 _mpic_map_dcr(mpic, node, rb, offset, size);
309 else
310 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
311 }
312 #else /* CONFIG_PPC_DCR */
313 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
314 #endif /* !CONFIG_PPC_DCR */
315
316
317
318 /* Check if we have one of those nice broken MPICs with a flipped endian on
319 * reads from IPI registers
320 */
321 static void __init mpic_test_broken_ipi(struct mpic *mpic)
322 {
323 u32 r;
324
325 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
326 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
327
328 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
329 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
330 mpic->flags |= MPIC_BROKEN_IPI;
331 }
332 }
333
334 #ifdef CONFIG_MPIC_U3_HT_IRQS
335
336 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
337 * to force the edge setting on the MPIC and do the ack workaround.
338 */
339 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
340 {
341 if (source >= 128 || !mpic->fixups)
342 return 0;
343 return mpic->fixups[source].base != NULL;
344 }
345
346
347 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
348 {
349 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
350
351 if (fixup->applebase) {
352 unsigned int soff = (fixup->index >> 3) & ~3;
353 unsigned int mask = 1U << (fixup->index & 0x1f);
354 writel(mask, fixup->applebase + soff);
355 } else {
356 raw_spin_lock(&mpic->fixup_lock);
357 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
358 writel(fixup->data, fixup->base + 4);
359 raw_spin_unlock(&mpic->fixup_lock);
360 }
361 }
362
363 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
364 bool level)
365 {
366 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
367 unsigned long flags;
368 u32 tmp;
369
370 if (fixup->base == NULL)
371 return;
372
373 DBG("startup_ht_interrupt(0x%x) index: %d\n",
374 source, fixup->index);
375 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
376 /* Enable and configure */
377 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
378 tmp = readl(fixup->base + 4);
379 tmp &= ~(0x23U);
380 if (level)
381 tmp |= 0x22;
382 writel(tmp, fixup->base + 4);
383 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
384
385 #ifdef CONFIG_PM
386 /* use the lowest bit inverted to the actual HW,
387 * set if this fixup was enabled, clear otherwise */
388 mpic->save_data[source].fixup_data = tmp | 1;
389 #endif
390 }
391
392 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
393 {
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
395 unsigned long flags;
396 u32 tmp;
397
398 if (fixup->base == NULL)
399 return;
400
401 DBG("shutdown_ht_interrupt(0x%x)\n", source);
402
403 /* Disable */
404 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
405 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
406 tmp = readl(fixup->base + 4);
407 tmp |= 1;
408 writel(tmp, fixup->base + 4);
409 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
410
411 #ifdef CONFIG_PM
412 /* use the lowest bit inverted to the actual HW,
413 * set if this fixup was enabled, clear otherwise */
414 mpic->save_data[source].fixup_data = tmp & ~1;
415 #endif
416 }
417
418 #ifdef CONFIG_PCI_MSI
419 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
420 unsigned int devfn)
421 {
422 u8 __iomem *base;
423 u8 pos, flags;
424 u64 addr = 0;
425
426 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
427 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
428 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
429 if (id == PCI_CAP_ID_HT) {
430 id = readb(devbase + pos + 3);
431 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
432 break;
433 }
434 }
435
436 if (pos == 0)
437 return;
438
439 base = devbase + pos;
440
441 flags = readb(base + HT_MSI_FLAGS);
442 if (!(flags & HT_MSI_FLAGS_FIXED)) {
443 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
444 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
445 }
446
447 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
448 PCI_SLOT(devfn), PCI_FUNC(devfn),
449 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
450
451 if (!(flags & HT_MSI_FLAGS_ENABLE))
452 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
453 }
454 #else
455 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
456 unsigned int devfn)
457 {
458 return;
459 }
460 #endif
461
462 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
463 unsigned int devfn, u32 vdid)
464 {
465 int i, irq, n;
466 u8 __iomem *base;
467 u32 tmp;
468 u8 pos;
469
470 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
471 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
472 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
473 if (id == PCI_CAP_ID_HT) {
474 id = readb(devbase + pos + 3);
475 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
476 break;
477 }
478 }
479 if (pos == 0)
480 return;
481
482 base = devbase + pos;
483 writeb(0x01, base + 2);
484 n = (readl(base + 4) >> 16) & 0xff;
485
486 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
487 " has %d irqs\n",
488 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
489
490 for (i = 0; i <= n; i++) {
491 writeb(0x10 + 2 * i, base + 2);
492 tmp = readl(base + 4);
493 irq = (tmp >> 16) & 0xff;
494 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
495 /* mask it , will be unmasked later */
496 tmp |= 0x1;
497 writel(tmp, base + 4);
498 mpic->fixups[irq].index = i;
499 mpic->fixups[irq].base = base;
500 /* Apple HT PIC has a non-standard way of doing EOIs */
501 if ((vdid & 0xffff) == 0x106b)
502 mpic->fixups[irq].applebase = devbase + 0x60;
503 else
504 mpic->fixups[irq].applebase = NULL;
505 writeb(0x11 + 2 * i, base + 2);
506 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
507 }
508 }
509
510
511 static void __init mpic_scan_ht_pics(struct mpic *mpic)
512 {
513 unsigned int devfn;
514 u8 __iomem *cfgspace;
515
516 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
517
518 /* Allocate fixups array */
519 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
520 BUG_ON(mpic->fixups == NULL);
521
522 /* Init spinlock */
523 raw_spin_lock_init(&mpic->fixup_lock);
524
525 /* Map U3 config space. We assume all IO-APICs are on the primary bus
526 * so we only need to map 64kB.
527 */
528 cfgspace = ioremap(0xf2000000, 0x10000);
529 BUG_ON(cfgspace == NULL);
530
531 /* Now we scan all slots. We do a very quick scan, we read the header
532 * type, vendor ID and device ID only, that's plenty enough
533 */
534 for (devfn = 0; devfn < 0x100; devfn++) {
535 u8 __iomem *devbase = cfgspace + (devfn << 8);
536 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
537 u32 l = readl(devbase + PCI_VENDOR_ID);
538 u16 s;
539
540 DBG("devfn %x, l: %x\n", devfn, l);
541
542 /* If no device, skip */
543 if (l == 0xffffffff || l == 0x00000000 ||
544 l == 0x0000ffff || l == 0xffff0000)
545 goto next;
546 /* Check if is supports capability lists */
547 s = readw(devbase + PCI_STATUS);
548 if (!(s & PCI_STATUS_CAP_LIST))
549 goto next;
550
551 mpic_scan_ht_pic(mpic, devbase, devfn, l);
552 mpic_scan_ht_msi(mpic, devbase, devfn);
553
554 next:
555 /* next device, if function 0 */
556 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
557 devfn += 7;
558 }
559 }
560
561 #else /* CONFIG_MPIC_U3_HT_IRQS */
562
563 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
564 {
565 return 0;
566 }
567
568 static void __init mpic_scan_ht_pics(struct mpic *mpic)
569 {
570 }
571
572 #endif /* CONFIG_MPIC_U3_HT_IRQS */
573
574 #ifdef CONFIG_SMP
575 static int irq_choose_cpu(const struct cpumask *mask)
576 {
577 int cpuid;
578
579 if (cpumask_equal(mask, cpu_all_mask)) {
580 static int irq_rover = 0;
581 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
582 unsigned long flags;
583
584 /* Round-robin distribution... */
585 do_round_robin:
586 raw_spin_lock_irqsave(&irq_rover_lock, flags);
587
588 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
589 if (irq_rover >= nr_cpu_ids)
590 irq_rover = cpumask_first(cpu_online_mask);
591
592 cpuid = irq_rover;
593
594 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
595 } else {
596 cpuid = cpumask_first_and(mask, cpu_online_mask);
597 if (cpuid >= nr_cpu_ids)
598 goto do_round_robin;
599 }
600
601 return get_hard_smp_processor_id(cpuid);
602 }
603 #else
604 static int irq_choose_cpu(const struct cpumask *mask)
605 {
606 return hard_smp_processor_id();
607 }
608 #endif
609
610 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
611
612 /* Find an mpic associated with a given linux interrupt */
613 static struct mpic *mpic_find(unsigned int irq)
614 {
615 if (irq < NUM_ISA_INTERRUPTS)
616 return NULL;
617
618 return irq_get_chip_data(irq);
619 }
620
621 /* Determine if the linux irq is an IPI */
622 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
623 {
624 unsigned int src = mpic_irq_to_hw(irq);
625
626 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
627 }
628
629
630 /* Convert a cpu mask from logical to physical cpu numbers. */
631 static inline u32 mpic_physmask(u32 cpumask)
632 {
633 int i;
634 u32 mask = 0;
635
636 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
637 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
638 return mask;
639 }
640
641 #ifdef CONFIG_SMP
642 /* Get the mpic structure from the IPI number */
643 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
644 {
645 return irq_data_get_irq_chip_data(d);
646 }
647 #endif
648
649 /* Get the mpic structure from the irq number */
650 static inline struct mpic * mpic_from_irq(unsigned int irq)
651 {
652 return irq_get_chip_data(irq);
653 }
654
655 /* Get the mpic structure from the irq data */
656 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
657 {
658 return irq_data_get_irq_chip_data(d);
659 }
660
661 /* Send an EOI */
662 static inline void mpic_eoi(struct mpic *mpic)
663 {
664 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
665 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
666 }
667
668 /*
669 * Linux descriptor level callbacks
670 */
671
672
673 void mpic_unmask_irq(struct irq_data *d)
674 {
675 unsigned int loops = 100000;
676 struct mpic *mpic = mpic_from_irq_data(d);
677 unsigned int src = mpic_irq_to_hw(d->irq);
678
679 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
680
681 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
682 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
683 ~MPIC_VECPRI_MASK);
684 /* make sure mask gets to controller before we return to user */
685 do {
686 if (!loops--) {
687 printk(KERN_ERR "%s: timeout on hwirq %u\n",
688 __func__, src);
689 break;
690 }
691 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
692 }
693
694 void mpic_mask_irq(struct irq_data *d)
695 {
696 unsigned int loops = 100000;
697 struct mpic *mpic = mpic_from_irq_data(d);
698 unsigned int src = mpic_irq_to_hw(d->irq);
699
700 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
701
702 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
703 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
704 MPIC_VECPRI_MASK);
705
706 /* make sure mask gets to controller before we return to user */
707 do {
708 if (!loops--) {
709 printk(KERN_ERR "%s: timeout on hwirq %u\n",
710 __func__, src);
711 break;
712 }
713 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
714 }
715
716 void mpic_end_irq(struct irq_data *d)
717 {
718 struct mpic *mpic = mpic_from_irq_data(d);
719
720 #ifdef DEBUG_IRQ
721 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
722 #endif
723 /* We always EOI on end_irq() even for edge interrupts since that
724 * should only lower the priority, the MPIC should have properly
725 * latched another edge interrupt coming in anyway
726 */
727
728 mpic_eoi(mpic);
729 }
730
731 #ifdef CONFIG_MPIC_U3_HT_IRQS
732
733 static void mpic_unmask_ht_irq(struct irq_data *d)
734 {
735 struct mpic *mpic = mpic_from_irq_data(d);
736 unsigned int src = mpic_irq_to_hw(d->irq);
737
738 mpic_unmask_irq(d);
739
740 if (irqd_is_level_type(d))
741 mpic_ht_end_irq(mpic, src);
742 }
743
744 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
745 {
746 struct mpic *mpic = mpic_from_irq_data(d);
747 unsigned int src = mpic_irq_to_hw(d->irq);
748
749 mpic_unmask_irq(d);
750 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
751
752 return 0;
753 }
754
755 static void mpic_shutdown_ht_irq(struct irq_data *d)
756 {
757 struct mpic *mpic = mpic_from_irq_data(d);
758 unsigned int src = mpic_irq_to_hw(d->irq);
759
760 mpic_shutdown_ht_interrupt(mpic, src);
761 mpic_mask_irq(d);
762 }
763
764 static void mpic_end_ht_irq(struct irq_data *d)
765 {
766 struct mpic *mpic = mpic_from_irq_data(d);
767 unsigned int src = mpic_irq_to_hw(d->irq);
768
769 #ifdef DEBUG_IRQ
770 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
771 #endif
772 /* We always EOI on end_irq() even for edge interrupts since that
773 * should only lower the priority, the MPIC should have properly
774 * latched another edge interrupt coming in anyway
775 */
776
777 if (irqd_is_level_type(d))
778 mpic_ht_end_irq(mpic, src);
779 mpic_eoi(mpic);
780 }
781 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
782
783 #ifdef CONFIG_SMP
784
785 static void mpic_unmask_ipi(struct irq_data *d)
786 {
787 struct mpic *mpic = mpic_from_ipi(d);
788 unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0];
789
790 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
791 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
792 }
793
794 static void mpic_mask_ipi(struct irq_data *d)
795 {
796 /* NEVER disable an IPI... that's just plain wrong! */
797 }
798
799 static void mpic_end_ipi(struct irq_data *d)
800 {
801 struct mpic *mpic = mpic_from_ipi(d);
802
803 /*
804 * IPIs are marked IRQ_PER_CPU. This has the side effect of
805 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
806 * applying to them. We EOI them late to avoid re-entering.
807 * We mark IPI's with IRQF_DISABLED as they must run with
808 * irqs disabled.
809 */
810 mpic_eoi(mpic);
811 }
812
813 #endif /* CONFIG_SMP */
814
815 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
816 bool force)
817 {
818 struct mpic *mpic = mpic_from_irq_data(d);
819 unsigned int src = mpic_irq_to_hw(d->irq);
820
821 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
822 int cpuid = irq_choose_cpu(cpumask);
823
824 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
825 } else {
826 cpumask_var_t tmp;
827
828 alloc_cpumask_var(&tmp, GFP_KERNEL);
829
830 cpumask_and(tmp, cpumask, cpu_online_mask);
831
832 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
833 mpic_physmask(cpumask_bits(tmp)[0]));
834
835 free_cpumask_var(tmp);
836 }
837
838 return 0;
839 }
840
841 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
842 {
843 /* Now convert sense value */
844 switch(type & IRQ_TYPE_SENSE_MASK) {
845 case IRQ_TYPE_EDGE_RISING:
846 return MPIC_INFO(VECPRI_SENSE_EDGE) |
847 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
848 case IRQ_TYPE_EDGE_FALLING:
849 case IRQ_TYPE_EDGE_BOTH:
850 return MPIC_INFO(VECPRI_SENSE_EDGE) |
851 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
852 case IRQ_TYPE_LEVEL_HIGH:
853 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
854 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
855 case IRQ_TYPE_LEVEL_LOW:
856 default:
857 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
858 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
859 }
860 }
861
862 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
863 {
864 struct mpic *mpic = mpic_from_irq_data(d);
865 unsigned int src = mpic_irq_to_hw(d->irq);
866 unsigned int vecpri, vold, vnew;
867
868 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
869 mpic, d->irq, src, flow_type);
870
871 if (src >= mpic->irq_count)
872 return -EINVAL;
873
874 if (flow_type == IRQ_TYPE_NONE)
875 if (mpic->senses && src < mpic->senses_count)
876 flow_type = mpic->senses[src];
877 if (flow_type == IRQ_TYPE_NONE)
878 flow_type = IRQ_TYPE_LEVEL_LOW;
879
880 irqd_set_trigger_type(d, flow_type);
881
882 if (mpic_is_ht_interrupt(mpic, src))
883 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
884 MPIC_VECPRI_SENSE_EDGE;
885 else
886 vecpri = mpic_type_to_vecpri(mpic, flow_type);
887
888 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
889 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
890 MPIC_INFO(VECPRI_SENSE_MASK));
891 vnew |= vecpri;
892 if (vold != vnew)
893 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
894
895 return IRQ_SET_MASK_OK_NOCOPY;;
896 }
897
898 void mpic_set_vector(unsigned int virq, unsigned int vector)
899 {
900 struct mpic *mpic = mpic_from_irq(virq);
901 unsigned int src = mpic_irq_to_hw(virq);
902 unsigned int vecpri;
903
904 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
905 mpic, virq, src, vector);
906
907 if (src >= mpic->irq_count)
908 return;
909
910 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
911 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
912 vecpri |= vector;
913 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
914 }
915
916 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
917 {
918 struct mpic *mpic = mpic_from_irq(virq);
919 unsigned int src = mpic_irq_to_hw(virq);
920
921 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
922 mpic, virq, src, cpuid);
923
924 if (src >= mpic->irq_count)
925 return;
926
927 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
928 }
929
930 static struct irq_chip mpic_irq_chip = {
931 .irq_mask = mpic_mask_irq,
932 .irq_unmask = mpic_unmask_irq,
933 .irq_eoi = mpic_end_irq,
934 .irq_set_type = mpic_set_irq_type,
935 };
936
937 #ifdef CONFIG_SMP
938 static struct irq_chip mpic_ipi_chip = {
939 .irq_mask = mpic_mask_ipi,
940 .irq_unmask = mpic_unmask_ipi,
941 .irq_eoi = mpic_end_ipi,
942 };
943 #endif /* CONFIG_SMP */
944
945 #ifdef CONFIG_MPIC_U3_HT_IRQS
946 static struct irq_chip mpic_irq_ht_chip = {
947 .irq_startup = mpic_startup_ht_irq,
948 .irq_shutdown = mpic_shutdown_ht_irq,
949 .irq_mask = mpic_mask_irq,
950 .irq_unmask = mpic_unmask_ht_irq,
951 .irq_eoi = mpic_end_ht_irq,
952 .irq_set_type = mpic_set_irq_type,
953 };
954 #endif /* CONFIG_MPIC_U3_HT_IRQS */
955
956
957 static int mpic_host_match(struct irq_host *h, struct device_node *node)
958 {
959 /* Exact match, unless mpic node is NULL */
960 return h->of_node == NULL || h->of_node == node;
961 }
962
963 static int mpic_host_map(struct irq_host *h, unsigned int virq,
964 irq_hw_number_t hw)
965 {
966 struct mpic *mpic = h->host_data;
967 struct irq_chip *chip;
968
969 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
970
971 if (hw == mpic->spurious_vec)
972 return -EINVAL;
973 if (mpic->protected && test_bit(hw, mpic->protected))
974 return -EINVAL;
975
976 #ifdef CONFIG_SMP
977 else if (hw >= mpic->ipi_vecs[0]) {
978 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
979
980 DBG("mpic: mapping as IPI\n");
981 irq_set_chip_data(virq, mpic);
982 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
983 handle_percpu_irq);
984 return 0;
985 }
986 #endif /* CONFIG_SMP */
987
988 if (hw >= mpic->irq_count)
989 return -EINVAL;
990
991 mpic_msi_reserve_hwirq(mpic, hw);
992
993 /* Default chip */
994 chip = &mpic->hc_irq;
995
996 #ifdef CONFIG_MPIC_U3_HT_IRQS
997 /* Check for HT interrupts, override vecpri */
998 if (mpic_is_ht_interrupt(mpic, hw))
999 chip = &mpic->hc_ht_irq;
1000 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1001
1002 DBG("mpic: mapping to irq chip @%p\n", chip);
1003
1004 irq_set_chip_data(virq, mpic);
1005 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1006
1007 /* Set default irq type */
1008 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1009
1010 /* If the MPIC was reset, then all vectors have already been
1011 * initialized. Otherwise, a per source lazy initialization
1012 * is done here.
1013 */
1014 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1015 mpic_set_vector(virq, hw);
1016 mpic_set_destination(virq, mpic_processor_id(mpic));
1017 mpic_irq_set_priority(virq, 8);
1018 }
1019
1020 return 0;
1021 }
1022
1023 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1024 const u32 *intspec, unsigned int intsize,
1025 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1026
1027 {
1028 static unsigned char map_mpic_senses[4] = {
1029 IRQ_TYPE_EDGE_RISING,
1030 IRQ_TYPE_LEVEL_LOW,
1031 IRQ_TYPE_LEVEL_HIGH,
1032 IRQ_TYPE_EDGE_FALLING,
1033 };
1034
1035 *out_hwirq = intspec[0];
1036 if (intsize > 1) {
1037 u32 mask = 0x3;
1038
1039 /* Apple invented a new race of encoding on machines with
1040 * an HT APIC. They encode, among others, the index within
1041 * the HT APIC. We don't care about it here since thankfully,
1042 * it appears that they have the APIC already properly
1043 * configured, and thus our current fixup code that reads the
1044 * APIC config works fine. However, we still need to mask out
1045 * bits in the specifier to make sure we only get bit 0 which
1046 * is the level/edge bit (the only sense bit exposed by Apple),
1047 * as their bit 1 means something else.
1048 */
1049 if (machine_is(powermac))
1050 mask = 0x1;
1051 *out_flags = map_mpic_senses[intspec[1] & mask];
1052 } else
1053 *out_flags = IRQ_TYPE_NONE;
1054
1055 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1056 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1057
1058 return 0;
1059 }
1060
1061 static struct irq_host_ops mpic_host_ops = {
1062 .match = mpic_host_match,
1063 .map = mpic_host_map,
1064 .xlate = mpic_host_xlate,
1065 };
1066
1067 static int mpic_reset_prohibited(struct device_node *node)
1068 {
1069 return node && of_get_property(node, "pic-no-reset", NULL);
1070 }
1071
1072 /*
1073 * Exported functions
1074 */
1075
1076 struct mpic * __init mpic_alloc(struct device_node *node,
1077 phys_addr_t phys_addr,
1078 unsigned int flags,
1079 unsigned int isu_size,
1080 unsigned int irq_count,
1081 const char *name)
1082 {
1083 struct mpic *mpic;
1084 u32 greg_feature;
1085 const char *vers;
1086 int i;
1087 int intvec_top;
1088 u64 paddr = phys_addr;
1089
1090 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1091 if (mpic == NULL)
1092 return NULL;
1093
1094 mpic->name = name;
1095
1096 mpic->hc_irq = mpic_irq_chip;
1097 mpic->hc_irq.name = name;
1098 if (flags & MPIC_PRIMARY)
1099 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1100 #ifdef CONFIG_MPIC_U3_HT_IRQS
1101 mpic->hc_ht_irq = mpic_irq_ht_chip;
1102 mpic->hc_ht_irq.name = name;
1103 if (flags & MPIC_PRIMARY)
1104 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1105 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1106
1107 #ifdef CONFIG_SMP
1108 mpic->hc_ipi = mpic_ipi_chip;
1109 mpic->hc_ipi.name = name;
1110 #endif /* CONFIG_SMP */
1111
1112 mpic->flags = flags;
1113 mpic->isu_size = isu_size;
1114 mpic->irq_count = irq_count;
1115 mpic->num_sources = 0; /* so far */
1116
1117 if (flags & MPIC_LARGE_VECTORS)
1118 intvec_top = 2047;
1119 else
1120 intvec_top = 255;
1121
1122 mpic->timer_vecs[0] = intvec_top - 8;
1123 mpic->timer_vecs[1] = intvec_top - 7;
1124 mpic->timer_vecs[2] = intvec_top - 6;
1125 mpic->timer_vecs[3] = intvec_top - 5;
1126 mpic->ipi_vecs[0] = intvec_top - 4;
1127 mpic->ipi_vecs[1] = intvec_top - 3;
1128 mpic->ipi_vecs[2] = intvec_top - 2;
1129 mpic->ipi_vecs[3] = intvec_top - 1;
1130 mpic->spurious_vec = intvec_top;
1131
1132 /* Check for "big-endian" in device-tree */
1133 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1134 mpic->flags |= MPIC_BIG_ENDIAN;
1135
1136 /* Look for protected sources */
1137 if (node) {
1138 int psize;
1139 unsigned int bits, mapsize;
1140 const u32 *psrc =
1141 of_get_property(node, "protected-sources", &psize);
1142 if (psrc) {
1143 psize /= 4;
1144 bits = intvec_top + 1;
1145 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1146 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1147 BUG_ON(mpic->protected == NULL);
1148 for (i = 0; i < psize; i++) {
1149 if (psrc[i] > intvec_top)
1150 continue;
1151 __set_bit(psrc[i], mpic->protected);
1152 }
1153 }
1154 }
1155
1156 #ifdef CONFIG_MPIC_WEIRD
1157 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1158 #endif
1159
1160 /* default register type */
1161 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1162 mpic_access_mmio_be : mpic_access_mmio_le;
1163
1164 /* If no physical address is passed in, a device-node is mandatory */
1165 BUG_ON(paddr == 0 && node == NULL);
1166
1167 /* If no physical address passed in, check if it's dcr based */
1168 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1169 #ifdef CONFIG_PPC_DCR
1170 mpic->flags |= MPIC_USES_DCR;
1171 mpic->reg_type = mpic_access_dcr;
1172 #else
1173 BUG();
1174 #endif /* CONFIG_PPC_DCR */
1175 }
1176
1177 /* If the MPIC is not DCR based, and no physical address was passed
1178 * in, try to obtain one
1179 */
1180 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1181 const u32 *reg = of_get_property(node, "reg", NULL);
1182 BUG_ON(reg == NULL);
1183 paddr = of_translate_address(node, reg);
1184 BUG_ON(paddr == OF_BAD_ADDR);
1185 }
1186
1187 /* Map the global registers */
1188 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1189 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1190
1191 /* Reset */
1192
1193 /* When using a device-node, reset requests are only honored if the MPIC
1194 * is allowed to reset.
1195 */
1196 if (mpic_reset_prohibited(node))
1197 mpic->flags |= MPIC_NO_RESET;
1198
1199 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1200 printk(KERN_DEBUG "mpic: Resetting\n");
1201 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1202 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1203 | MPIC_GREG_GCONF_RESET);
1204 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1205 & MPIC_GREG_GCONF_RESET)
1206 mb();
1207 }
1208
1209 /* CoreInt */
1210 if (flags & MPIC_ENABLE_COREINT)
1211 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1212 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1213 | MPIC_GREG_GCONF_COREINT);
1214
1215 if (flags & MPIC_ENABLE_MCK)
1216 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1217 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1218 | MPIC_GREG_GCONF_MCK);
1219
1220 /* Read feature register, calculate num CPUs and, for non-ISU
1221 * MPICs, num sources as well. On ISU MPICs, sources are counted
1222 * as ISUs are added
1223 */
1224 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1225 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1226 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1227 if (isu_size == 0) {
1228 if (flags & MPIC_BROKEN_FRR_NIRQS)
1229 mpic->num_sources = mpic->irq_count;
1230 else
1231 mpic->num_sources =
1232 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1233 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1234 }
1235
1236 /* Map the per-CPU registers */
1237 for (i = 0; i < mpic->num_cpus; i++) {
1238 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1239 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1240 0x1000);
1241 }
1242
1243 /* Initialize main ISU if none provided */
1244 if (mpic->isu_size == 0) {
1245 mpic->isu_size = mpic->num_sources;
1246 mpic_map(mpic, node, paddr, &mpic->isus[0],
1247 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1248 }
1249 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1250 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1251
1252 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1253 isu_size ? isu_size : mpic->num_sources,
1254 &mpic_host_ops,
1255 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1256 if (mpic->irqhost == NULL)
1257 return NULL;
1258
1259 mpic->irqhost->host_data = mpic;
1260
1261 /* Display version */
1262 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1263 case 1:
1264 vers = "1.0";
1265 break;
1266 case 2:
1267 vers = "1.2";
1268 break;
1269 case 3:
1270 vers = "1.3";
1271 break;
1272 default:
1273 vers = "<unknown>";
1274 break;
1275 }
1276 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1277 " max %d CPUs\n",
1278 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1279 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1280 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1281
1282 mpic->next = mpics;
1283 mpics = mpic;
1284
1285 if (flags & MPIC_PRIMARY) {
1286 mpic_primary = mpic;
1287 irq_set_default_host(mpic->irqhost);
1288 }
1289
1290 return mpic;
1291 }
1292
1293 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1294 phys_addr_t paddr)
1295 {
1296 unsigned int isu_first = isu_num * mpic->isu_size;
1297
1298 BUG_ON(isu_num >= MPIC_MAX_ISU);
1299
1300 mpic_map(mpic, mpic->irqhost->of_node,
1301 paddr, &mpic->isus[isu_num], 0,
1302 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1303
1304 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1305 mpic->num_sources = isu_first + mpic->isu_size;
1306 }
1307
1308 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1309 {
1310 mpic->senses = senses;
1311 mpic->senses_count = count;
1312 }
1313
1314 void __init mpic_init(struct mpic *mpic)
1315 {
1316 int i;
1317 int cpu;
1318
1319 BUG_ON(mpic->num_sources == 0);
1320
1321 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1322
1323 /* Set current processor priority to max */
1324 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1325
1326 /* Initialize timers: just disable them all */
1327 for (i = 0; i < 4; i++) {
1328 mpic_write(mpic->tmregs,
1329 i * MPIC_INFO(TIMER_STRIDE) +
1330 MPIC_INFO(TIMER_DESTINATION), 0);
1331 mpic_write(mpic->tmregs,
1332 i * MPIC_INFO(TIMER_STRIDE) +
1333 MPIC_INFO(TIMER_VECTOR_PRI),
1334 MPIC_VECPRI_MASK |
1335 (mpic->timer_vecs[0] + i));
1336 }
1337
1338 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1339 mpic_test_broken_ipi(mpic);
1340 for (i = 0; i < 4; i++) {
1341 mpic_ipi_write(i,
1342 MPIC_VECPRI_MASK |
1343 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1344 (mpic->ipi_vecs[0] + i));
1345 }
1346
1347 /* Initialize interrupt sources */
1348 if (mpic->irq_count == 0)
1349 mpic->irq_count = mpic->num_sources;
1350
1351 /* Do the HT PIC fixups on U3 broken mpic */
1352 DBG("MPIC flags: %x\n", mpic->flags);
1353 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1354 mpic_scan_ht_pics(mpic);
1355 mpic_u3msi_init(mpic);
1356 }
1357
1358 mpic_pasemi_msi_init(mpic);
1359
1360 cpu = mpic_processor_id(mpic);
1361
1362 if (!(mpic->flags & MPIC_NO_RESET)) {
1363 for (i = 0; i < mpic->num_sources; i++) {
1364 /* start with vector = source number, and masked */
1365 u32 vecpri = MPIC_VECPRI_MASK | i |
1366 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1367
1368 /* check if protected */
1369 if (mpic->protected && test_bit(i, mpic->protected))
1370 continue;
1371 /* init hw */
1372 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1373 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1374 }
1375 }
1376
1377 /* Init spurious vector */
1378 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1379
1380 /* Disable 8259 passthrough, if supported */
1381 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1382 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1383 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1384 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1385
1386 if (mpic->flags & MPIC_NO_BIAS)
1387 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1388 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1389 | MPIC_GREG_GCONF_NO_BIAS);
1390
1391 /* Set current processor priority to 0 */
1392 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1393
1394 #ifdef CONFIG_PM
1395 /* allocate memory to save mpic state */
1396 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1397 GFP_KERNEL);
1398 BUG_ON(mpic->save_data == NULL);
1399 #endif
1400 }
1401
1402 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1403 {
1404 u32 v;
1405
1406 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1407 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1408 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1409 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1410 }
1411
1412 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1413 {
1414 unsigned long flags;
1415 u32 v;
1416
1417 raw_spin_lock_irqsave(&mpic_lock, flags);
1418 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1419 if (enable)
1420 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1421 else
1422 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1423 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1424 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1425 }
1426
1427 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1428 {
1429 struct mpic *mpic = mpic_find(irq);
1430 unsigned int src = mpic_irq_to_hw(irq);
1431 unsigned long flags;
1432 u32 reg;
1433
1434 if (!mpic)
1435 return;
1436
1437 raw_spin_lock_irqsave(&mpic_lock, flags);
1438 if (mpic_is_ipi(mpic, irq)) {
1439 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1440 ~MPIC_VECPRI_PRIORITY_MASK;
1441 mpic_ipi_write(src - mpic->ipi_vecs[0],
1442 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1443 } else {
1444 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1445 & ~MPIC_VECPRI_PRIORITY_MASK;
1446 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1447 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1448 }
1449 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1450 }
1451
1452 void mpic_setup_this_cpu(void)
1453 {
1454 #ifdef CONFIG_SMP
1455 struct mpic *mpic = mpic_primary;
1456 unsigned long flags;
1457 u32 msk = 1 << hard_smp_processor_id();
1458 unsigned int i;
1459
1460 BUG_ON(mpic == NULL);
1461
1462 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1463
1464 raw_spin_lock_irqsave(&mpic_lock, flags);
1465
1466 /* let the mpic know we want intrs. default affinity is 0xffffffff
1467 * until changed via /proc. That's how it's done on x86. If we want
1468 * it differently, then we should make sure we also change the default
1469 * values of irq_desc[].affinity in irq.c.
1470 */
1471 if (distribute_irqs) {
1472 for (i = 0; i < mpic->num_sources ; i++)
1473 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1474 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1475 }
1476
1477 /* Set current processor priority to 0 */
1478 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1479
1480 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1481 #endif /* CONFIG_SMP */
1482 }
1483
1484 int mpic_cpu_get_priority(void)
1485 {
1486 struct mpic *mpic = mpic_primary;
1487
1488 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1489 }
1490
1491 void mpic_cpu_set_priority(int prio)
1492 {
1493 struct mpic *mpic = mpic_primary;
1494
1495 prio &= MPIC_CPU_TASKPRI_MASK;
1496 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1497 }
1498
1499 void mpic_teardown_this_cpu(int secondary)
1500 {
1501 struct mpic *mpic = mpic_primary;
1502 unsigned long flags;
1503 u32 msk = 1 << hard_smp_processor_id();
1504 unsigned int i;
1505
1506 BUG_ON(mpic == NULL);
1507
1508 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1509 raw_spin_lock_irqsave(&mpic_lock, flags);
1510
1511 /* let the mpic know we don't want intrs. */
1512 for (i = 0; i < mpic->num_sources ; i++)
1513 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1514 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1515
1516 /* Set current processor priority to max */
1517 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1518 /* We need to EOI the IPI since not all platforms reset the MPIC
1519 * on boot and new interrupts wouldn't get delivered otherwise.
1520 */
1521 mpic_eoi(mpic);
1522
1523 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1524 }
1525
1526
1527 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1528 {
1529 u32 src;
1530
1531 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1532 #ifdef DEBUG_LOW
1533 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1534 #endif
1535 if (unlikely(src == mpic->spurious_vec)) {
1536 if (mpic->flags & MPIC_SPV_EOI)
1537 mpic_eoi(mpic);
1538 return NO_IRQ;
1539 }
1540 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1541 if (printk_ratelimit())
1542 printk(KERN_WARNING "%s: Got protected source %d !\n",
1543 mpic->name, (int)src);
1544 mpic_eoi(mpic);
1545 return NO_IRQ;
1546 }
1547
1548 return irq_linear_revmap(mpic->irqhost, src);
1549 }
1550
1551 unsigned int mpic_get_one_irq(struct mpic *mpic)
1552 {
1553 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1554 }
1555
1556 unsigned int mpic_get_irq(void)
1557 {
1558 struct mpic *mpic = mpic_primary;
1559
1560 BUG_ON(mpic == NULL);
1561
1562 return mpic_get_one_irq(mpic);
1563 }
1564
1565 unsigned int mpic_get_coreint_irq(void)
1566 {
1567 #ifdef CONFIG_BOOKE
1568 struct mpic *mpic = mpic_primary;
1569 u32 src;
1570
1571 BUG_ON(mpic == NULL);
1572
1573 src = mfspr(SPRN_EPR);
1574
1575 if (unlikely(src == mpic->spurious_vec)) {
1576 if (mpic->flags & MPIC_SPV_EOI)
1577 mpic_eoi(mpic);
1578 return NO_IRQ;
1579 }
1580 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1581 if (printk_ratelimit())
1582 printk(KERN_WARNING "%s: Got protected source %d !\n",
1583 mpic->name, (int)src);
1584 return NO_IRQ;
1585 }
1586
1587 return irq_linear_revmap(mpic->irqhost, src);
1588 #else
1589 return NO_IRQ;
1590 #endif
1591 }
1592
1593 unsigned int mpic_get_mcirq(void)
1594 {
1595 struct mpic *mpic = mpic_primary;
1596
1597 BUG_ON(mpic == NULL);
1598
1599 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1600 }
1601
1602 #ifdef CONFIG_SMP
1603 void mpic_request_ipis(void)
1604 {
1605 struct mpic *mpic = mpic_primary;
1606 int i;
1607 BUG_ON(mpic == NULL);
1608
1609 printk(KERN_INFO "mpic: requesting IPIs...\n");
1610
1611 for (i = 0; i < 4; i++) {
1612 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1613 mpic->ipi_vecs[0] + i);
1614 if (vipi == NO_IRQ) {
1615 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1616 continue;
1617 }
1618 smp_request_message_ipi(vipi, i);
1619 }
1620 }
1621
1622 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
1623 {
1624 struct mpic *mpic = mpic_primary;
1625
1626 BUG_ON(mpic == NULL);
1627
1628 #ifdef DEBUG_IPI
1629 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1630 #endif
1631
1632 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1633 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1634 mpic_physmask(cpumask_bits(cpu_mask)[0]));
1635 }
1636
1637 void smp_mpic_message_pass(int target, int msg)
1638 {
1639 cpumask_var_t tmp;
1640
1641 /* make sure we're sending something that translates to an IPI */
1642 if ((unsigned int)msg > 3) {
1643 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1644 smp_processor_id(), msg);
1645 return;
1646 }
1647 switch (target) {
1648 case MSG_ALL:
1649 mpic_send_ipi(msg, cpu_online_mask);
1650 break;
1651 case MSG_ALL_BUT_SELF:
1652 alloc_cpumask_var(&tmp, GFP_NOWAIT);
1653 cpumask_andnot(tmp, cpu_online_mask,
1654 cpumask_of(smp_processor_id()));
1655 mpic_send_ipi(msg, tmp);
1656 free_cpumask_var(tmp);
1657 break;
1658 default:
1659 mpic_send_ipi(msg, cpumask_of(target));
1660 break;
1661 }
1662 }
1663
1664 int __init smp_mpic_probe(void)
1665 {
1666 int nr_cpus;
1667
1668 DBG("smp_mpic_probe()...\n");
1669
1670 nr_cpus = cpumask_weight(cpu_possible_mask);
1671
1672 DBG("nr_cpus: %d\n", nr_cpus);
1673
1674 if (nr_cpus > 1)
1675 mpic_request_ipis();
1676
1677 return nr_cpus;
1678 }
1679
1680 void __devinit smp_mpic_setup_cpu(int cpu)
1681 {
1682 mpic_setup_this_cpu();
1683 }
1684
1685 void mpic_reset_core(int cpu)
1686 {
1687 struct mpic *mpic = mpic_primary;
1688 u32 pir;
1689 int cpuid = get_hard_smp_processor_id(cpu);
1690
1691 /* Set target bit for core reset */
1692 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1693 pir |= (1 << cpuid);
1694 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1695 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1696
1697 /* Restore target bit after reset complete */
1698 pir &= ~(1 << cpuid);
1699 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1700 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1701 }
1702 #endif /* CONFIG_SMP */
1703
1704 #ifdef CONFIG_PM
1705 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1706 {
1707 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1708 int i;
1709
1710 for (i = 0; i < mpic->num_sources; i++) {
1711 mpic->save_data[i].vecprio =
1712 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1713 mpic->save_data[i].dest =
1714 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1715 }
1716
1717 return 0;
1718 }
1719
1720 static int mpic_resume(struct sys_device *dev)
1721 {
1722 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1723 int i;
1724
1725 for (i = 0; i < mpic->num_sources; i++) {
1726 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1727 mpic->save_data[i].vecprio);
1728 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1729 mpic->save_data[i].dest);
1730
1731 #ifdef CONFIG_MPIC_U3_HT_IRQS
1732 if (mpic->fixups) {
1733 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1734
1735 if (fixup->base) {
1736 /* we use the lowest bit in an inverted meaning */
1737 if ((mpic->save_data[i].fixup_data & 1) == 0)
1738 continue;
1739
1740 /* Enable and configure */
1741 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1742
1743 writel(mpic->save_data[i].fixup_data & ~1,
1744 fixup->base + 4);
1745 }
1746 }
1747 #endif
1748 } /* end for loop */
1749
1750 return 0;
1751 }
1752 #endif
1753
1754 static struct sysdev_class mpic_sysclass = {
1755 #ifdef CONFIG_PM
1756 .resume = mpic_resume,
1757 .suspend = mpic_suspend,
1758 #endif
1759 .name = "mpic",
1760 };
1761
1762 static int mpic_init_sys(void)
1763 {
1764 struct mpic *mpic = mpics;
1765 int error, id = 0;
1766
1767 error = sysdev_class_register(&mpic_sysclass);
1768
1769 while (mpic && !error) {
1770 mpic->sysdev.cls = &mpic_sysclass;
1771 mpic->sysdev.id = id++;
1772 error = sysdev_register(&mpic->sysdev);
1773 mpic = mpic->next;
1774 }
1775 return error;
1776 }
1777
1778 device_initcall(mpic_init_sys);
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