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[ALSA] sscape: support for audio part of VIVO cards
[linux-2.6.git] / drivers / net / bnx2.c
blob78ed633ceb829e121161a8a230a1350d9de06017
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <asm/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50
51 #include "bnx2.h"
52 #include "bnx2_fw.h"
53 #include "bnx2_fw2.h"
54
55 #define FW_BUF_SIZE 0x8000
56
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.6.7"
60 #define DRV_MODULE_RELDATE "October 10, 2007"
61
62 #define RUN_AT(x) (jiffies + (x))
63
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
66
67 static const char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
74
75 static int disable_msi = 0;
76
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80 typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
86 BCM5708,
87 BCM5708S,
88 BCM5709,
89 BCM5709S,
90 } board_t;
91
92 /* indexed by board_t, above */
93 static const struct {
94 char *name;
95 } board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
105 };
106
107 static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
126 { 0, }
127 };
128
129 static struct flash_spec flash_table[] =
130 {
131 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
133 /* Slow EEPROM */
134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
216 };
217
218 static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225 };
226
227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
229 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
230 {
231 u32 diff;
232
233 smp_mb();
234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
238 diff = bp->tx_prod - bp->tx_cons;
239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
244 return (bp->tx_ring_size - diff);
245 }
246
247 static u32
248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249 {
250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
257 }
258
259 static void
260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261 {
262 spin_lock_bh(&bp->indirect_lock);
263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
265 spin_unlock_bh(&bp->indirect_lock);
266 }
267
268 static void
269 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
270 {
271 offset += cid_addr;
272 spin_lock_bh(&bp->indirect_lock);
273 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
274 int i;
275
276 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
277 REG_WR(bp, BNX2_CTX_CTX_CTRL,
278 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
279 for (i = 0; i < 5; i++) {
280 u32 val;
281 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
282 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
283 break;
284 udelay(5);
285 }
286 } else {
287 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
288 REG_WR(bp, BNX2_CTX_DATA, val);
289 }
290 spin_unlock_bh(&bp->indirect_lock);
291 }
292
293 static int
294 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
295 {
296 u32 val1;
297 int i, ret;
298
299 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
300 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
301 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
302
303 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
304 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
305
306 udelay(40);
307 }
308
309 val1 = (bp->phy_addr << 21) | (reg << 16) |
310 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
311 BNX2_EMAC_MDIO_COMM_START_BUSY;
312 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
313
314 for (i = 0; i < 50; i++) {
315 udelay(10);
316
317 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
318 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
319 udelay(5);
320
321 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
322 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
323
324 break;
325 }
326 }
327
328 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
329 *val = 0x0;
330 ret = -EBUSY;
331 }
332 else {
333 *val = val1;
334 ret = 0;
335 }
336
337 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
338 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
339 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
340
341 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
342 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
343
344 udelay(40);
345 }
346
347 return ret;
348 }
349
350 static int
351 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
352 {
353 u32 val1;
354 int i, ret;
355
356 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
357 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
358 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
359
360 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
361 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
362
363 udelay(40);
364 }
365
366 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
367 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
368 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
369 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
370
371 for (i = 0; i < 50; i++) {
372 udelay(10);
373
374 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
375 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
376 udelay(5);
377 break;
378 }
379 }
380
381 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
382 ret = -EBUSY;
383 else
384 ret = 0;
385
386 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
387 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
388 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
389
390 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
391 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
392
393 udelay(40);
394 }
395
396 return ret;
397 }
398
399 static void
400 bnx2_disable_int(struct bnx2 *bp)
401 {
402 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
403 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
404 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
405 }
406
407 static void
408 bnx2_enable_int(struct bnx2 *bp)
409 {
410 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
411 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
412 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
413
414 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
415 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
416
417 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
418 }
419
420 static void
421 bnx2_disable_int_sync(struct bnx2 *bp)
422 {
423 atomic_inc(&bp->intr_sem);
424 bnx2_disable_int(bp);
425 synchronize_irq(bp->pdev->irq);
426 }
427
428 static void
429 bnx2_netif_stop(struct bnx2 *bp)
430 {
431 bnx2_disable_int_sync(bp);
432 if (netif_running(bp->dev)) {
433 napi_disable(&bp->napi);
434 netif_tx_disable(bp->dev);
435 bp->dev->trans_start = jiffies; /* prevent tx timeout */
436 }
437 }
438
439 static void
440 bnx2_netif_start(struct bnx2 *bp)
441 {
442 if (atomic_dec_and_test(&bp->intr_sem)) {
443 if (netif_running(bp->dev)) {
444 netif_wake_queue(bp->dev);
445 napi_enable(&bp->napi);
446 bnx2_enable_int(bp);
447 }
448 }
449 }
450
451 static void
452 bnx2_free_mem(struct bnx2 *bp)
453 {
454 int i;
455
456 for (i = 0; i < bp->ctx_pages; i++) {
457 if (bp->ctx_blk[i]) {
458 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
459 bp->ctx_blk[i],
460 bp->ctx_blk_mapping[i]);
461 bp->ctx_blk[i] = NULL;
462 }
463 }
464 if (bp->status_blk) {
465 pci_free_consistent(bp->pdev, bp->status_stats_size,
466 bp->status_blk, bp->status_blk_mapping);
467 bp->status_blk = NULL;
468 bp->stats_blk = NULL;
469 }
470 if (bp->tx_desc_ring) {
471 pci_free_consistent(bp->pdev,
472 sizeof(struct tx_bd) * TX_DESC_CNT,
473 bp->tx_desc_ring, bp->tx_desc_mapping);
474 bp->tx_desc_ring = NULL;
475 }
476 kfree(bp->tx_buf_ring);
477 bp->tx_buf_ring = NULL;
478 for (i = 0; i < bp->rx_max_ring; i++) {
479 if (bp->rx_desc_ring[i])
480 pci_free_consistent(bp->pdev,
481 sizeof(struct rx_bd) * RX_DESC_CNT,
482 bp->rx_desc_ring[i],
483 bp->rx_desc_mapping[i]);
484 bp->rx_desc_ring[i] = NULL;
485 }
486 vfree(bp->rx_buf_ring);
487 bp->rx_buf_ring = NULL;
488 }
489
490 static int
491 bnx2_alloc_mem(struct bnx2 *bp)
492 {
493 int i, status_blk_size;
494
495 bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
496 GFP_KERNEL);
497 if (bp->tx_buf_ring == NULL)
498 return -ENOMEM;
499
500 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
501 sizeof(struct tx_bd) *
502 TX_DESC_CNT,
503 &bp->tx_desc_mapping);
504 if (bp->tx_desc_ring == NULL)
505 goto alloc_mem_err;
506
507 bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
508 bp->rx_max_ring);
509 if (bp->rx_buf_ring == NULL)
510 goto alloc_mem_err;
511
512 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
513 bp->rx_max_ring);
514
515 for (i = 0; i < bp->rx_max_ring; i++) {
516 bp->rx_desc_ring[i] =
517 pci_alloc_consistent(bp->pdev,
518 sizeof(struct rx_bd) * RX_DESC_CNT,
519 &bp->rx_desc_mapping[i]);
520 if (bp->rx_desc_ring[i] == NULL)
521 goto alloc_mem_err;
522
523 }
524
525 /* Combine status and statistics blocks into one allocation. */
526 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
527 bp->status_stats_size = status_blk_size +
528 sizeof(struct statistics_block);
529
530 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
531 &bp->status_blk_mapping);
532 if (bp->status_blk == NULL)
533 goto alloc_mem_err;
534
535 memset(bp->status_blk, 0, bp->status_stats_size);
536
537 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
538 status_blk_size);
539
540 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
541
542 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
543 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
544 if (bp->ctx_pages == 0)
545 bp->ctx_pages = 1;
546 for (i = 0; i < bp->ctx_pages; i++) {
547 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
548 BCM_PAGE_SIZE,
549 &bp->ctx_blk_mapping[i]);
550 if (bp->ctx_blk[i] == NULL)
551 goto alloc_mem_err;
552 }
553 }
554 return 0;
555
556 alloc_mem_err:
557 bnx2_free_mem(bp);
558 return -ENOMEM;
559 }
560
561 static void
562 bnx2_report_fw_link(struct bnx2 *bp)
563 {
564 u32 fw_link_status = 0;
565
566 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
567 return;
568
569 if (bp->link_up) {
570 u32 bmsr;
571
572 switch (bp->line_speed) {
573 case SPEED_10:
574 if (bp->duplex == DUPLEX_HALF)
575 fw_link_status = BNX2_LINK_STATUS_10HALF;
576 else
577 fw_link_status = BNX2_LINK_STATUS_10FULL;
578 break;
579 case SPEED_100:
580 if (bp->duplex == DUPLEX_HALF)
581 fw_link_status = BNX2_LINK_STATUS_100HALF;
582 else
583 fw_link_status = BNX2_LINK_STATUS_100FULL;
584 break;
585 case SPEED_1000:
586 if (bp->duplex == DUPLEX_HALF)
587 fw_link_status = BNX2_LINK_STATUS_1000HALF;
588 else
589 fw_link_status = BNX2_LINK_STATUS_1000FULL;
590 break;
591 case SPEED_2500:
592 if (bp->duplex == DUPLEX_HALF)
593 fw_link_status = BNX2_LINK_STATUS_2500HALF;
594 else
595 fw_link_status = BNX2_LINK_STATUS_2500FULL;
596 break;
597 }
598
599 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
600
601 if (bp->autoneg) {
602 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
603
604 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
605 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
606
607 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
608 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
609 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
610 else
611 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
612 }
613 }
614 else
615 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
616
617 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
618 }
619
620 static char *
621 bnx2_xceiver_str(struct bnx2 *bp)
622 {
623 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
624 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
625 "Copper"));
626 }
627
628 static void
629 bnx2_report_link(struct bnx2 *bp)
630 {
631 if (bp->link_up) {
632 netif_carrier_on(bp->dev);
633 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
634 bnx2_xceiver_str(bp));
635
636 printk("%d Mbps ", bp->line_speed);
637
638 if (bp->duplex == DUPLEX_FULL)
639 printk("full duplex");
640 else
641 printk("half duplex");
642
643 if (bp->flow_ctrl) {
644 if (bp->flow_ctrl & FLOW_CTRL_RX) {
645 printk(", receive ");
646 if (bp->flow_ctrl & FLOW_CTRL_TX)
647 printk("& transmit ");
648 }
649 else {
650 printk(", transmit ");
651 }
652 printk("flow control ON");
653 }
654 printk("\n");
655 }
656 else {
657 netif_carrier_off(bp->dev);
658 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
659 bnx2_xceiver_str(bp));
660 }
661
662 bnx2_report_fw_link(bp);
663 }
664
665 static void
666 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
667 {
668 u32 local_adv, remote_adv;
669
670 bp->flow_ctrl = 0;
671 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
672 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
673
674 if (bp->duplex == DUPLEX_FULL) {
675 bp->flow_ctrl = bp->req_flow_ctrl;
676 }
677 return;
678 }
679
680 if (bp->duplex != DUPLEX_FULL) {
681 return;
682 }
683
684 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
685 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
686 u32 val;
687
688 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
689 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
690 bp->flow_ctrl |= FLOW_CTRL_TX;
691 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
692 bp->flow_ctrl |= FLOW_CTRL_RX;
693 return;
694 }
695
696 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
697 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
698
699 if (bp->phy_flags & PHY_SERDES_FLAG) {
700 u32 new_local_adv = 0;
701 u32 new_remote_adv = 0;
702
703 if (local_adv & ADVERTISE_1000XPAUSE)
704 new_local_adv |= ADVERTISE_PAUSE_CAP;
705 if (local_adv & ADVERTISE_1000XPSE_ASYM)
706 new_local_adv |= ADVERTISE_PAUSE_ASYM;
707 if (remote_adv & ADVERTISE_1000XPAUSE)
708 new_remote_adv |= ADVERTISE_PAUSE_CAP;
709 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
710 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
711
712 local_adv = new_local_adv;
713 remote_adv = new_remote_adv;
714 }
715
716 /* See Table 28B-3 of 802.3ab-1999 spec. */
717 if (local_adv & ADVERTISE_PAUSE_CAP) {
718 if(local_adv & ADVERTISE_PAUSE_ASYM) {
719 if (remote_adv & ADVERTISE_PAUSE_CAP) {
720 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
721 }
722 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
723 bp->flow_ctrl = FLOW_CTRL_RX;
724 }
725 }
726 else {
727 if (remote_adv & ADVERTISE_PAUSE_CAP) {
728 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
729 }
730 }
731 }
732 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
733 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
734 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
735
736 bp->flow_ctrl = FLOW_CTRL_TX;
737 }
738 }
739 }
740
741 static int
742 bnx2_5709s_linkup(struct bnx2 *bp)
743 {
744 u32 val, speed;
745
746 bp->link_up = 1;
747
748 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
749 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
750 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
751
752 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
753 bp->line_speed = bp->req_line_speed;
754 bp->duplex = bp->req_duplex;
755 return 0;
756 }
757 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
758 switch (speed) {
759 case MII_BNX2_GP_TOP_AN_SPEED_10:
760 bp->line_speed = SPEED_10;
761 break;
762 case MII_BNX2_GP_TOP_AN_SPEED_100:
763 bp->line_speed = SPEED_100;
764 break;
765 case MII_BNX2_GP_TOP_AN_SPEED_1G:
766 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
767 bp->line_speed = SPEED_1000;
768 break;
769 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
770 bp->line_speed = SPEED_2500;
771 break;
772 }
773 if (val & MII_BNX2_GP_TOP_AN_FD)
774 bp->duplex = DUPLEX_FULL;
775 else
776 bp->duplex = DUPLEX_HALF;
777 return 0;
778 }
779
780 static int
781 bnx2_5708s_linkup(struct bnx2 *bp)
782 {
783 u32 val;
784
785 bp->link_up = 1;
786 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
787 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
788 case BCM5708S_1000X_STAT1_SPEED_10:
789 bp->line_speed = SPEED_10;
790 break;
791 case BCM5708S_1000X_STAT1_SPEED_100:
792 bp->line_speed = SPEED_100;
793 break;
794 case BCM5708S_1000X_STAT1_SPEED_1G:
795 bp->line_speed = SPEED_1000;
796 break;
797 case BCM5708S_1000X_STAT1_SPEED_2G5:
798 bp->line_speed = SPEED_2500;
799 break;
800 }
801 if (val & BCM5708S_1000X_STAT1_FD)
802 bp->duplex = DUPLEX_FULL;
803 else
804 bp->duplex = DUPLEX_HALF;
805
806 return 0;
807 }
808
809 static int
810 bnx2_5706s_linkup(struct bnx2 *bp)
811 {
812 u32 bmcr, local_adv, remote_adv, common;
813
814 bp->link_up = 1;
815 bp->line_speed = SPEED_1000;
816
817 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
818 if (bmcr & BMCR_FULLDPLX) {
819 bp->duplex = DUPLEX_FULL;
820 }
821 else {
822 bp->duplex = DUPLEX_HALF;
823 }
824
825 if (!(bmcr & BMCR_ANENABLE)) {
826 return 0;
827 }
828
829 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
830 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
831
832 common = local_adv & remote_adv;
833 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
834
835 if (common & ADVERTISE_1000XFULL) {
836 bp->duplex = DUPLEX_FULL;
837 }
838 else {
839 bp->duplex = DUPLEX_HALF;
840 }
841 }
842
843 return 0;
844 }
845
846 static int
847 bnx2_copper_linkup(struct bnx2 *bp)
848 {
849 u32 bmcr;
850
851 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
852 if (bmcr & BMCR_ANENABLE) {
853 u32 local_adv, remote_adv, common;
854
855 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
856 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
857
858 common = local_adv & (remote_adv >> 2);
859 if (common & ADVERTISE_1000FULL) {
860 bp->line_speed = SPEED_1000;
861 bp->duplex = DUPLEX_FULL;
862 }
863 else if (common & ADVERTISE_1000HALF) {
864 bp->line_speed = SPEED_1000;
865 bp->duplex = DUPLEX_HALF;
866 }
867 else {
868 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
869 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
870
871 common = local_adv & remote_adv;
872 if (common & ADVERTISE_100FULL) {
873 bp->line_speed = SPEED_100;
874 bp->duplex = DUPLEX_FULL;
875 }
876 else if (common & ADVERTISE_100HALF) {
877 bp->line_speed = SPEED_100;
878 bp->duplex = DUPLEX_HALF;
879 }
880 else if (common & ADVERTISE_10FULL) {
881 bp->line_speed = SPEED_10;
882 bp->duplex = DUPLEX_FULL;
883 }
884 else if (common & ADVERTISE_10HALF) {
885 bp->line_speed = SPEED_10;
886 bp->duplex = DUPLEX_HALF;
887 }
888 else {
889 bp->line_speed = 0;
890 bp->link_up = 0;
891 }
892 }
893 }
894 else {
895 if (bmcr & BMCR_SPEED100) {
896 bp->line_speed = SPEED_100;
897 }
898 else {
899 bp->line_speed = SPEED_10;
900 }
901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
903 }
904 else {
905 bp->duplex = DUPLEX_HALF;
906 }
907 }
908
909 return 0;
910 }
911
912 static int
913 bnx2_set_mac_link(struct bnx2 *bp)
914 {
915 u32 val;
916
917 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
918 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
919 (bp->duplex == DUPLEX_HALF)) {
920 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
921 }
922
923 /* Configure the EMAC mode register. */
924 val = REG_RD(bp, BNX2_EMAC_MODE);
925
926 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
927 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
928 BNX2_EMAC_MODE_25G_MODE);
929
930 if (bp->link_up) {
931 switch (bp->line_speed) {
932 case SPEED_10:
933 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
934 val |= BNX2_EMAC_MODE_PORT_MII_10M;
935 break;
936 }
937 /* fall through */
938 case SPEED_100:
939 val |= BNX2_EMAC_MODE_PORT_MII;
940 break;
941 case SPEED_2500:
942 val |= BNX2_EMAC_MODE_25G_MODE;
943 /* fall through */
944 case SPEED_1000:
945 val |= BNX2_EMAC_MODE_PORT_GMII;
946 break;
947 }
948 }
949 else {
950 val |= BNX2_EMAC_MODE_PORT_GMII;
951 }
952
953 /* Set the MAC to operate in the appropriate duplex mode. */
954 if (bp->duplex == DUPLEX_HALF)
955 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
956 REG_WR(bp, BNX2_EMAC_MODE, val);
957
958 /* Enable/disable rx PAUSE. */
959 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
960
961 if (bp->flow_ctrl & FLOW_CTRL_RX)
962 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
963 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
964
965 /* Enable/disable tx PAUSE. */
966 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
967 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
968
969 if (bp->flow_ctrl & FLOW_CTRL_TX)
970 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
971 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
972
973 /* Acknowledge the interrupt. */
974 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
975
976 return 0;
977 }
978
979 static void
980 bnx2_enable_bmsr1(struct bnx2 *bp)
981 {
982 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
983 (CHIP_NUM(bp) == CHIP_NUM_5709))
984 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
985 MII_BNX2_BLK_ADDR_GP_STATUS);
986 }
987
988 static void
989 bnx2_disable_bmsr1(struct bnx2 *bp)
990 {
991 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
992 (CHIP_NUM(bp) == CHIP_NUM_5709))
993 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
994 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
995 }
996
997 static int
998 bnx2_test_and_enable_2g5(struct bnx2 *bp)
999 {
1000 u32 up1;
1001 int ret = 1;
1002
1003 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1004 return 0;
1005
1006 if (bp->autoneg & AUTONEG_SPEED)
1007 bp->advertising |= ADVERTISED_2500baseX_Full;
1008
1009 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1010 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1011
1012 bnx2_read_phy(bp, bp->mii_up1, &up1);
1013 if (!(up1 & BCM5708S_UP1_2G5)) {
1014 up1 |= BCM5708S_UP1_2G5;
1015 bnx2_write_phy(bp, bp->mii_up1, up1);
1016 ret = 0;
1017 }
1018
1019 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1020 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1021 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1022
1023 return ret;
1024 }
1025
1026 static int
1027 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1028 {
1029 u32 up1;
1030 int ret = 0;
1031
1032 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1033 return 0;
1034
1035 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1036 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1037
1038 bnx2_read_phy(bp, bp->mii_up1, &up1);
1039 if (up1 & BCM5708S_UP1_2G5) {
1040 up1 &= ~BCM5708S_UP1_2G5;
1041 bnx2_write_phy(bp, bp->mii_up1, up1);
1042 ret = 1;
1043 }
1044
1045 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1046 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1047 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1048
1049 return ret;
1050 }
1051
1052 static void
1053 bnx2_enable_forced_2g5(struct bnx2 *bp)
1054 {
1055 u32 bmcr;
1056
1057 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1058 return;
1059
1060 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1061 u32 val;
1062
1063 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1064 MII_BNX2_BLK_ADDR_SERDES_DIG);
1065 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1066 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1067 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1068 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1069
1070 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1071 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1072 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1073
1074 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1075 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1076 bmcr |= BCM5708S_BMCR_FORCE_2500;
1077 }
1078
1079 if (bp->autoneg & AUTONEG_SPEED) {
1080 bmcr &= ~BMCR_ANENABLE;
1081 if (bp->req_duplex == DUPLEX_FULL)
1082 bmcr |= BMCR_FULLDPLX;
1083 }
1084 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1085 }
1086
1087 static void
1088 bnx2_disable_forced_2g5(struct bnx2 *bp)
1089 {
1090 u32 bmcr;
1091
1092 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1093 return;
1094
1095 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1096 u32 val;
1097
1098 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1099 MII_BNX2_BLK_ADDR_SERDES_DIG);
1100 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1101 val &= ~MII_BNX2_SD_MISC1_FORCE;
1102 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1103
1104 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1105 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1106 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1107
1108 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1109 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1110 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1111 }
1112
1113 if (bp->autoneg & AUTONEG_SPEED)
1114 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1115 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1116 }
1117
1118 static int
1119 bnx2_set_link(struct bnx2 *bp)
1120 {
1121 u32 bmsr;
1122 u8 link_up;
1123
1124 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1125 bp->link_up = 1;
1126 return 0;
1127 }
1128
1129 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1130 return 0;
1131
1132 link_up = bp->link_up;
1133
1134 bnx2_enable_bmsr1(bp);
1135 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1136 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1137 bnx2_disable_bmsr1(bp);
1138
1139 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1140 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1141 u32 val;
1142
1143 val = REG_RD(bp, BNX2_EMAC_STATUS);
1144 if (val & BNX2_EMAC_STATUS_LINK)
1145 bmsr |= BMSR_LSTATUS;
1146 else
1147 bmsr &= ~BMSR_LSTATUS;
1148 }
1149
1150 if (bmsr & BMSR_LSTATUS) {
1151 bp->link_up = 1;
1152
1153 if (bp->phy_flags & PHY_SERDES_FLAG) {
1154 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1155 bnx2_5706s_linkup(bp);
1156 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1157 bnx2_5708s_linkup(bp);
1158 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1159 bnx2_5709s_linkup(bp);
1160 }
1161 else {
1162 bnx2_copper_linkup(bp);
1163 }
1164 bnx2_resolve_flow_ctrl(bp);
1165 }
1166 else {
1167 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1168 (bp->autoneg & AUTONEG_SPEED))
1169 bnx2_disable_forced_2g5(bp);
1170
1171 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1172 bp->link_up = 0;
1173 }
1174
1175 if (bp->link_up != link_up) {
1176 bnx2_report_link(bp);
1177 }
1178
1179 bnx2_set_mac_link(bp);
1180
1181 return 0;
1182 }
1183
1184 static int
1185 bnx2_reset_phy(struct bnx2 *bp)
1186 {
1187 int i;
1188 u32 reg;
1189
1190 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1191
1192 #define PHY_RESET_MAX_WAIT 100
1193 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1194 udelay(10);
1195
1196 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1197 if (!(reg & BMCR_RESET)) {
1198 udelay(20);
1199 break;
1200 }
1201 }
1202 if (i == PHY_RESET_MAX_WAIT) {
1203 return -EBUSY;
1204 }
1205 return 0;
1206 }
1207
1208 static u32
1209 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1210 {
1211 u32 adv = 0;
1212
1213 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1214 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1215
1216 if (bp->phy_flags & PHY_SERDES_FLAG) {
1217 adv = ADVERTISE_1000XPAUSE;
1218 }
1219 else {
1220 adv = ADVERTISE_PAUSE_CAP;
1221 }
1222 }
1223 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1224 if (bp->phy_flags & PHY_SERDES_FLAG) {
1225 adv = ADVERTISE_1000XPSE_ASYM;
1226 }
1227 else {
1228 adv = ADVERTISE_PAUSE_ASYM;
1229 }
1230 }
1231 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1232 if (bp->phy_flags & PHY_SERDES_FLAG) {
1233 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1234 }
1235 else {
1236 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1237 }
1238 }
1239 return adv;
1240 }
1241
1242 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1243
1244 static int
1245 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1246 {
1247 u32 speed_arg = 0, pause_adv;
1248
1249 pause_adv = bnx2_phy_get_pause_adv(bp);
1250
1251 if (bp->autoneg & AUTONEG_SPEED) {
1252 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1253 if (bp->advertising & ADVERTISED_10baseT_Half)
1254 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1255 if (bp->advertising & ADVERTISED_10baseT_Full)
1256 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1257 if (bp->advertising & ADVERTISED_100baseT_Half)
1258 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1259 if (bp->advertising & ADVERTISED_100baseT_Full)
1260 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1261 if (bp->advertising & ADVERTISED_1000baseT_Full)
1262 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1263 if (bp->advertising & ADVERTISED_2500baseX_Full)
1264 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1265 } else {
1266 if (bp->req_line_speed == SPEED_2500)
1267 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1268 else if (bp->req_line_speed == SPEED_1000)
1269 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1270 else if (bp->req_line_speed == SPEED_100) {
1271 if (bp->req_duplex == DUPLEX_FULL)
1272 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1273 else
1274 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1275 } else if (bp->req_line_speed == SPEED_10) {
1276 if (bp->req_duplex == DUPLEX_FULL)
1277 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1278 else
1279 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1280 }
1281 }
1282
1283 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1284 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1285 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1286 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1287
1288 if (port == PORT_TP)
1289 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1290 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1291
1292 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1293
1294 spin_unlock_bh(&bp->phy_lock);
1295 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1296 spin_lock_bh(&bp->phy_lock);
1297
1298 return 0;
1299 }
1300
1301 static int
1302 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1303 {
1304 u32 adv, bmcr;
1305 u32 new_adv = 0;
1306
1307 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1308 return (bnx2_setup_remote_phy(bp, port));
1309
1310 if (!(bp->autoneg & AUTONEG_SPEED)) {
1311 u32 new_bmcr;
1312 int force_link_down = 0;
1313
1314 if (bp->req_line_speed == SPEED_2500) {
1315 if (!bnx2_test_and_enable_2g5(bp))
1316 force_link_down = 1;
1317 } else if (bp->req_line_speed == SPEED_1000) {
1318 if (bnx2_test_and_disable_2g5(bp))
1319 force_link_down = 1;
1320 }
1321 bnx2_read_phy(bp, bp->mii_adv, &adv);
1322 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1323
1324 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1325 new_bmcr = bmcr & ~BMCR_ANENABLE;
1326 new_bmcr |= BMCR_SPEED1000;
1327
1328 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1329 if (bp->req_line_speed == SPEED_2500)
1330 bnx2_enable_forced_2g5(bp);
1331 else if (bp->req_line_speed == SPEED_1000) {
1332 bnx2_disable_forced_2g5(bp);
1333 new_bmcr &= ~0x2000;
1334 }
1335
1336 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1337 if (bp->req_line_speed == SPEED_2500)
1338 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1339 else
1340 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1341 }
1342
1343 if (bp->req_duplex == DUPLEX_FULL) {
1344 adv |= ADVERTISE_1000XFULL;
1345 new_bmcr |= BMCR_FULLDPLX;
1346 }
1347 else {
1348 adv |= ADVERTISE_1000XHALF;
1349 new_bmcr &= ~BMCR_FULLDPLX;
1350 }
1351 if ((new_bmcr != bmcr) || (force_link_down)) {
1352 /* Force a link down visible on the other side */
1353 if (bp->link_up) {
1354 bnx2_write_phy(bp, bp->mii_adv, adv &
1355 ~(ADVERTISE_1000XFULL |
1356 ADVERTISE_1000XHALF));
1357 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1358 BMCR_ANRESTART | BMCR_ANENABLE);
1359
1360 bp->link_up = 0;
1361 netif_carrier_off(bp->dev);
1362 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1363 bnx2_report_link(bp);
1364 }
1365 bnx2_write_phy(bp, bp->mii_adv, adv);
1366 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1367 } else {
1368 bnx2_resolve_flow_ctrl(bp);
1369 bnx2_set_mac_link(bp);
1370 }
1371 return 0;
1372 }
1373
1374 bnx2_test_and_enable_2g5(bp);
1375
1376 if (bp->advertising & ADVERTISED_1000baseT_Full)
1377 new_adv |= ADVERTISE_1000XFULL;
1378
1379 new_adv |= bnx2_phy_get_pause_adv(bp);
1380
1381 bnx2_read_phy(bp, bp->mii_adv, &adv);
1382 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1383
1384 bp->serdes_an_pending = 0;
1385 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1386 /* Force a link down visible on the other side */
1387 if (bp->link_up) {
1388 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1389 spin_unlock_bh(&bp->phy_lock);
1390 msleep(20);
1391 spin_lock_bh(&bp->phy_lock);
1392 }
1393
1394 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1395 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1396 BMCR_ANENABLE);
1397 /* Speed up link-up time when the link partner
1398 * does not autonegotiate which is very common
1399 * in blade servers. Some blade servers use
1400 * IPMI for kerboard input and it's important
1401 * to minimize link disruptions. Autoneg. involves
1402 * exchanging base pages plus 3 next pages and
1403 * normally completes in about 120 msec.
1404 */
1405 bp->current_interval = SERDES_AN_TIMEOUT;
1406 bp->serdes_an_pending = 1;
1407 mod_timer(&bp->timer, jiffies + bp->current_interval);
1408 } else {
1409 bnx2_resolve_flow_ctrl(bp);
1410 bnx2_set_mac_link(bp);
1411 }
1412
1413 return 0;
1414 }
1415
1416 #define ETHTOOL_ALL_FIBRE_SPEED \
1417 (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ? \
1418 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1419 (ADVERTISED_1000baseT_Full)
1420
1421 #define ETHTOOL_ALL_COPPER_SPEED \
1422 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1423 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1424 ADVERTISED_1000baseT_Full)
1425
1426 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1427 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1428
1429 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1430
1431 static void
1432 bnx2_set_default_remote_link(struct bnx2 *bp)
1433 {
1434 u32 link;
1435
1436 if (bp->phy_port == PORT_TP)
1437 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1438 else
1439 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1440
1441 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1442 bp->req_line_speed = 0;
1443 bp->autoneg |= AUTONEG_SPEED;
1444 bp->advertising = ADVERTISED_Autoneg;
1445 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1446 bp->advertising |= ADVERTISED_10baseT_Half;
1447 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1448 bp->advertising |= ADVERTISED_10baseT_Full;
1449 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1450 bp->advertising |= ADVERTISED_100baseT_Half;
1451 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1452 bp->advertising |= ADVERTISED_100baseT_Full;
1453 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1454 bp->advertising |= ADVERTISED_1000baseT_Full;
1455 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1456 bp->advertising |= ADVERTISED_2500baseX_Full;
1457 } else {
1458 bp->autoneg = 0;
1459 bp->advertising = 0;
1460 bp->req_duplex = DUPLEX_FULL;
1461 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1462 bp->req_line_speed = SPEED_10;
1463 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1464 bp->req_duplex = DUPLEX_HALF;
1465 }
1466 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1467 bp->req_line_speed = SPEED_100;
1468 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1469 bp->req_duplex = DUPLEX_HALF;
1470 }
1471 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1472 bp->req_line_speed = SPEED_1000;
1473 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1474 bp->req_line_speed = SPEED_2500;
1475 }
1476 }
1477
1478 static void
1479 bnx2_set_default_link(struct bnx2 *bp)
1480 {
1481 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1482 return bnx2_set_default_remote_link(bp);
1483
1484 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1485 bp->req_line_speed = 0;
1486 if (bp->phy_flags & PHY_SERDES_FLAG) {
1487 u32 reg;
1488
1489 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1490
1491 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1492 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1493 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1494 bp->autoneg = 0;
1495 bp->req_line_speed = bp->line_speed = SPEED_1000;
1496 bp->req_duplex = DUPLEX_FULL;
1497 }
1498 } else
1499 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1500 }
1501
1502 static void
1503 bnx2_send_heart_beat(struct bnx2 *bp)
1504 {
1505 u32 msg;
1506 u32 addr;
1507
1508 spin_lock(&bp->indirect_lock);
1509 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1510 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1511 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1512 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1513 spin_unlock(&bp->indirect_lock);
1514 }
1515
1516 static void
1517 bnx2_remote_phy_event(struct bnx2 *bp)
1518 {
1519 u32 msg;
1520 u8 link_up = bp->link_up;
1521 u8 old_port;
1522
1523 msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1524
1525 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1526 bnx2_send_heart_beat(bp);
1527
1528 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1529
1530 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1531 bp->link_up = 0;
1532 else {
1533 u32 speed;
1534
1535 bp->link_up = 1;
1536 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1537 bp->duplex = DUPLEX_FULL;
1538 switch (speed) {
1539 case BNX2_LINK_STATUS_10HALF:
1540 bp->duplex = DUPLEX_HALF;
1541 case BNX2_LINK_STATUS_10FULL:
1542 bp->line_speed = SPEED_10;
1543 break;
1544 case BNX2_LINK_STATUS_100HALF:
1545 bp->duplex = DUPLEX_HALF;
1546 case BNX2_LINK_STATUS_100BASE_T4:
1547 case BNX2_LINK_STATUS_100FULL:
1548 bp->line_speed = SPEED_100;
1549 break;
1550 case BNX2_LINK_STATUS_1000HALF:
1551 bp->duplex = DUPLEX_HALF;
1552 case BNX2_LINK_STATUS_1000FULL:
1553 bp->line_speed = SPEED_1000;
1554 break;
1555 case BNX2_LINK_STATUS_2500HALF:
1556 bp->duplex = DUPLEX_HALF;
1557 case BNX2_LINK_STATUS_2500FULL:
1558 bp->line_speed = SPEED_2500;
1559 break;
1560 default:
1561 bp->line_speed = 0;
1562 break;
1563 }
1564
1565 spin_lock(&bp->phy_lock);
1566 bp->flow_ctrl = 0;
1567 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1568 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1569 if (bp->duplex == DUPLEX_FULL)
1570 bp->flow_ctrl = bp->req_flow_ctrl;
1571 } else {
1572 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1573 bp->flow_ctrl |= FLOW_CTRL_TX;
1574 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1575 bp->flow_ctrl |= FLOW_CTRL_RX;
1576 }
1577
1578 old_port = bp->phy_port;
1579 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1580 bp->phy_port = PORT_FIBRE;
1581 else
1582 bp->phy_port = PORT_TP;
1583
1584 if (old_port != bp->phy_port)
1585 bnx2_set_default_link(bp);
1586
1587 spin_unlock(&bp->phy_lock);
1588 }
1589 if (bp->link_up != link_up)
1590 bnx2_report_link(bp);
1591
1592 bnx2_set_mac_link(bp);
1593 }
1594
1595 static int
1596 bnx2_set_remote_link(struct bnx2 *bp)
1597 {
1598 u32 evt_code;
1599
1600 evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1601 switch (evt_code) {
1602 case BNX2_FW_EVT_CODE_LINK_EVENT:
1603 bnx2_remote_phy_event(bp);
1604 break;
1605 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1606 default:
1607 bnx2_send_heart_beat(bp);
1608 break;
1609 }
1610 return 0;
1611 }
1612
1613 static int
1614 bnx2_setup_copper_phy(struct bnx2 *bp)
1615 {
1616 u32 bmcr;
1617 u32 new_bmcr;
1618
1619 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1620
1621 if (bp->autoneg & AUTONEG_SPEED) {
1622 u32 adv_reg, adv1000_reg;
1623 u32 new_adv_reg = 0;
1624 u32 new_adv1000_reg = 0;
1625
1626 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1627 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1628 ADVERTISE_PAUSE_ASYM);
1629
1630 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1631 adv1000_reg &= PHY_ALL_1000_SPEED;
1632
1633 if (bp->advertising & ADVERTISED_10baseT_Half)
1634 new_adv_reg |= ADVERTISE_10HALF;
1635 if (bp->advertising & ADVERTISED_10baseT_Full)
1636 new_adv_reg |= ADVERTISE_10FULL;
1637 if (bp->advertising & ADVERTISED_100baseT_Half)
1638 new_adv_reg |= ADVERTISE_100HALF;
1639 if (bp->advertising & ADVERTISED_100baseT_Full)
1640 new_adv_reg |= ADVERTISE_100FULL;
1641 if (bp->advertising & ADVERTISED_1000baseT_Full)
1642 new_adv1000_reg |= ADVERTISE_1000FULL;
1643
1644 new_adv_reg |= ADVERTISE_CSMA;
1645
1646 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1647
1648 if ((adv1000_reg != new_adv1000_reg) ||
1649 (adv_reg != new_adv_reg) ||
1650 ((bmcr & BMCR_ANENABLE) == 0)) {
1651
1652 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1653 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1654 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1655 BMCR_ANENABLE);
1656 }
1657 else if (bp->link_up) {
1658 /* Flow ctrl may have changed from auto to forced */
1659 /* or vice-versa. */
1660
1661 bnx2_resolve_flow_ctrl(bp);
1662 bnx2_set_mac_link(bp);
1663 }
1664 return 0;
1665 }
1666
1667 new_bmcr = 0;
1668 if (bp->req_line_speed == SPEED_100) {
1669 new_bmcr |= BMCR_SPEED100;
1670 }
1671 if (bp->req_duplex == DUPLEX_FULL) {
1672 new_bmcr |= BMCR_FULLDPLX;
1673 }
1674 if (new_bmcr != bmcr) {
1675 u32 bmsr;
1676
1677 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1678 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1679
1680 if (bmsr & BMSR_LSTATUS) {
1681 /* Force link down */
1682 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1683 spin_unlock_bh(&bp->phy_lock);
1684 msleep(50);
1685 spin_lock_bh(&bp->phy_lock);
1686
1687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1689 }
1690
1691 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1692
1693 /* Normally, the new speed is setup after the link has
1694 * gone down and up again. In some cases, link will not go
1695 * down so we need to set up the new speed here.
1696 */
1697 if (bmsr & BMSR_LSTATUS) {
1698 bp->line_speed = bp->req_line_speed;
1699 bp->duplex = bp->req_duplex;
1700 bnx2_resolve_flow_ctrl(bp);
1701 bnx2_set_mac_link(bp);
1702 }
1703 } else {
1704 bnx2_resolve_flow_ctrl(bp);
1705 bnx2_set_mac_link(bp);
1706 }
1707 return 0;
1708 }
1709
1710 static int
1711 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1712 {
1713 if (bp->loopback == MAC_LOOPBACK)
1714 return 0;
1715
1716 if (bp->phy_flags & PHY_SERDES_FLAG) {
1717 return (bnx2_setup_serdes_phy(bp, port));
1718 }
1719 else {
1720 return (bnx2_setup_copper_phy(bp));
1721 }
1722 }
1723
1724 static int
1725 bnx2_init_5709s_phy(struct bnx2 *bp)
1726 {
1727 u32 val;
1728
1729 bp->mii_bmcr = MII_BMCR + 0x10;
1730 bp->mii_bmsr = MII_BMSR + 0x10;
1731 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1732 bp->mii_adv = MII_ADVERTISE + 0x10;
1733 bp->mii_lpa = MII_LPA + 0x10;
1734 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1735
1736 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1737 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1738
1739 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1740 bnx2_reset_phy(bp);
1741
1742 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1743
1744 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1745 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1746 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1747 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1748
1749 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1750 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1751 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1752 val |= BCM5708S_UP1_2G5;
1753 else
1754 val &= ~BCM5708S_UP1_2G5;
1755 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1756
1757 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1758 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1759 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1760 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1761
1762 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1763
1764 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1765 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1766 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1767
1768 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1769
1770 return 0;
1771 }
1772
1773 static int
1774 bnx2_init_5708s_phy(struct bnx2 *bp)
1775 {
1776 u32 val;
1777
1778 bnx2_reset_phy(bp);
1779
1780 bp->mii_up1 = BCM5708S_UP1;
1781
1782 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1783 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1784 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1785
1786 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1787 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1788 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1789
1790 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1791 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1792 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1793
1794 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1795 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1796 val |= BCM5708S_UP1_2G5;
1797 bnx2_write_phy(bp, BCM5708S_UP1, val);
1798 }
1799
1800 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1801 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1802 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1803 /* increase tx signal amplitude */
1804 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1805 BCM5708S_BLK_ADDR_TX_MISC);
1806 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1807 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1808 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1809 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1810 }
1811
1812 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1813 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1814
1815 if (val) {
1816 u32 is_backplane;
1817
1818 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1819 BNX2_SHARED_HW_CFG_CONFIG);
1820 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1821 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1822 BCM5708S_BLK_ADDR_TX_MISC);
1823 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1824 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1825 BCM5708S_BLK_ADDR_DIG);
1826 }
1827 }
1828 return 0;
1829 }
1830
1831 static int
1832 bnx2_init_5706s_phy(struct bnx2 *bp)
1833 {
1834 bnx2_reset_phy(bp);
1835
1836 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1837
1838 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1839 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1840
1841 if (bp->dev->mtu > 1500) {
1842 u32 val;
1843
1844 /* Set extended packet length bit */
1845 bnx2_write_phy(bp, 0x18, 0x7);
1846 bnx2_read_phy(bp, 0x18, &val);
1847 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1848
1849 bnx2_write_phy(bp, 0x1c, 0x6c00);
1850 bnx2_read_phy(bp, 0x1c, &val);
1851 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1852 }
1853 else {
1854 u32 val;
1855
1856 bnx2_write_phy(bp, 0x18, 0x7);
1857 bnx2_read_phy(bp, 0x18, &val);
1858 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1859
1860 bnx2_write_phy(bp, 0x1c, 0x6c00);
1861 bnx2_read_phy(bp, 0x1c, &val);
1862 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1863 }
1864
1865 return 0;
1866 }
1867
1868 static int
1869 bnx2_init_copper_phy(struct bnx2 *bp)
1870 {
1871 u32 val;
1872
1873 bnx2_reset_phy(bp);
1874
1875 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1876 bnx2_write_phy(bp, 0x18, 0x0c00);
1877 bnx2_write_phy(bp, 0x17, 0x000a);
1878 bnx2_write_phy(bp, 0x15, 0x310b);
1879 bnx2_write_phy(bp, 0x17, 0x201f);
1880 bnx2_write_phy(bp, 0x15, 0x9506);
1881 bnx2_write_phy(bp, 0x17, 0x401f);
1882 bnx2_write_phy(bp, 0x15, 0x14e2);
1883 bnx2_write_phy(bp, 0x18, 0x0400);
1884 }
1885
1886 if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1887 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1888 MII_BNX2_DSP_EXPAND_REG | 0x8);
1889 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1890 val &= ~(1 << 8);
1891 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1892 }
1893
1894 if (bp->dev->mtu > 1500) {
1895 /* Set extended packet length bit */
1896 bnx2_write_phy(bp, 0x18, 0x7);
1897 bnx2_read_phy(bp, 0x18, &val);
1898 bnx2_write_phy(bp, 0x18, val | 0x4000);
1899
1900 bnx2_read_phy(bp, 0x10, &val);
1901 bnx2_write_phy(bp, 0x10, val | 0x1);
1902 }
1903 else {
1904 bnx2_write_phy(bp, 0x18, 0x7);
1905 bnx2_read_phy(bp, 0x18, &val);
1906 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1907
1908 bnx2_read_phy(bp, 0x10, &val);
1909 bnx2_write_phy(bp, 0x10, val & ~0x1);
1910 }
1911
1912 /* ethernet@wirespeed */
1913 bnx2_write_phy(bp, 0x18, 0x7007);
1914 bnx2_read_phy(bp, 0x18, &val);
1915 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1916 return 0;
1917 }
1918
1919
1920 static int
1921 bnx2_init_phy(struct bnx2 *bp)
1922 {
1923 u32 val;
1924 int rc = 0;
1925
1926 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1927 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1928
1929 bp->mii_bmcr = MII_BMCR;
1930 bp->mii_bmsr = MII_BMSR;
1931 bp->mii_bmsr1 = MII_BMSR;
1932 bp->mii_adv = MII_ADVERTISE;
1933 bp->mii_lpa = MII_LPA;
1934
1935 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1936
1937 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1938 goto setup_phy;
1939
1940 bnx2_read_phy(bp, MII_PHYSID1, &val);
1941 bp->phy_id = val << 16;
1942 bnx2_read_phy(bp, MII_PHYSID2, &val);
1943 bp->phy_id |= val & 0xffff;
1944
1945 if (bp->phy_flags & PHY_SERDES_FLAG) {
1946 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1947 rc = bnx2_init_5706s_phy(bp);
1948 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1949 rc = bnx2_init_5708s_phy(bp);
1950 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1951 rc = bnx2_init_5709s_phy(bp);
1952 }
1953 else {
1954 rc = bnx2_init_copper_phy(bp);
1955 }
1956
1957 setup_phy:
1958 if (!rc)
1959 rc = bnx2_setup_phy(bp, bp->phy_port);
1960
1961 return rc;
1962 }
1963
1964 static int
1965 bnx2_set_mac_loopback(struct bnx2 *bp)
1966 {
1967 u32 mac_mode;
1968
1969 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1970 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1971 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1972 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1973 bp->link_up = 1;
1974 return 0;
1975 }
1976
1977 static int bnx2_test_link(struct bnx2 *);
1978
1979 static int
1980 bnx2_set_phy_loopback(struct bnx2 *bp)
1981 {
1982 u32 mac_mode;
1983 int rc, i;
1984
1985 spin_lock_bh(&bp->phy_lock);
1986 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1987 BMCR_SPEED1000);
1988 spin_unlock_bh(&bp->phy_lock);
1989 if (rc)
1990 return rc;
1991
1992 for (i = 0; i < 10; i++) {
1993 if (bnx2_test_link(bp) == 0)
1994 break;
1995 msleep(100);
1996 }
1997
1998 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1999 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2000 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2001 BNX2_EMAC_MODE_25G_MODE);
2002
2003 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2004 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2005 bp->link_up = 1;
2006 return 0;
2007 }
2008
2009 static int
2010 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2011 {
2012 int i;
2013 u32 val;
2014
2015 bp->fw_wr_seq++;
2016 msg_data |= bp->fw_wr_seq;
2017
2018 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2019
2020 /* wait for an acknowledgement. */
2021 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2022 msleep(10);
2023
2024 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2025
2026 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2027 break;
2028 }
2029 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2030 return 0;
2031
2032 /* If we timed out, inform the firmware that this is the case. */
2033 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2034 if (!silent)
2035 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2036 "%x\n", msg_data);
2037
2038 msg_data &= ~BNX2_DRV_MSG_CODE;
2039 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2040
2041 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2042
2043 return -EBUSY;
2044 }
2045
2046 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2047 return -EIO;
2048
2049 return 0;
2050 }
2051
2052 static int
2053 bnx2_init_5709_context(struct bnx2 *bp)
2054 {
2055 int i, ret = 0;
2056 u32 val;
2057
2058 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2059 val |= (BCM_PAGE_BITS - 8) << 16;
2060 REG_WR(bp, BNX2_CTX_COMMAND, val);
2061 for (i = 0; i < 10; i++) {
2062 val = REG_RD(bp, BNX2_CTX_COMMAND);
2063 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2064 break;
2065 udelay(2);
2066 }
2067 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2068 return -EBUSY;
2069
2070 for (i = 0; i < bp->ctx_pages; i++) {
2071 int j;
2072
2073 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2074 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2075 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2076 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2077 (u64) bp->ctx_blk_mapping[i] >> 32);
2078 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2079 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2080 for (j = 0; j < 10; j++) {
2081
2082 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2083 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2084 break;
2085 udelay(5);
2086 }
2087 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2088 ret = -EBUSY;
2089 break;
2090 }
2091 }
2092 return ret;
2093 }
2094
2095 static void
2096 bnx2_init_context(struct bnx2 *bp)
2097 {
2098 u32 vcid;
2099
2100 vcid = 96;
2101 while (vcid) {
2102 u32 vcid_addr, pcid_addr, offset;
2103 int i;
2104
2105 vcid--;
2106
2107 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2108 u32 new_vcid;
2109
2110 vcid_addr = GET_PCID_ADDR(vcid);
2111 if (vcid & 0x8) {
2112 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2113 }
2114 else {
2115 new_vcid = vcid;
2116 }
2117 pcid_addr = GET_PCID_ADDR(new_vcid);
2118 }
2119 else {
2120 vcid_addr = GET_CID_ADDR(vcid);
2121 pcid_addr = vcid_addr;
2122 }
2123
2124 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2125 vcid_addr += (i << PHY_CTX_SHIFT);
2126 pcid_addr += (i << PHY_CTX_SHIFT);
2127
2128 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
2129 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2130
2131 /* Zero out the context. */
2132 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2133 CTX_WR(bp, 0x00, offset, 0);
2134
2135 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2136 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2137 }
2138 }
2139 }
2140
2141 static int
2142 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2143 {
2144 u16 *good_mbuf;
2145 u32 good_mbuf_cnt;
2146 u32 val;
2147
2148 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2149 if (good_mbuf == NULL) {
2150 printk(KERN_ERR PFX "Failed to allocate memory in "
2151 "bnx2_alloc_bad_rbuf\n");
2152 return -ENOMEM;
2153 }
2154
2155 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2156 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2157
2158 good_mbuf_cnt = 0;
2159
2160 /* Allocate a bunch of mbufs and save the good ones in an array. */
2161 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2162 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2163 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2164
2165 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2166
2167 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2168
2169 /* The addresses with Bit 9 set are bad memory blocks. */
2170 if (!(val & (1 << 9))) {
2171 good_mbuf[good_mbuf_cnt] = (u16) val;
2172 good_mbuf_cnt++;
2173 }
2174
2175 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2176 }
2177
2178 /* Free the good ones back to the mbuf pool thus discarding
2179 * all the bad ones. */
2180 while (good_mbuf_cnt) {
2181 good_mbuf_cnt--;
2182
2183 val = good_mbuf[good_mbuf_cnt];
2184 val = (val << 9) | val | 1;
2185
2186 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2187 }
2188 kfree(good_mbuf);
2189 return 0;
2190 }
2191
2192 static void
2193 bnx2_set_mac_addr(struct bnx2 *bp)
2194 {
2195 u32 val;
2196 u8 *mac_addr = bp->dev->dev_addr;
2197
2198 val = (mac_addr[0] << 8) | mac_addr[1];
2199
2200 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2201
2202 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2203 (mac_addr[4] << 8) | mac_addr[5];
2204
2205 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2206 }
2207
2208 static inline int
2209 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2210 {
2211 struct sk_buff *skb;
2212 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2213 dma_addr_t mapping;
2214 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2215 unsigned long align;
2216
2217 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2218 if (skb == NULL) {
2219 return -ENOMEM;
2220 }
2221
2222 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2223 skb_reserve(skb, BNX2_RX_ALIGN - align);
2224
2225 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2226 PCI_DMA_FROMDEVICE);
2227
2228 rx_buf->skb = skb;
2229 pci_unmap_addr_set(rx_buf, mapping, mapping);
2230
2231 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2232 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2233
2234 bp->rx_prod_bseq += bp->rx_buf_use_size;
2235
2236 return 0;
2237 }
2238
2239 static int
2240 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2241 {
2242 struct status_block *sblk = bp->status_blk;
2243 u32 new_link_state, old_link_state;
2244 int is_set = 1;
2245
2246 new_link_state = sblk->status_attn_bits & event;
2247 old_link_state = sblk->status_attn_bits_ack & event;
2248 if (new_link_state != old_link_state) {
2249 if (new_link_state)
2250 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2251 else
2252 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2253 } else
2254 is_set = 0;
2255
2256 return is_set;
2257 }
2258
2259 static void
2260 bnx2_phy_int(struct bnx2 *bp)
2261 {
2262 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
2263 spin_lock(&bp->phy_lock);
2264 bnx2_set_link(bp);
2265 spin_unlock(&bp->phy_lock);
2266 }
2267 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT))
2268 bnx2_set_remote_link(bp);
2269
2270 }
2271
2272 static void
2273 bnx2_tx_int(struct bnx2 *bp)
2274 {
2275 struct status_block *sblk = bp->status_blk;
2276 u16 hw_cons, sw_cons, sw_ring_cons;
2277 int tx_free_bd = 0;
2278
2279 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
2280 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2281 hw_cons++;
2282 }
2283 sw_cons = bp->tx_cons;
2284
2285 while (sw_cons != hw_cons) {
2286 struct sw_bd *tx_buf;
2287 struct sk_buff *skb;
2288 int i, last;
2289
2290 sw_ring_cons = TX_RING_IDX(sw_cons);
2291
2292 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2293 skb = tx_buf->skb;
2294
2295 /* partial BD completions possible with TSO packets */
2296 if (skb_is_gso(skb)) {
2297 u16 last_idx, last_ring_idx;
2298
2299 last_idx = sw_cons +
2300 skb_shinfo(skb)->nr_frags + 1;
2301 last_ring_idx = sw_ring_cons +
2302 skb_shinfo(skb)->nr_frags + 1;
2303 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2304 last_idx++;
2305 }
2306 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2307 break;
2308 }
2309 }
2310
2311 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2312 skb_headlen(skb), PCI_DMA_TODEVICE);
2313
2314 tx_buf->skb = NULL;
2315 last = skb_shinfo(skb)->nr_frags;
2316
2317 for (i = 0; i < last; i++) {
2318 sw_cons = NEXT_TX_BD(sw_cons);
2319
2320 pci_unmap_page(bp->pdev,
2321 pci_unmap_addr(
2322 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2323 mapping),
2324 skb_shinfo(skb)->frags[i].size,
2325 PCI_DMA_TODEVICE);
2326 }
2327
2328 sw_cons = NEXT_TX_BD(sw_cons);
2329
2330 tx_free_bd += last + 1;
2331
2332 dev_kfree_skb(skb);
2333
2334 hw_cons = bp->hw_tx_cons =
2335 sblk->status_tx_quick_consumer_index0;
2336
2337 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2338 hw_cons++;
2339 }
2340 }
2341
2342 bp->tx_cons = sw_cons;
2343 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2344 * before checking for netif_queue_stopped(). Without the
2345 * memory barrier, there is a small possibility that bnx2_start_xmit()
2346 * will miss it and cause the queue to be stopped forever.
2347 */
2348 smp_mb();
2349
2350 if (unlikely(netif_queue_stopped(bp->dev)) &&
2351 (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2352 netif_tx_lock(bp->dev);
2353 if ((netif_queue_stopped(bp->dev)) &&
2354 (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2355 netif_wake_queue(bp->dev);
2356 netif_tx_unlock(bp->dev);
2357 }
2358 }
2359
2360 static inline void
2361 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2362 u16 cons, u16 prod)
2363 {
2364 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2365 struct rx_bd *cons_bd, *prod_bd;
2366
2367 cons_rx_buf = &bp->rx_buf_ring[cons];
2368 prod_rx_buf = &bp->rx_buf_ring[prod];
2369
2370 pci_dma_sync_single_for_device(bp->pdev,
2371 pci_unmap_addr(cons_rx_buf, mapping),
2372 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2373
2374 bp->rx_prod_bseq += bp->rx_buf_use_size;
2375
2376 prod_rx_buf->skb = skb;
2377
2378 if (cons == prod)
2379 return;
2380
2381 pci_unmap_addr_set(prod_rx_buf, mapping,
2382 pci_unmap_addr(cons_rx_buf, mapping));
2383
2384 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2385 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2386 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2387 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2388 }
2389
2390 static int
2391 bnx2_rx_int(struct bnx2 *bp, int budget)
2392 {
2393 struct status_block *sblk = bp->status_blk;
2394 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2395 struct l2_fhdr *rx_hdr;
2396 int rx_pkt = 0;
2397
2398 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
2399 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2400 hw_cons++;
2401 }
2402 sw_cons = bp->rx_cons;
2403 sw_prod = bp->rx_prod;
2404
2405 /* Memory barrier necessary as speculative reads of the rx
2406 * buffer can be ahead of the index in the status block
2407 */
2408 rmb();
2409 while (sw_cons != hw_cons) {
2410 unsigned int len;
2411 u32 status;
2412 struct sw_bd *rx_buf;
2413 struct sk_buff *skb;
2414 dma_addr_t dma_addr;
2415
2416 sw_ring_cons = RX_RING_IDX(sw_cons);
2417 sw_ring_prod = RX_RING_IDX(sw_prod);
2418
2419 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2420 skb = rx_buf->skb;
2421
2422 rx_buf->skb = NULL;
2423
2424 dma_addr = pci_unmap_addr(rx_buf, mapping);
2425
2426 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2427 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2428
2429 rx_hdr = (struct l2_fhdr *) skb->data;
2430 len = rx_hdr->l2_fhdr_pkt_len - 4;
2431
2432 if ((status = rx_hdr->l2_fhdr_status) &
2433 (L2_FHDR_ERRORS_BAD_CRC |
2434 L2_FHDR_ERRORS_PHY_DECODE |
2435 L2_FHDR_ERRORS_ALIGNMENT |
2436 L2_FHDR_ERRORS_TOO_SHORT |
2437 L2_FHDR_ERRORS_GIANT_FRAME)) {
2438
2439 goto reuse_rx;
2440 }
2441
2442 /* Since we don't have a jumbo ring, copy small packets
2443 * if mtu > 1500
2444 */
2445 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
2446 struct sk_buff *new_skb;
2447
2448 new_skb = netdev_alloc_skb(bp->dev, len + 2);
2449 if (new_skb == NULL)
2450 goto reuse_rx;
2451
2452 /* aligned copy */
2453 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2454 new_skb->data, len + 2);
2455 skb_reserve(new_skb, 2);
2456 skb_put(new_skb, len);
2457
2458 bnx2_reuse_rx_skb(bp, skb,
2459 sw_ring_cons, sw_ring_prod);
2460
2461 skb = new_skb;
2462 }
2463 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
2464 pci_unmap_single(bp->pdev, dma_addr,
2465 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
2466
2467 skb_reserve(skb, bp->rx_offset);
2468 skb_put(skb, len);
2469 }
2470 else {
2471 reuse_rx:
2472 bnx2_reuse_rx_skb(bp, skb,
2473 sw_ring_cons, sw_ring_prod);
2474 goto next_rx;
2475 }
2476
2477 skb->protocol = eth_type_trans(skb, bp->dev);
2478
2479 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2480 (ntohs(skb->protocol) != 0x8100)) {
2481
2482 dev_kfree_skb(skb);
2483 goto next_rx;
2484
2485 }
2486
2487 skb->ip_summed = CHECKSUM_NONE;
2488 if (bp->rx_csum &&
2489 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2490 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2491
2492 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2493 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2494 skb->ip_summed = CHECKSUM_UNNECESSARY;
2495 }
2496
2497 #ifdef BCM_VLAN
2498 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2499 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2500 rx_hdr->l2_fhdr_vlan_tag);
2501 }
2502 else
2503 #endif
2504 netif_receive_skb(skb);
2505
2506 bp->dev->last_rx = jiffies;
2507 rx_pkt++;
2508
2509 next_rx:
2510 sw_cons = NEXT_RX_BD(sw_cons);
2511 sw_prod = NEXT_RX_BD(sw_prod);
2512
2513 if ((rx_pkt == budget))
2514 break;
2515
2516 /* Refresh hw_cons to see if there is new work */
2517 if (sw_cons == hw_cons) {
2518 hw_cons = bp->hw_rx_cons =
2519 sblk->status_rx_quick_consumer_index0;
2520 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
2521 hw_cons++;
2522 rmb();
2523 }
2524 }
2525 bp->rx_cons = sw_cons;
2526 bp->rx_prod = sw_prod;
2527
2528 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2529
2530 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2531
2532 mmiowb();
2533
2534 return rx_pkt;
2535
2536 }
2537
2538 /* MSI ISR - The only difference between this and the INTx ISR
2539 * is that the MSI interrupt is always serviced.
2540 */
2541 static irqreturn_t
2542 bnx2_msi(int irq, void *dev_instance)
2543 {
2544 struct net_device *dev = dev_instance;
2545 struct bnx2 *bp = netdev_priv(dev);
2546
2547 prefetch(bp->status_blk);
2548 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2549 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2550 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2551
2552 /* Return here if interrupt is disabled. */
2553 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2554 return IRQ_HANDLED;
2555
2556 netif_rx_schedule(dev, &bp->napi);
2557
2558 return IRQ_HANDLED;
2559 }
2560
2561 static irqreturn_t
2562 bnx2_msi_1shot(int irq, void *dev_instance)
2563 {
2564 struct net_device *dev = dev_instance;
2565 struct bnx2 *bp = netdev_priv(dev);
2566
2567 prefetch(bp->status_blk);
2568
2569 /* Return here if interrupt is disabled. */
2570 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2571 return IRQ_HANDLED;
2572
2573 netif_rx_schedule(dev, &bp->napi);
2574
2575 return IRQ_HANDLED;
2576 }
2577
2578 static irqreturn_t
2579 bnx2_interrupt(int irq, void *dev_instance)
2580 {
2581 struct net_device *dev = dev_instance;
2582 struct bnx2 *bp = netdev_priv(dev);
2583 struct status_block *sblk = bp->status_blk;
2584
2585 /* When using INTx, it is possible for the interrupt to arrive
2586 * at the CPU before the status block posted prior to the
2587 * interrupt. Reading a register will flush the status block.
2588 * When using MSI, the MSI message will always complete after
2589 * the status block write.
2590 */
2591 if ((sblk->status_idx == bp->last_status_idx) &&
2592 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2593 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2594 return IRQ_NONE;
2595
2596 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2597 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2598 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2599
2600 /* Read back to deassert IRQ immediately to avoid too many
2601 * spurious interrupts.
2602 */
2603 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2604
2605 /* Return here if interrupt is shared and is disabled. */
2606 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2607 return IRQ_HANDLED;
2608
2609 if (netif_rx_schedule_prep(dev, &bp->napi)) {
2610 bp->last_status_idx = sblk->status_idx;
2611 __netif_rx_schedule(dev, &bp->napi);
2612 }
2613
2614 return IRQ_HANDLED;
2615 }
2616
2617 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2618 STATUS_ATTN_BITS_TIMER_ABORT)
2619
2620 static inline int
2621 bnx2_has_work(struct bnx2 *bp)
2622 {
2623 struct status_block *sblk = bp->status_blk;
2624
2625 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2626 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2627 return 1;
2628
2629 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2630 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2631 return 1;
2632
2633 return 0;
2634 }
2635
2636 static int bnx2_poll_work(struct bnx2 *bp, int work_done, int budget)
2637 {
2638 struct status_block *sblk = bp->status_blk;
2639 u32 status_attn_bits = sblk->status_attn_bits;
2640 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2641
2642 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2643 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2644
2645 bnx2_phy_int(bp);
2646
2647 /* This is needed to take care of transient status
2648 * during link changes.
2649 */
2650 REG_WR(bp, BNX2_HC_COMMAND,
2651 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2652 REG_RD(bp, BNX2_HC_COMMAND);
2653 }
2654
2655 if (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2656 bnx2_tx_int(bp);
2657
2658 if (sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons)
2659 work_done += bnx2_rx_int(bp, budget - work_done);
2660
2661 return work_done;
2662 }
2663
2664 static int bnx2_poll(struct napi_struct *napi, int budget)
2665 {
2666 struct bnx2 *bp = container_of(napi, struct bnx2, napi);
2667 int work_done = 0;
2668 struct status_block *sblk = bp->status_blk;
2669
2670 while (1) {
2671 work_done = bnx2_poll_work(bp, work_done, budget);
2672
2673 if (unlikely(work_done >= budget))
2674 break;
2675
2676 /* bp->last_status_idx is used below to tell the hw how
2677 * much work has been processed, so we must read it before
2678 * checking for more work.
2679 */
2680 bp->last_status_idx = sblk->status_idx;
2681 rmb();
2682 if (likely(!bnx2_has_work(bp))) {
2683 netif_rx_complete(bp->dev, napi);
2684 if (likely(bp->flags & USING_MSI_FLAG)) {
2685 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2686 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2687 bp->last_status_idx);
2688 break;
2689 }
2690 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2691 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2692 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2693 bp->last_status_idx);
2694
2695 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2696 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2697 bp->last_status_idx);
2698 break;
2699 }
2700 }
2701
2702 return work_done;
2703 }
2704
2705 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2706 * from set_multicast.
2707 */
2708 static void
2709 bnx2_set_rx_mode(struct net_device *dev)
2710 {
2711 struct bnx2 *bp = netdev_priv(dev);
2712 u32 rx_mode, sort_mode;
2713 int i;
2714
2715 spin_lock_bh(&bp->phy_lock);
2716
2717 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2718 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2719 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2720 #ifdef BCM_VLAN
2721 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2722 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2723 #else
2724 if (!(bp->flags & ASF_ENABLE_FLAG))
2725 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2726 #endif
2727 if (dev->flags & IFF_PROMISC) {
2728 /* Promiscuous mode. */
2729 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2730 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2731 BNX2_RPM_SORT_USER0_PROM_VLAN;
2732 }
2733 else if (dev->flags & IFF_ALLMULTI) {
2734 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2735 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2736 0xffffffff);
2737 }
2738 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2739 }
2740 else {
2741 /* Accept one or more multicast(s). */
2742 struct dev_mc_list *mclist;
2743 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2744 u32 regidx;
2745 u32 bit;
2746 u32 crc;
2747
2748 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2749
2750 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2751 i++, mclist = mclist->next) {
2752
2753 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2754 bit = crc & 0xff;
2755 regidx = (bit & 0xe0) >> 5;
2756 bit &= 0x1f;
2757 mc_filter[regidx] |= (1 << bit);
2758 }
2759
2760 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2761 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2762 mc_filter[i]);
2763 }
2764
2765 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2766 }
2767
2768 if (rx_mode != bp->rx_mode) {
2769 bp->rx_mode = rx_mode;
2770 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2771 }
2772
2773 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2774 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2775 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2776
2777 spin_unlock_bh(&bp->phy_lock);
2778 }
2779
2780 static void
2781 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2782 u32 rv2p_proc)
2783 {
2784 int i;
2785 u32 val;
2786
2787
2788 for (i = 0; i < rv2p_code_len; i += 8) {
2789 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2790 rv2p_code++;
2791 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2792 rv2p_code++;
2793
2794 if (rv2p_proc == RV2P_PROC1) {
2795 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2796 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2797 }
2798 else {
2799 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2800 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2801 }
2802 }
2803
2804 /* Reset the processor, un-stall is done later. */
2805 if (rv2p_proc == RV2P_PROC1) {
2806 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2807 }
2808 else {
2809 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2810 }
2811 }
2812
2813 static int
2814 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2815 {
2816 u32 offset;
2817 u32 val;
2818 int rc;
2819
2820 /* Halt the CPU. */
2821 val = REG_RD_IND(bp, cpu_reg->mode);
2822 val |= cpu_reg->mode_value_halt;
2823 REG_WR_IND(bp, cpu_reg->mode, val);
2824 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2825
2826 /* Load the Text area. */
2827 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2828 if (fw->gz_text) {
2829 int j;
2830
2831 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
2832 fw->gz_text_len);
2833 if (rc < 0)
2834 return rc;
2835
2836 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2837 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2838 }
2839 }
2840
2841 /* Load the Data area. */
2842 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2843 if (fw->data) {
2844 int j;
2845
2846 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2847 REG_WR_IND(bp, offset, fw->data[j]);
2848 }
2849 }
2850
2851 /* Load the SBSS area. */
2852 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2853 if (fw->sbss_len) {
2854 int j;
2855
2856 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2857 REG_WR_IND(bp, offset, 0);
2858 }
2859 }
2860
2861 /* Load the BSS area. */
2862 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2863 if (fw->bss_len) {
2864 int j;
2865
2866 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2867 REG_WR_IND(bp, offset, 0);
2868 }
2869 }
2870
2871 /* Load the Read-Only area. */
2872 offset = cpu_reg->spad_base +
2873 (fw->rodata_addr - cpu_reg->mips_view_base);
2874 if (fw->rodata) {
2875 int j;
2876
2877 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2878 REG_WR_IND(bp, offset, fw->rodata[j]);
2879 }
2880 }
2881
2882 /* Clear the pre-fetch instruction. */
2883 REG_WR_IND(bp, cpu_reg->inst, 0);
2884 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2885
2886 /* Start the CPU. */
2887 val = REG_RD_IND(bp, cpu_reg->mode);
2888 val &= ~cpu_reg->mode_value_halt;
2889 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2890 REG_WR_IND(bp, cpu_reg->mode, val);
2891
2892 return 0;
2893 }
2894
2895 static int
2896 bnx2_init_cpus(struct bnx2 *bp)
2897 {
2898 struct cpu_reg cpu_reg;
2899 struct fw_info *fw;
2900 int rc;
2901 void *text;
2902
2903 /* Initialize the RV2P processor. */
2904 text = vmalloc(FW_BUF_SIZE);
2905 if (!text)
2906 return -ENOMEM;
2907 rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1));
2908 if (rc < 0)
2909 goto init_cpu_err;
2910
2911 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
2912
2913 rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2));
2914 if (rc < 0)
2915 goto init_cpu_err;
2916
2917 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
2918
2919 /* Initialize the RX Processor. */
2920 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2921 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2922 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2923 cpu_reg.state = BNX2_RXP_CPU_STATE;
2924 cpu_reg.state_value_clear = 0xffffff;
2925 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2926 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2927 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2928 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2929 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2930 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2931 cpu_reg.mips_view_base = 0x8000000;
2932
2933 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2934 fw = &bnx2_rxp_fw_09;
2935 else
2936 fw = &bnx2_rxp_fw_06;
2937
2938 fw->text = text;
2939 rc = load_cpu_fw(bp, &cpu_reg, fw);
2940 if (rc)
2941 goto init_cpu_err;
2942
2943 /* Initialize the TX Processor. */
2944 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2945 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2946 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2947 cpu_reg.state = BNX2_TXP_CPU_STATE;
2948 cpu_reg.state_value_clear = 0xffffff;
2949 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2950 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2951 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2952 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2953 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2954 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2955 cpu_reg.mips_view_base = 0x8000000;
2956
2957 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2958 fw = &bnx2_txp_fw_09;
2959 else
2960 fw = &bnx2_txp_fw_06;
2961
2962 fw->text = text;
2963 rc = load_cpu_fw(bp, &cpu_reg, fw);
2964 if (rc)
2965 goto init_cpu_err;
2966
2967 /* Initialize the TX Patch-up Processor. */
2968 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2969 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2970 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2971 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2972 cpu_reg.state_value_clear = 0xffffff;
2973 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2974 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2975 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2976 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2977 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2978 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2979 cpu_reg.mips_view_base = 0x8000000;
2980
2981 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2982 fw = &bnx2_tpat_fw_09;
2983 else
2984 fw = &bnx2_tpat_fw_06;
2985
2986 fw->text = text;
2987 rc = load_cpu_fw(bp, &cpu_reg, fw);
2988 if (rc)
2989 goto init_cpu_err;
2990
2991 /* Initialize the Completion Processor. */
2992 cpu_reg.mode = BNX2_COM_CPU_MODE;
2993 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2994 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2995 cpu_reg.state = BNX2_COM_CPU_STATE;
2996 cpu_reg.state_value_clear = 0xffffff;
2997 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2998 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2999 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3000 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3001 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3002 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3003 cpu_reg.mips_view_base = 0x8000000;
3004
3005 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3006 fw = &bnx2_com_fw_09;
3007 else
3008 fw = &bnx2_com_fw_06;
3009
3010 fw->text = text;
3011 rc = load_cpu_fw(bp, &cpu_reg, fw);
3012 if (rc)
3013 goto init_cpu_err;
3014
3015 /* Initialize the Command Processor. */
3016 cpu_reg.mode = BNX2_CP_CPU_MODE;
3017 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3018 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3019 cpu_reg.state = BNX2_CP_CPU_STATE;
3020 cpu_reg.state_value_clear = 0xffffff;
3021 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3022 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3023 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3024 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3025 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3026 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3027 cpu_reg.mips_view_base = 0x8000000;
3028
3029 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3030 fw = &bnx2_cp_fw_09;
3031
3032 fw->text = text;
3033 rc = load_cpu_fw(bp, &cpu_reg, fw);
3034 if (rc)
3035 goto init_cpu_err;
3036 }
3037 init_cpu_err:
3038 vfree(text);
3039 return rc;
3040 }
3041
3042 static int
3043 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3044 {
3045 u16 pmcsr;
3046
3047 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3048
3049 switch (state) {
3050 case PCI_D0: {
3051 u32 val;
3052
3053 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3054 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3055 PCI_PM_CTRL_PME_STATUS);
3056
3057 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3058 /* delay required during transition out of D3hot */
3059 msleep(20);
3060
3061 val = REG_RD(bp, BNX2_EMAC_MODE);
3062 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3063 val &= ~BNX2_EMAC_MODE_MPKT;
3064 REG_WR(bp, BNX2_EMAC_MODE, val);
3065
3066 val = REG_RD(bp, BNX2_RPM_CONFIG);
3067 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3068 REG_WR(bp, BNX2_RPM_CONFIG, val);
3069 break;
3070 }
3071 case PCI_D3hot: {
3072 int i;
3073 u32 val, wol_msg;
3074
3075 if (bp->wol) {
3076 u32 advertising;
3077 u8 autoneg;
3078
3079 autoneg = bp->autoneg;
3080 advertising = bp->advertising;
3081
3082 bp->autoneg = AUTONEG_SPEED;
3083 bp->advertising = ADVERTISED_10baseT_Half |
3084 ADVERTISED_10baseT_Full |
3085 ADVERTISED_100baseT_Half |
3086 ADVERTISED_100baseT_Full |
3087 ADVERTISED_Autoneg;
3088
3089 bnx2_setup_copper_phy(bp);
3090
3091 bp->autoneg = autoneg;
3092 bp->advertising = advertising;
3093
3094 bnx2_set_mac_addr(bp);
3095
3096 val = REG_RD(bp, BNX2_EMAC_MODE);
3097
3098 /* Enable port mode. */
3099 val &= ~BNX2_EMAC_MODE_PORT;
3100 val |= BNX2_EMAC_MODE_PORT_MII |
3101 BNX2_EMAC_MODE_MPKT_RCVD |
3102 BNX2_EMAC_MODE_ACPI_RCVD |
3103 BNX2_EMAC_MODE_MPKT;
3104
3105 REG_WR(bp, BNX2_EMAC_MODE, val);
3106
3107 /* receive all multicast */
3108 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3109 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3110 0xffffffff);
3111 }
3112 REG_WR(bp, BNX2_EMAC_RX_MODE,
3113 BNX2_EMAC_RX_MODE_SORT_MODE);
3114
3115 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3116 BNX2_RPM_SORT_USER0_MC_EN;
3117 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3118 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3119 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3120 BNX2_RPM_SORT_USER0_ENA);
3121
3122 /* Need to enable EMAC and RPM for WOL. */
3123 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3124 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3125 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3126 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3127
3128 val = REG_RD(bp, BNX2_RPM_CONFIG);
3129 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3130 REG_WR(bp, BNX2_RPM_CONFIG, val);
3131
3132 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3133 }
3134 else {
3135 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3136 }
3137
3138 if (!(bp->flags & NO_WOL_FLAG))
3139 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3140
3141 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3142 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3143 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3144
3145 if (bp->wol)
3146 pmcsr |= 3;
3147 }
3148 else {
3149 pmcsr |= 3;
3150 }
3151 if (bp->wol) {
3152 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3153 }
3154 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3155 pmcsr);
3156
3157 /* No more memory access after this point until
3158 * device is brought back to D0.
3159 */
3160 udelay(50);
3161 break;
3162 }
3163 default:
3164 return -EINVAL;
3165 }
3166 return 0;
3167 }
3168
3169 static int
3170 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3171 {
3172 u32 val;
3173 int j;
3174
3175 /* Request access to the flash interface. */
3176 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3177 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3178 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3179 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3180 break;
3181
3182 udelay(5);
3183 }
3184
3185 if (j >= NVRAM_TIMEOUT_COUNT)
3186 return -EBUSY;
3187
3188 return 0;
3189 }
3190
3191 static int
3192 bnx2_release_nvram_lock(struct bnx2 *bp)
3193 {
3194 int j;
3195 u32 val;
3196
3197 /* Relinquish nvram interface. */
3198 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3199
3200 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3201 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3202 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3203 break;
3204
3205 udelay(5);
3206 }
3207
3208 if (j >= NVRAM_TIMEOUT_COUNT)
3209 return -EBUSY;
3210
3211 return 0;
3212 }
3213
3214
3215 static int
3216 bnx2_enable_nvram_write(struct bnx2 *bp)
3217 {
3218 u32 val;
3219
3220 val = REG_RD(bp, BNX2_MISC_CFG);
3221 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3222
3223 if (bp->flash_info->flags & BNX2_NV_WREN) {
3224 int j;
3225
3226 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3227 REG_WR(bp, BNX2_NVM_COMMAND,
3228 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3229
3230 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3231 udelay(5);
3232
3233 val = REG_RD(bp, BNX2_NVM_COMMAND);
3234 if (val & BNX2_NVM_COMMAND_DONE)
3235 break;
3236 }
3237
3238 if (j >= NVRAM_TIMEOUT_COUNT)
3239 return -EBUSY;
3240 }
3241 return 0;
3242 }
3243
3244 static void
3245 bnx2_disable_nvram_write(struct bnx2 *bp)
3246 {
3247 u32 val;
3248
3249 val = REG_RD(bp, BNX2_MISC_CFG);
3250 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3251 }
3252
3253
3254 static void
3255 bnx2_enable_nvram_access(struct bnx2 *bp)
3256 {
3257 u32 val;
3258
3259 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3260 /* Enable both bits, even on read. */
3261 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3262 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3263 }
3264
3265 static void
3266 bnx2_disable_nvram_access(struct bnx2 *bp)
3267 {
3268 u32 val;
3269
3270 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3271 /* Disable both bits, even after read. */
3272 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3273 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3274 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3275 }
3276
3277 static int
3278 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3279 {
3280 u32 cmd;
3281 int j;
3282
3283 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3284 /* Buffered flash, no erase needed */
3285 return 0;
3286
3287 /* Build an erase command */
3288 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3289 BNX2_NVM_COMMAND_DOIT;
3290
3291 /* Need to clear DONE bit separately. */
3292 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3293
3294 /* Address of the NVRAM to read from. */
3295 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3296
3297 /* Issue an erase command. */
3298 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3299
3300 /* Wait for completion. */
3301 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3302 u32 val;
3303
3304 udelay(5);
3305
3306 val = REG_RD(bp, BNX2_NVM_COMMAND);
3307 if (val & BNX2_NVM_COMMAND_DONE)
3308 break;
3309 }
3310
3311 if (j >= NVRAM_TIMEOUT_COUNT)
3312 return -EBUSY;
3313
3314 return 0;
3315 }
3316
3317 static int
3318 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3319 {
3320 u32 cmd;
3321 int j;
3322
3323 /* Build the command word. */
3324 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3325
3326 /* Calculate an offset of a buffered flash, not needed for 5709. */
3327 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3328 offset = ((offset / bp->flash_info->page_size) <<
3329 bp->flash_info->page_bits) +
3330 (offset % bp->flash_info->page_size);
3331 }
3332
3333 /* Need to clear DONE bit separately. */
3334 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3335
3336 /* Address of the NVRAM to read from. */
3337 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3338
3339 /* Issue a read command. */
3340 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3341
3342 /* Wait for completion. */
3343 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3344 u32 val;
3345
3346 udelay(5);
3347
3348 val = REG_RD(bp, BNX2_NVM_COMMAND);
3349 if (val & BNX2_NVM_COMMAND_DONE) {
3350 val = REG_RD(bp, BNX2_NVM_READ);
3351
3352 val = be32_to_cpu(val);
3353 memcpy(ret_val, &val, 4);
3354 break;
3355 }
3356 }
3357 if (j >= NVRAM_TIMEOUT_COUNT)
3358 return -EBUSY;
3359
3360 return 0;
3361 }
3362
3363
3364 static int
3365 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3366 {
3367 u32 cmd, val32;
3368 int j;
3369
3370 /* Build the command word. */
3371 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3372
3373 /* Calculate an offset of a buffered flash, not needed for 5709. */
3374 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3375 offset = ((offset / bp->flash_info->page_size) <<
3376 bp->flash_info->page_bits) +
3377 (offset % bp->flash_info->page_size);
3378 }
3379
3380 /* Need to clear DONE bit separately. */
3381 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3382
3383 memcpy(&val32, val, 4);
3384 val32 = cpu_to_be32(val32);
3385
3386 /* Write the data. */
3387 REG_WR(bp, BNX2_NVM_WRITE, val32);
3388
3389 /* Address of the NVRAM to write to. */
3390 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3391
3392 /* Issue the write command. */
3393 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3394
3395 /* Wait for completion. */
3396 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3397 udelay(5);
3398
3399 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3400 break;
3401 }
3402 if (j >= NVRAM_TIMEOUT_COUNT)
3403 return -EBUSY;
3404
3405 return 0;
3406 }
3407
3408 static int
3409 bnx2_init_nvram(struct bnx2 *bp)
3410 {
3411 u32 val;
3412 int j, entry_count, rc = 0;
3413 struct flash_spec *flash;
3414
3415 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3416 bp->flash_info = &flash_5709;
3417 goto get_flash_size;
3418 }
3419
3420 /* Determine the selected interface. */
3421 val = REG_RD(bp, BNX2_NVM_CFG1);
3422
3423 entry_count = ARRAY_SIZE(flash_table);
3424
3425 if (val & 0x40000000) {
3426
3427 /* Flash interface has been reconfigured */
3428 for (j = 0, flash = &flash_table[0]; j < entry_count;
3429 j++, flash++) {
3430 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3431 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3432 bp->flash_info = flash;
3433 break;
3434 }
3435 }
3436 }
3437 else {
3438 u32 mask;
3439 /* Not yet been reconfigured */
3440
3441 if (val & (1 << 23))
3442 mask = FLASH_BACKUP_STRAP_MASK;
3443 else
3444 mask = FLASH_STRAP_MASK;
3445
3446 for (j = 0, flash = &flash_table[0]; j < entry_count;
3447 j++, flash++) {
3448
3449 if ((val & mask) == (flash->strapping & mask)) {
3450 bp->flash_info = flash;
3451
3452 /* Request access to the flash interface. */
3453 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3454 return rc;
3455
3456 /* Enable access to flash interface */
3457 bnx2_enable_nvram_access(bp);
3458
3459 /* Reconfigure the flash interface */
3460 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3461 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3462 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3463 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3464
3465 /* Disable access to flash interface */
3466 bnx2_disable_nvram_access(bp);
3467 bnx2_release_nvram_lock(bp);
3468
3469 break;
3470 }
3471 }
3472 } /* if (val & 0x40000000) */
3473
3474 if (j == entry_count) {
3475 bp->flash_info = NULL;
3476 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3477 return -ENODEV;
3478 }
3479
3480 get_flash_size:
3481 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3482 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3483 if (val)
3484 bp->flash_size = val;
3485 else
3486 bp->flash_size = bp->flash_info->total_size;
3487
3488 return rc;
3489 }
3490
3491 static int
3492 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3493 int buf_size)
3494 {
3495 int rc = 0;
3496 u32 cmd_flags, offset32, len32, extra;
3497
3498 if (buf_size == 0)
3499 return 0;
3500
3501 /* Request access to the flash interface. */
3502 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3503 return rc;
3504
3505 /* Enable access to flash interface */
3506 bnx2_enable_nvram_access(bp);
3507
3508 len32 = buf_size;
3509 offset32 = offset;
3510 extra = 0;
3511
3512 cmd_flags = 0;
3513
3514 if (offset32 & 3) {
3515 u8 buf[4];
3516 u32 pre_len;
3517
3518 offset32 &= ~3;
3519 pre_len = 4 - (offset & 3);
3520
3521 if (pre_len >= len32) {
3522 pre_len = len32;
3523 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3524 BNX2_NVM_COMMAND_LAST;
3525 }
3526 else {
3527 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3528 }
3529
3530 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3531
3532 if (rc)
3533 return rc;
3534
3535 memcpy(ret_buf, buf + (offset & 3), pre_len);
3536
3537 offset32 += 4;
3538 ret_buf += pre_len;
3539 len32 -= pre_len;
3540 }
3541 if (len32 & 3) {
3542 extra = 4 - (len32 & 3);
3543 len32 = (len32 + 4) & ~3;
3544 }
3545
3546 if (len32 == 4) {
3547 u8 buf[4];
3548
3549 if (cmd_flags)
3550 cmd_flags = BNX2_NVM_COMMAND_LAST;
3551 else
3552 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3553 BNX2_NVM_COMMAND_LAST;
3554
3555 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3556
3557 memcpy(ret_buf, buf, 4 - extra);
3558 }
3559 else if (len32 > 0) {
3560 u8 buf[4];
3561
3562 /* Read the first word. */
3563 if (cmd_flags)
3564 cmd_flags = 0;
3565 else
3566 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3567
3568 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3569
3570 /* Advance to the next dword. */
3571 offset32 += 4;
3572 ret_buf += 4;
3573 len32 -= 4;
3574
3575 while (len32 > 4 && rc == 0) {
3576 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3577
3578 /* Advance to the next dword. */
3579 offset32 += 4;
3580 ret_buf += 4;
3581 len32 -= 4;
3582 }
3583
3584 if (rc)
3585 return rc;
3586
3587 cmd_flags = BNX2_NVM_COMMAND_LAST;
3588 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3589
3590 memcpy(ret_buf, buf, 4 - extra);
3591 }
3592
3593 /* Disable access to flash interface */
3594 bnx2_disable_nvram_access(bp);
3595
3596 bnx2_release_nvram_lock(bp);
3597
3598 return rc;
3599 }
3600
3601 static int
3602 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3603 int buf_size)
3604 {
3605 u32 written, offset32, len32;
3606 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3607 int rc = 0;
3608 int align_start, align_end;
3609
3610 buf = data_buf;
3611 offset32 = offset;
3612 len32 = buf_size;
3613 align_start = align_end = 0;
3614
3615 if ((align_start = (offset32 & 3))) {
3616 offset32 &= ~3;
3617 len32 += align_start;
3618 if (len32 < 4)
3619 len32 = 4;
3620 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3621 return rc;
3622 }
3623
3624 if (len32 & 3) {
3625 align_end = 4 - (len32 & 3);
3626 len32 += align_end;
3627 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3628 return rc;
3629 }
3630
3631 if (align_start || align_end) {
3632 align_buf = kmalloc(len32, GFP_KERNEL);
3633 if (align_buf == NULL)
3634 return -ENOMEM;
3635 if (align_start) {
3636 memcpy(align_buf, start, 4);
3637 }
3638 if (align_end) {
3639 memcpy(align_buf + len32 - 4, end, 4);
3640 }
3641 memcpy(align_buf + align_start, data_buf, buf_size);
3642 buf = align_buf;
3643 }
3644
3645 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3646 flash_buffer = kmalloc(264, GFP_KERNEL);
3647 if (flash_buffer == NULL) {
3648 rc = -ENOMEM;
3649 goto nvram_write_end;
3650 }
3651 }
3652
3653 written = 0;
3654 while ((written < len32) && (rc == 0)) {
3655 u32 page_start, page_end, data_start, data_end;
3656 u32 addr, cmd_flags;
3657 int i;
3658
3659 /* Find the page_start addr */
3660 page_start = offset32 + written;
3661 page_start -= (page_start % bp->flash_info->page_size);
3662 /* Find the page_end addr */
3663 page_end = page_start + bp->flash_info->page_size;
3664 /* Find the data_start addr */
3665 data_start = (written == 0) ? offset32 : page_start;
3666 /* Find the data_end addr */
3667 data_end = (page_end > offset32 + len32) ?
3668 (offset32 + len32) : page_end;
3669
3670 /* Request access to the flash interface. */
3671 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3672 goto nvram_write_end;
3673
3674 /* Enable access to flash interface */
3675 bnx2_enable_nvram_access(bp);
3676
3677 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3678 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3679 int j;
3680
3681 /* Read the whole page into the buffer
3682 * (non-buffer flash only) */
3683 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3684 if (j == (bp->flash_info->page_size - 4)) {
3685 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3686 }
3687 rc = bnx2_nvram_read_dword(bp,
3688 page_start + j,
3689 &flash_buffer[j],
3690 cmd_flags);
3691
3692 if (rc)
3693 goto nvram_write_end;
3694
3695 cmd_flags = 0;
3696 }
3697 }
3698
3699 /* Enable writes to flash interface (unlock write-protect) */
3700 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3701 goto nvram_write_end;
3702
3703 /* Loop to write back the buffer data from page_start to
3704 * data_start */
3705 i = 0;
3706 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3707 /* Erase the page */
3708 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3709 goto nvram_write_end;
3710
3711 /* Re-enable the write again for the actual write */
3712 bnx2_enable_nvram_write(bp);
3713
3714 for (addr = page_start; addr < data_start;
3715 addr += 4, i += 4) {
3716
3717 rc = bnx2_nvram_write_dword(bp, addr,
3718 &flash_buffer[i], cmd_flags);
3719
3720 if (rc != 0)
3721 goto nvram_write_end;
3722
3723 cmd_flags = 0;
3724 }
3725 }
3726
3727 /* Loop to write the new data from data_start to data_end */
3728 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3729 if ((addr == page_end - 4) ||
3730 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
3731 (addr == data_end - 4))) {
3732
3733 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3734 }
3735 rc = bnx2_nvram_write_dword(bp, addr, buf,
3736 cmd_flags);
3737
3738 if (rc != 0)
3739 goto nvram_write_end;
3740
3741 cmd_flags = 0;
3742 buf += 4;
3743 }
3744
3745 /* Loop to write back the buffer data from data_end
3746 * to page_end */
3747 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3748 for (addr = data_end; addr < page_end;
3749 addr += 4, i += 4) {
3750
3751 if (addr == page_end-4) {
3752 cmd_flags = BNX2_NVM_COMMAND_LAST;
3753 }
3754 rc = bnx2_nvram_write_dword(bp, addr,
3755 &flash_buffer[i], cmd_flags);
3756
3757 if (rc != 0)
3758 goto nvram_write_end;
3759
3760 cmd_flags = 0;
3761 }
3762 }
3763
3764 /* Disable writes to flash interface (lock write-protect) */
3765 bnx2_disable_nvram_write(bp);
3766
3767 /* Disable access to flash interface */
3768 bnx2_disable_nvram_access(bp);
3769 bnx2_release_nvram_lock(bp);
3770
3771 /* Increment written */
3772 written += data_end - data_start;
3773 }
3774
3775 nvram_write_end:
3776 kfree(flash_buffer);
3777 kfree(align_buf);
3778 return rc;
3779 }
3780
3781 static void
3782 bnx2_init_remote_phy(struct bnx2 *bp)
3783 {
3784 u32 val;
3785
3786 bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
3787 if (!(bp->phy_flags & PHY_SERDES_FLAG))
3788 return;
3789
3790 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
3791 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
3792 return;
3793
3794 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
3795 bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
3796
3797 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
3798 if (val & BNX2_LINK_STATUS_SERDES_LINK)
3799 bp->phy_port = PORT_FIBRE;
3800 else
3801 bp->phy_port = PORT_TP;
3802
3803 if (netif_running(bp->dev)) {
3804 u32 sig;
3805
3806 if (val & BNX2_LINK_STATUS_LINK_UP) {
3807 bp->link_up = 1;
3808 netif_carrier_on(bp->dev);
3809 } else {
3810 bp->link_up = 0;
3811 netif_carrier_off(bp->dev);
3812 }
3813 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
3814 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
3815 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
3816 sig);
3817 }
3818 }
3819 }
3820
3821 static int
3822 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3823 {
3824 u32 val;
3825 int i, rc = 0;
3826 u8 old_port;
3827
3828 /* Wait for the current PCI transaction to complete before
3829 * issuing a reset. */
3830 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3831 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3832 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3833 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3834 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3835 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3836 udelay(5);
3837
3838 /* Wait for the firmware to tell us it is ok to issue a reset. */
3839 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3840
3841 /* Deposit a driver reset signature so the firmware knows that
3842 * this is a soft reset. */
3843 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3844 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3845
3846 /* Do a dummy read to force the chip to complete all current transaction
3847 * before we issue a reset. */
3848 val = REG_RD(bp, BNX2_MISC_ID);
3849
3850 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3851 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3852 REG_RD(bp, BNX2_MISC_COMMAND);
3853 udelay(5);
3854
3855 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3856 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3857
3858 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3859
3860 } else {
3861 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3862 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3863 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3864
3865 /* Chip reset. */
3866 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3867
3868 /* Reading back any register after chip reset will hang the
3869 * bus on 5706 A0 and A1. The msleep below provides plenty
3870 * of margin for write posting.
3871 */
3872 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3873 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3874 msleep(20);
3875
3876 /* Reset takes approximate 30 usec */
3877 for (i = 0; i < 10; i++) {
3878 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3879 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3880 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3881 break;
3882 udelay(10);
3883 }
3884
3885 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3886 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3887 printk(KERN_ERR PFX "Chip reset did not complete\n");
3888 return -EBUSY;
3889 }
3890 }
3891
3892 /* Make sure byte swapping is properly configured. */
3893 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3894 if (val != 0x01020304) {
3895 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3896 return -ENODEV;
3897 }
3898
3899 /* Wait for the firmware to finish its initialization. */
3900 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3901 if (rc)
3902 return rc;
3903
3904 spin_lock_bh(&bp->phy_lock);
3905 old_port = bp->phy_port;
3906 bnx2_init_remote_phy(bp);
3907 if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port)
3908 bnx2_set_default_remote_link(bp);
3909 spin_unlock_bh(&bp->phy_lock);
3910
3911 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3912 /* Adjust the voltage regular to two steps lower. The default
3913 * of this register is 0x0000000e. */
3914 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3915
3916 /* Remove bad rbuf memory from the free pool. */
3917 rc = bnx2_alloc_bad_rbuf(bp);
3918 }
3919
3920 return rc;
3921 }
3922
3923 static int
3924 bnx2_init_chip(struct bnx2 *bp)
3925 {
3926 u32 val;
3927 int rc;
3928
3929 /* Make sure the interrupt is not active. */
3930 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3931
3932 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3933 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3934 #ifdef __BIG_ENDIAN
3935 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3936 #endif
3937 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3938 DMA_READ_CHANS << 12 |
3939 DMA_WRITE_CHANS << 16;
3940
3941 val |= (0x2 << 20) | (1 << 11);
3942
3943 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3944 val |= (1 << 23);
3945
3946 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3947 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3948 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3949
3950 REG_WR(bp, BNX2_DMA_CONFIG, val);
3951
3952 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3953 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3954 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3955 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3956 }
3957
3958 if (bp->flags & PCIX_FLAG) {
3959 u16 val16;
3960
3961 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3962 &val16);
3963 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3964 val16 & ~PCI_X_CMD_ERO);
3965 }
3966
3967 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3968 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3969 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3970 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3971
3972 /* Initialize context mapping and zero out the quick contexts. The
3973 * context block must have already been enabled. */
3974 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3975 rc = bnx2_init_5709_context(bp);
3976 if (rc)
3977 return rc;
3978 } else
3979 bnx2_init_context(bp);
3980
3981 if ((rc = bnx2_init_cpus(bp)) != 0)
3982 return rc;
3983
3984 bnx2_init_nvram(bp);
3985
3986 bnx2_set_mac_addr(bp);
3987
3988 val = REG_RD(bp, BNX2_MQ_CONFIG);
3989 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3990 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3991 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
3992 val |= BNX2_MQ_CONFIG_HALT_DIS;
3993
3994 REG_WR(bp, BNX2_MQ_CONFIG, val);
3995
3996 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3997 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3998 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3999
4000 val = (BCM_PAGE_BITS - 8) << 24;
4001 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4002
4003 /* Configure page size. */
4004 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4005 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4006 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4007 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4008
4009 val = bp->mac_addr[0] +
4010 (bp->mac_addr[1] << 8) +
4011 (bp->mac_addr[2] << 16) +
4012 bp->mac_addr[3] +
4013 (bp->mac_addr[4] << 8) +
4014 (bp->mac_addr[5] << 16);
4015 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4016
4017 /* Program the MTU. Also include 4 bytes for CRC32. */
4018 val = bp->dev->mtu + ETH_HLEN + 4;
4019 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4020 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4021 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4022
4023 bp->last_status_idx = 0;
4024 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4025
4026 /* Set up how to generate a link change interrupt. */
4027 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4028
4029 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4030 (u64) bp->status_blk_mapping & 0xffffffff);
4031 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4032
4033 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4034 (u64) bp->stats_blk_mapping & 0xffffffff);
4035 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4036 (u64) bp->stats_blk_mapping >> 32);
4037
4038 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4039 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4040
4041 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4042 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4043
4044 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4045 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4046
4047 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4048
4049 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4050
4051 REG_WR(bp, BNX2_HC_COM_TICKS,
4052 (bp->com_ticks_int << 16) | bp->com_ticks);
4053
4054 REG_WR(bp, BNX2_HC_CMD_TICKS,
4055 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4056
4057 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4058 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4059 else
4060 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4061 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4062
4063 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4064 val = BNX2_HC_CONFIG_COLLECT_STATS;
4065 else {
4066 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4067 BNX2_HC_CONFIG_COLLECT_STATS;
4068 }
4069
4070 if (bp->flags & ONE_SHOT_MSI_FLAG)
4071 val |= BNX2_HC_CONFIG_ONE_SHOT;
4072
4073 REG_WR(bp, BNX2_HC_CONFIG, val);
4074
4075 /* Clear internal stats counters. */
4076 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4077
4078 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4079
4080 /* Initialize the receive filter. */
4081 bnx2_set_rx_mode(bp->dev);
4082
4083 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4084 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4085 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4086 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4087 }
4088 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4089 0);
4090
4091 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4092 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4093
4094 udelay(20);
4095
4096 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4097
4098 return rc;
4099 }
4100
4101 static void
4102 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4103 {
4104 u32 val, offset0, offset1, offset2, offset3;
4105
4106 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4107 offset0 = BNX2_L2CTX_TYPE_XI;
4108 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4109 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4110 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4111 } else {
4112 offset0 = BNX2_L2CTX_TYPE;
4113 offset1 = BNX2_L2CTX_CMD_TYPE;
4114 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4115 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4116 }
4117 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4118 CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
4119
4120 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4121 CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
4122
4123 val = (u64) bp->tx_desc_mapping >> 32;
4124 CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
4125
4126 val = (u64) bp->tx_desc_mapping & 0xffffffff;
4127 CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
4128 }
4129
4130 static void
4131 bnx2_init_tx_ring(struct bnx2 *bp)
4132 {
4133 struct tx_bd *txbd;
4134 u32 cid;
4135
4136 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4137
4138 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4139
4140 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4141 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4142
4143 bp->tx_prod = 0;
4144 bp->tx_cons = 0;
4145 bp->hw_tx_cons = 0;
4146 bp->tx_prod_bseq = 0;
4147
4148 cid = TX_CID;
4149 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4150 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4151
4152 bnx2_init_tx_context(bp, cid);
4153 }
4154
4155 static void
4156 bnx2_init_rx_ring(struct bnx2 *bp)
4157 {
4158 struct rx_bd *rxbd;
4159 int i;
4160 u16 prod, ring_prod;
4161 u32 val;
4162
4163 /* 8 for CRC and VLAN */
4164 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4165 /* hw alignment */
4166 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4167
4168 ring_prod = prod = bp->rx_prod = 0;
4169 bp->rx_cons = 0;
4170 bp->hw_rx_cons = 0;
4171 bp->rx_prod_bseq = 0;
4172
4173 for (i = 0; i < bp->rx_max_ring; i++) {
4174 int j;
4175
4176 rxbd = &bp->rx_desc_ring[i][0];
4177 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4178 rxbd->rx_bd_len = bp->rx_buf_use_size;
4179 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4180 }
4181 if (i == (bp->rx_max_ring - 1))
4182 j = 0;
4183 else
4184 j = i + 1;
4185 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
4186 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
4187 0xffffffff;
4188 }
4189
4190 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4191 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
4192 val |= 0x02 << 8;
4193 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
4194
4195 val = (u64) bp->rx_desc_mapping[0] >> 32;
4196 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
4197
4198 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4199 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
4200
4201 for (i = 0; i < bp->rx_ring_size; i++) {
4202 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
4203 break;
4204 }
4205 prod = NEXT_RX_BD(prod);
4206 ring_prod = RX_RING_IDX(prod);
4207 }
4208 bp->rx_prod = prod;
4209
4210 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4211
4212 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
4213 }
4214
4215 static void
4216 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4217 {
4218 u32 num_rings, max;
4219
4220 bp->rx_ring_size = size;
4221 num_rings = 1;
4222 while (size > MAX_RX_DESC_CNT) {
4223 size -= MAX_RX_DESC_CNT;
4224 num_rings++;
4225 }
4226 /* round to next power of 2 */
4227 max = MAX_RX_RINGS;
4228 while ((max & num_rings) == 0)
4229 max >>= 1;
4230
4231 if (num_rings != max)
4232 max <<= 1;
4233
4234 bp->rx_max_ring = max;
4235 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4236 }
4237
4238 static void
4239 bnx2_free_tx_skbs(struct bnx2 *bp)
4240 {
4241 int i;
4242
4243 if (bp->tx_buf_ring == NULL)
4244 return;
4245
4246 for (i = 0; i < TX_DESC_CNT; ) {
4247 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4248 struct sk_buff *skb = tx_buf->skb;
4249 int j, last;
4250
4251 if (skb == NULL) {
4252 i++;
4253 continue;
4254 }
4255
4256 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4257 skb_headlen(skb), PCI_DMA_TODEVICE);
4258
4259 tx_buf->skb = NULL;
4260
4261 last = skb_shinfo(skb)->nr_frags;
4262 for (j = 0; j < last; j++) {
4263 tx_buf = &bp->tx_buf_ring[i + j + 1];
4264 pci_unmap_page(bp->pdev,
4265 pci_unmap_addr(tx_buf, mapping),
4266 skb_shinfo(skb)->frags[j].size,
4267 PCI_DMA_TODEVICE);
4268 }
4269 dev_kfree_skb(skb);
4270 i += j + 1;
4271 }
4272
4273 }
4274
4275 static void
4276 bnx2_free_rx_skbs(struct bnx2 *bp)
4277 {
4278 int i;
4279
4280 if (bp->rx_buf_ring == NULL)
4281 return;
4282
4283 for (i = 0; i < bp->rx_max_ring_idx; i++) {
4284 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4285 struct sk_buff *skb = rx_buf->skb;
4286
4287 if (skb == NULL)
4288 continue;
4289
4290 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4291 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4292
4293 rx_buf->skb = NULL;
4294
4295 dev_kfree_skb(skb);
4296 }
4297 }
4298
4299 static void
4300 bnx2_free_skbs(struct bnx2 *bp)
4301 {
4302 bnx2_free_tx_skbs(bp);
4303 bnx2_free_rx_skbs(bp);
4304 }
4305
4306 static int
4307 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4308 {
4309 int rc;
4310
4311 rc = bnx2_reset_chip(bp, reset_code);
4312 bnx2_free_skbs(bp);
4313 if (rc)
4314 return rc;
4315
4316 if ((rc = bnx2_init_chip(bp)) != 0)
4317 return rc;
4318
4319 bnx2_init_tx_ring(bp);
4320 bnx2_init_rx_ring(bp);
4321 return 0;
4322 }
4323
4324 static int
4325 bnx2_init_nic(struct bnx2 *bp)
4326 {
4327 int rc;
4328
4329 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4330 return rc;
4331
4332 spin_lock_bh(&bp->phy_lock);
4333 bnx2_init_phy(bp);
4334 bnx2_set_link(bp);
4335 spin_unlock_bh(&bp->phy_lock);
4336 return 0;
4337 }
4338
4339 static int
4340 bnx2_test_registers(struct bnx2 *bp)
4341 {
4342 int ret;
4343 int i, is_5709;
4344 static const struct {
4345 u16 offset;
4346 u16 flags;
4347 #define BNX2_FL_NOT_5709 1
4348 u32 rw_mask;
4349 u32 ro_mask;
4350 } reg_tbl[] = {
4351 { 0x006c, 0, 0x00000000, 0x0000003f },
4352 { 0x0090, 0, 0xffffffff, 0x00000000 },
4353 { 0x0094, 0, 0x00000000, 0x00000000 },
4354
4355 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4356 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4357 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4358 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4359 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4360 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4361 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4362 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4363 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4364
4365 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4366 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4367 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4368 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4369 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4370 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4371
4372 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4373 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4374 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
4375
4376 { 0x1000, 0, 0x00000000, 0x00000001 },
4377 { 0x1004, 0, 0x00000000, 0x000f0001 },
4378
4379 { 0x1408, 0, 0x01c00800, 0x00000000 },
4380 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4381 { 0x14a8, 0, 0x00000000, 0x000001ff },
4382 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4383 { 0x14b0, 0, 0x00000002, 0x00000001 },
4384 { 0x14b8, 0, 0x00000000, 0x00000000 },
4385 { 0x14c0, 0, 0x00000000, 0x00000009 },
4386 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4387 { 0x14cc, 0, 0x00000000, 0x00000001 },
4388 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4389
4390 { 0x1800, 0, 0x00000000, 0x00000001 },
4391 { 0x1804, 0, 0x00000000, 0x00000003 },
4392
4393 { 0x2800, 0, 0x00000000, 0x00000001 },
4394 { 0x2804, 0, 0x00000000, 0x00003f01 },
4395 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4396 { 0x2810, 0, 0xffff0000, 0x00000000 },
4397 { 0x2814, 0, 0xffff0000, 0x00000000 },
4398 { 0x2818, 0, 0xffff0000, 0x00000000 },
4399 { 0x281c, 0, 0xffff0000, 0x00000000 },
4400 { 0x2834, 0, 0xffffffff, 0x00000000 },
4401 { 0x2840, 0, 0x00000000, 0xffffffff },
4402 { 0x2844, 0, 0x00000000, 0xffffffff },
4403 { 0x2848, 0, 0xffffffff, 0x00000000 },
4404 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4405
4406 { 0x2c00, 0, 0x00000000, 0x00000011 },
4407 { 0x2c04, 0, 0x00000000, 0x00030007 },
4408
4409 { 0x3c00, 0, 0x00000000, 0x00000001 },
4410 { 0x3c04, 0, 0x00000000, 0x00070000 },
4411 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4412 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4413 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4414 { 0x3c14, 0, 0x00000000, 0xffffffff },
4415 { 0x3c18, 0, 0x00000000, 0xffffffff },
4416 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4417 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4418
4419 { 0x5004, 0, 0x00000000, 0x0000007f },
4420 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4421
4422 { 0x5c00, 0, 0x00000000, 0x00000001 },
4423 { 0x5c04, 0, 0x00000000, 0x0003000f },
4424 { 0x5c08, 0, 0x00000003, 0x00000000 },
4425 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4426 { 0x5c10, 0, 0x00000000, 0xffffffff },
4427 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4428 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4429 { 0x5c88, 0, 0x00000000, 0x00077373 },
4430 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4431
4432 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4433 { 0x680c, 0, 0xffffffff, 0x00000000 },
4434 { 0x6810, 0, 0xffffffff, 0x00000000 },
4435 { 0x6814, 0, 0xffffffff, 0x00000000 },
4436 { 0x6818, 0, 0xffffffff, 0x00000000 },
4437 { 0x681c, 0, 0xffffffff, 0x00000000 },
4438 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4439 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4440 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4441 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4442 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4443 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4444 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4445 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4446 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4447 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4448 { 0x684c, 0, 0xffffffff, 0x00000000 },
4449 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4450 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4451 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4452 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4453 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4454 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4455
4456 { 0xffff, 0, 0x00000000, 0x00000000 },
4457 };
4458
4459 ret = 0;
4460 is_5709 = 0;
4461 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4462 is_5709 = 1;
4463
4464 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4465 u32 offset, rw_mask, ro_mask, save_val, val;
4466 u16 flags = reg_tbl[i].flags;
4467
4468 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4469 continue;
4470
4471 offset = (u32) reg_tbl[i].offset;
4472 rw_mask = reg_tbl[i].rw_mask;
4473 ro_mask = reg_tbl[i].ro_mask;
4474
4475 save_val = readl(bp->regview + offset);
4476
4477 writel(0, bp->regview + offset);
4478
4479 val = readl(bp->regview + offset);
4480 if ((val & rw_mask) != 0) {
4481 goto reg_test_err;
4482 }
4483
4484 if ((val & ro_mask) != (save_val & ro_mask)) {
4485 goto reg_test_err;
4486 }
4487
4488 writel(0xffffffff, bp->regview + offset);
4489
4490 val = readl(bp->regview + offset);
4491 if ((val & rw_mask) != rw_mask) {
4492 goto reg_test_err;
4493 }
4494
4495 if ((val & ro_mask) != (save_val & ro_mask)) {
4496 goto reg_test_err;
4497 }
4498
4499 writel(save_val, bp->regview + offset);
4500 continue;
4501
4502 reg_test_err:
4503 writel(save_val, bp->regview + offset);
4504 ret = -ENODEV;
4505 break;
4506 }
4507 return ret;
4508 }
4509
4510 static int
4511 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
4512 {
4513 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
4514 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
4515 int i;
4516
4517 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
4518 u32 offset;
4519
4520 for (offset = 0; offset < size; offset += 4) {
4521
4522 REG_WR_IND(bp, start + offset, test_pattern[i]);
4523
4524 if (REG_RD_IND(bp, start + offset) !=
4525 test_pattern[i]) {
4526 return -ENODEV;
4527 }
4528 }
4529 }
4530 return 0;
4531 }
4532
4533 static int
4534 bnx2_test_memory(struct bnx2 *bp)
4535 {
4536 int ret = 0;
4537 int i;
4538 static struct mem_entry {
4539 u32 offset;
4540 u32 len;
4541 } mem_tbl_5706[] = {
4542 { 0x60000, 0x4000 },
4543 { 0xa0000, 0x3000 },
4544 { 0xe0000, 0x4000 },
4545 { 0x120000, 0x4000 },
4546 { 0x1a0000, 0x4000 },
4547 { 0x160000, 0x4000 },
4548 { 0xffffffff, 0 },
4549 },
4550 mem_tbl_5709[] = {
4551 { 0x60000, 0x4000 },
4552 { 0xa0000, 0x3000 },
4553 { 0xe0000, 0x4000 },
4554 { 0x120000, 0x4000 },
4555 { 0x1a0000, 0x4000 },
4556 { 0xffffffff, 0 },
4557 };
4558 struct mem_entry *mem_tbl;
4559
4560 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4561 mem_tbl = mem_tbl_5709;
4562 else
4563 mem_tbl = mem_tbl_5706;
4564
4565 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
4566 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
4567 mem_tbl[i].len)) != 0) {
4568 return ret;
4569 }
4570 }
4571
4572 return ret;
4573 }
4574
4575 #define BNX2_MAC_LOOPBACK 0
4576 #define BNX2_PHY_LOOPBACK 1
4577
4578 static int
4579 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4580 {
4581 unsigned int pkt_size, num_pkts, i;
4582 struct sk_buff *skb, *rx_skb;
4583 unsigned char *packet;
4584 u16 rx_start_idx, rx_idx;
4585 dma_addr_t map;
4586 struct tx_bd *txbd;
4587 struct sw_bd *rx_buf;
4588 struct l2_fhdr *rx_hdr;
4589 int ret = -ENODEV;
4590
4591 if (loopback_mode == BNX2_MAC_LOOPBACK) {
4592 bp->loopback = MAC_LOOPBACK;
4593 bnx2_set_mac_loopback(bp);
4594 }
4595 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
4596 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4597 return 0;
4598
4599 bp->loopback = PHY_LOOPBACK;
4600 bnx2_set_phy_loopback(bp);
4601 }
4602 else
4603 return -EINVAL;
4604
4605 pkt_size = 1514;
4606 skb = netdev_alloc_skb(bp->dev, pkt_size);
4607 if (!skb)
4608 return -ENOMEM;
4609 packet = skb_put(skb, pkt_size);
4610 memcpy(packet, bp->dev->dev_addr, 6);
4611 memset(packet + 6, 0x0, 8);
4612 for (i = 14; i < pkt_size; i++)
4613 packet[i] = (unsigned char) (i & 0xff);
4614
4615 map = pci_map_single(bp->pdev, skb->data, pkt_size,
4616 PCI_DMA_TODEVICE);
4617
4618 REG_WR(bp, BNX2_HC_COMMAND,
4619 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4620
4621 REG_RD(bp, BNX2_HC_COMMAND);
4622
4623 udelay(5);
4624 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
4625
4626 num_pkts = 0;
4627
4628 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
4629
4630 txbd->tx_bd_haddr_hi = (u64) map >> 32;
4631 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
4632 txbd->tx_bd_mss_nbytes = pkt_size;
4633 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
4634
4635 num_pkts++;
4636 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4637 bp->tx_prod_bseq += pkt_size;
4638
4639 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
4640 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4641
4642 udelay(100);
4643
4644 REG_WR(bp, BNX2_HC_COMMAND,
4645 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4646
4647 REG_RD(bp, BNX2_HC_COMMAND);
4648
4649 udelay(5);
4650
4651 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4652 dev_kfree_skb(skb);
4653
4654 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4655 goto loopback_test_done;
4656 }
4657
4658 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4659 if (rx_idx != rx_start_idx + num_pkts) {
4660 goto loopback_test_done;
4661 }
4662
4663 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4664 rx_skb = rx_buf->skb;
4665
4666 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4667 skb_reserve(rx_skb, bp->rx_offset);
4668
4669 pci_dma_sync_single_for_cpu(bp->pdev,
4670 pci_unmap_addr(rx_buf, mapping),
4671 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4672
4673 if (rx_hdr->l2_fhdr_status &
4674 (L2_FHDR_ERRORS_BAD_CRC |
4675 L2_FHDR_ERRORS_PHY_DECODE |
4676 L2_FHDR_ERRORS_ALIGNMENT |
4677 L2_FHDR_ERRORS_TOO_SHORT |
4678 L2_FHDR_ERRORS_GIANT_FRAME)) {
4679
4680 goto loopback_test_done;
4681 }
4682
4683 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4684 goto loopback_test_done;
4685 }
4686
4687 for (i = 14; i < pkt_size; i++) {
4688 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4689 goto loopback_test_done;
4690 }
4691 }
4692
4693 ret = 0;
4694
4695 loopback_test_done:
4696 bp->loopback = 0;
4697 return ret;
4698 }
4699
4700 #define BNX2_MAC_LOOPBACK_FAILED 1
4701 #define BNX2_PHY_LOOPBACK_FAILED 2
4702 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4703 BNX2_PHY_LOOPBACK_FAILED)
4704
4705 static int
4706 bnx2_test_loopback(struct bnx2 *bp)
4707 {
4708 int rc = 0;
4709
4710 if (!netif_running(bp->dev))
4711 return BNX2_LOOPBACK_FAILED;
4712
4713 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4714 spin_lock_bh(&bp->phy_lock);
4715 bnx2_init_phy(bp);
4716 spin_unlock_bh(&bp->phy_lock);
4717 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4718 rc |= BNX2_MAC_LOOPBACK_FAILED;
4719 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4720 rc |= BNX2_PHY_LOOPBACK_FAILED;
4721 return rc;
4722 }
4723
4724 #define NVRAM_SIZE 0x200
4725 #define CRC32_RESIDUAL 0xdebb20e3
4726
4727 static int
4728 bnx2_test_nvram(struct bnx2 *bp)
4729 {
4730 u32 buf[NVRAM_SIZE / 4];
4731 u8 *data = (u8 *) buf;
4732 int rc = 0;
4733 u32 magic, csum;
4734
4735 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4736 goto test_nvram_done;
4737
4738 magic = be32_to_cpu(buf[0]);
4739 if (magic != 0x669955aa) {
4740 rc = -ENODEV;
4741 goto test_nvram_done;
4742 }
4743
4744 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4745 goto test_nvram_done;
4746
4747 csum = ether_crc_le(0x100, data);
4748 if (csum != CRC32_RESIDUAL) {
4749 rc = -ENODEV;
4750 goto test_nvram_done;
4751 }
4752
4753 csum = ether_crc_le(0x100, data + 0x100);
4754 if (csum != CRC32_RESIDUAL) {
4755 rc = -ENODEV;
4756 }
4757
4758 test_nvram_done:
4759 return rc;
4760 }
4761
4762 static int
4763 bnx2_test_link(struct bnx2 *bp)
4764 {
4765 u32 bmsr;
4766
4767 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
4768 if (bp->link_up)
4769 return 0;
4770 return -ENODEV;
4771 }
4772 spin_lock_bh(&bp->phy_lock);
4773 bnx2_enable_bmsr1(bp);
4774 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4775 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4776 bnx2_disable_bmsr1(bp);
4777 spin_unlock_bh(&bp->phy_lock);
4778
4779 if (bmsr & BMSR_LSTATUS) {
4780 return 0;
4781 }
4782 return -ENODEV;
4783 }
4784
4785 static int
4786 bnx2_test_intr(struct bnx2 *bp)
4787 {
4788 int i;
4789 u16 status_idx;
4790
4791 if (!netif_running(bp->dev))
4792 return -ENODEV;
4793
4794 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4795
4796 /* This register is not touched during run-time. */
4797 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4798 REG_RD(bp, BNX2_HC_COMMAND);
4799
4800 for (i = 0; i < 10; i++) {
4801 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4802 status_idx) {
4803
4804 break;
4805 }
4806
4807 msleep_interruptible(10);
4808 }
4809 if (i < 10)
4810 return 0;
4811
4812 return -ENODEV;
4813 }
4814
4815 static void
4816 bnx2_5706_serdes_timer(struct bnx2 *bp)
4817 {
4818 spin_lock(&bp->phy_lock);
4819 if (bp->serdes_an_pending)
4820 bp->serdes_an_pending--;
4821 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4822 u32 bmcr;
4823
4824 bp->current_interval = bp->timer_interval;
4825
4826 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4827
4828 if (bmcr & BMCR_ANENABLE) {
4829 u32 phy1, phy2;
4830
4831 bnx2_write_phy(bp, 0x1c, 0x7c00);
4832 bnx2_read_phy(bp, 0x1c, &phy1);
4833
4834 bnx2_write_phy(bp, 0x17, 0x0f01);
4835 bnx2_read_phy(bp, 0x15, &phy2);
4836 bnx2_write_phy(bp, 0x17, 0x0f01);
4837 bnx2_read_phy(bp, 0x15, &phy2);
4838
4839 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4840 !(phy2 & 0x20)) { /* no CONFIG */
4841
4842 bmcr &= ~BMCR_ANENABLE;
4843 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4844 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4845 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4846 }
4847 }
4848 }
4849 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4850 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4851 u32 phy2;
4852
4853 bnx2_write_phy(bp, 0x17, 0x0f01);
4854 bnx2_read_phy(bp, 0x15, &phy2);
4855 if (phy2 & 0x20) {
4856 u32 bmcr;
4857
4858 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4859 bmcr |= BMCR_ANENABLE;
4860 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4861
4862 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4863 }
4864 } else
4865 bp->current_interval = bp->timer_interval;
4866
4867 spin_unlock(&bp->phy_lock);
4868 }
4869
4870 static void
4871 bnx2_5708_serdes_timer(struct bnx2 *bp)
4872 {
4873 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4874 return;
4875
4876 if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
4877 bp->serdes_an_pending = 0;
4878 return;
4879 }
4880
4881 spin_lock(&bp->phy_lock);
4882 if (bp->serdes_an_pending)
4883 bp->serdes_an_pending--;
4884 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4885 u32 bmcr;
4886
4887 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4888 if (bmcr & BMCR_ANENABLE) {
4889 bnx2_enable_forced_2g5(bp);
4890 bp->current_interval = SERDES_FORCED_TIMEOUT;
4891 } else {
4892 bnx2_disable_forced_2g5(bp);
4893 bp->serdes_an_pending = 2;
4894 bp->current_interval = bp->timer_interval;
4895 }
4896
4897 } else
4898 bp->current_interval = bp->timer_interval;
4899
4900 spin_unlock(&bp->phy_lock);
4901 }
4902
4903 static void
4904 bnx2_timer(unsigned long data)
4905 {
4906 struct bnx2 *bp = (struct bnx2 *) data;
4907
4908 if (!netif_running(bp->dev))
4909 return;
4910
4911 if (atomic_read(&bp->intr_sem) != 0)
4912 goto bnx2_restart_timer;
4913
4914 bnx2_send_heart_beat(bp);
4915
4916 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4917
4918 /* workaround occasional corrupted counters */
4919 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
4920 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
4921 BNX2_HC_COMMAND_STATS_NOW);
4922
4923 if (bp->phy_flags & PHY_SERDES_FLAG) {
4924 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4925 bnx2_5706_serdes_timer(bp);
4926 else
4927 bnx2_5708_serdes_timer(bp);
4928 }
4929
4930 bnx2_restart_timer:
4931 mod_timer(&bp->timer, jiffies + bp->current_interval);
4932 }
4933
4934 static int
4935 bnx2_request_irq(struct bnx2 *bp)
4936 {
4937 struct net_device *dev = bp->dev;
4938 int rc = 0;
4939
4940 if (bp->flags & USING_MSI_FLAG) {
4941 irq_handler_t fn = bnx2_msi;
4942
4943 if (bp->flags & ONE_SHOT_MSI_FLAG)
4944 fn = bnx2_msi_1shot;
4945
4946 rc = request_irq(bp->pdev->irq, fn, 0, dev->name, dev);
4947 } else
4948 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4949 IRQF_SHARED, dev->name, dev);
4950 return rc;
4951 }
4952
4953 static void
4954 bnx2_free_irq(struct bnx2 *bp)
4955 {
4956 struct net_device *dev = bp->dev;
4957
4958 if (bp->flags & USING_MSI_FLAG) {
4959 free_irq(bp->pdev->irq, dev);
4960 pci_disable_msi(bp->pdev);
4961 bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG);
4962 } else
4963 free_irq(bp->pdev->irq, dev);
4964 }
4965
4966 /* Called with rtnl_lock */
4967 static int
4968 bnx2_open(struct net_device *dev)
4969 {
4970 struct bnx2 *bp = netdev_priv(dev);
4971 int rc;
4972
4973 netif_carrier_off(dev);
4974
4975 bnx2_set_power_state(bp, PCI_D0);
4976 bnx2_disable_int(bp);
4977
4978 rc = bnx2_alloc_mem(bp);
4979 if (rc)
4980 return rc;
4981
4982 napi_enable(&bp->napi);
4983
4984 if ((bp->flags & MSI_CAP_FLAG) && !disable_msi) {
4985 if (pci_enable_msi(bp->pdev) == 0) {
4986 bp->flags |= USING_MSI_FLAG;
4987 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4988 bp->flags |= ONE_SHOT_MSI_FLAG;
4989 }
4990 }
4991 rc = bnx2_request_irq(bp);
4992
4993 if (rc) {
4994 napi_disable(&bp->napi);
4995 bnx2_free_mem(bp);
4996 return rc;
4997 }
4998
4999 rc = bnx2_init_nic(bp);
5000
5001 if (rc) {
5002 napi_disable(&bp->napi);
5003 bnx2_free_irq(bp);
5004 bnx2_free_skbs(bp);
5005 bnx2_free_mem(bp);
5006 return rc;
5007 }
5008
5009 mod_timer(&bp->timer, jiffies + bp->current_interval);
5010
5011 atomic_set(&bp->intr_sem, 0);
5012
5013 bnx2_enable_int(bp);
5014
5015 if (bp->flags & USING_MSI_FLAG) {
5016 /* Test MSI to make sure it is working
5017 * If MSI test fails, go back to INTx mode
5018 */
5019 if (bnx2_test_intr(bp) != 0) {
5020 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5021 " using MSI, switching to INTx mode. Please"
5022 " report this failure to the PCI maintainer"
5023 " and include system chipset information.\n",
5024 bp->dev->name);
5025
5026 bnx2_disable_int(bp);
5027 bnx2_free_irq(bp);
5028
5029 rc = bnx2_init_nic(bp);
5030
5031 if (!rc)
5032 rc = bnx2_request_irq(bp);
5033
5034 if (rc) {
5035 napi_disable(&bp->napi);
5036 bnx2_free_skbs(bp);
5037 bnx2_free_mem(bp);
5038 del_timer_sync(&bp->timer);
5039 return rc;
5040 }
5041 bnx2_enable_int(bp);
5042 }
5043 }
5044 if (bp->flags & USING_MSI_FLAG) {
5045 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5046 }
5047
5048 netif_start_queue(dev);
5049
5050 return 0;
5051 }
5052
5053 static void
5054 bnx2_reset_task(struct work_struct *work)
5055 {
5056 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5057
5058 if (!netif_running(bp->dev))
5059 return;
5060
5061 bp->in_reset_task = 1;
5062 bnx2_netif_stop(bp);
5063
5064 bnx2_init_nic(bp);
5065
5066 atomic_set(&bp->intr_sem, 1);
5067 bnx2_netif_start(bp);
5068 bp->in_reset_task = 0;
5069 }
5070
5071 static void
5072 bnx2_tx_timeout(struct net_device *dev)
5073 {
5074 struct bnx2 *bp = netdev_priv(dev);
5075
5076 /* This allows the netif to be shutdown gracefully before resetting */
5077 schedule_work(&bp->reset_task);
5078 }
5079
5080 #ifdef BCM_VLAN
5081 /* Called with rtnl_lock */
5082 static void
5083 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5084 {
5085 struct bnx2 *bp = netdev_priv(dev);
5086
5087 bnx2_netif_stop(bp);
5088
5089 bp->vlgrp = vlgrp;
5090 bnx2_set_rx_mode(dev);
5091
5092 bnx2_netif_start(bp);
5093 }
5094 #endif
5095
5096 /* Called with netif_tx_lock.
5097 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5098 * netif_wake_queue().
5099 */
5100 static int
5101 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5102 {
5103 struct bnx2 *bp = netdev_priv(dev);
5104 dma_addr_t mapping;
5105 struct tx_bd *txbd;
5106 struct sw_bd *tx_buf;
5107 u32 len, vlan_tag_flags, last_frag, mss;
5108 u16 prod, ring_prod;
5109 int i;
5110
5111 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
5112 netif_stop_queue(dev);
5113 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5114 dev->name);
5115
5116 return NETDEV_TX_BUSY;
5117 }
5118 len = skb_headlen(skb);
5119 prod = bp->tx_prod;
5120 ring_prod = TX_RING_IDX(prod);
5121
5122 vlan_tag_flags = 0;
5123 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5124 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5125 }
5126
5127 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
5128 vlan_tag_flags |=
5129 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5130 }
5131 if ((mss = skb_shinfo(skb)->gso_size)) {
5132 u32 tcp_opt_len, ip_tcp_len;
5133 struct iphdr *iph;
5134
5135 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5136
5137 tcp_opt_len = tcp_optlen(skb);
5138
5139 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5140 u32 tcp_off = skb_transport_offset(skb) -
5141 sizeof(struct ipv6hdr) - ETH_HLEN;
5142
5143 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5144 TX_BD_FLAGS_SW_FLAGS;
5145 if (likely(tcp_off == 0))
5146 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5147 else {
5148 tcp_off >>= 3;
5149 vlan_tag_flags |= ((tcp_off & 0x3) <<
5150 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5151 ((tcp_off & 0x10) <<
5152 TX_BD_FLAGS_TCP6_OFF4_SHL);
5153 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5154 }
5155 } else {
5156 if (skb_header_cloned(skb) &&
5157 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5158 dev_kfree_skb(skb);
5159 return NETDEV_TX_OK;
5160 }
5161
5162 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5163
5164 iph = ip_hdr(skb);
5165 iph->check = 0;
5166 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5167 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5168 iph->daddr, 0,
5169 IPPROTO_TCP,
5170 0);
5171 if (tcp_opt_len || (iph->ihl > 5)) {
5172 vlan_tag_flags |= ((iph->ihl - 5) +
5173 (tcp_opt_len >> 2)) << 8;
5174 }
5175 }
5176 } else
5177 mss = 0;
5178
5179 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5180
5181 tx_buf = &bp->tx_buf_ring[ring_prod];
5182 tx_buf->skb = skb;
5183 pci_unmap_addr_set(tx_buf, mapping, mapping);
5184
5185 txbd = &bp->tx_desc_ring[ring_prod];
5186
5187 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5188 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5189 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5190 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5191
5192 last_frag = skb_shinfo(skb)->nr_frags;
5193
5194 for (i = 0; i < last_frag; i++) {
5195 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5196
5197 prod = NEXT_TX_BD(prod);
5198 ring_prod = TX_RING_IDX(prod);
5199 txbd = &bp->tx_desc_ring[ring_prod];
5200
5201 len = frag->size;
5202 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5203 len, PCI_DMA_TODEVICE);
5204 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5205 mapping, mapping);
5206
5207 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5208 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5209 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5210 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5211
5212 }
5213 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5214
5215 prod = NEXT_TX_BD(prod);
5216 bp->tx_prod_bseq += skb->len;
5217
5218 REG_WR16(bp, bp->tx_bidx_addr, prod);
5219 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5220
5221 mmiowb();
5222
5223 bp->tx_prod = prod;
5224 dev->trans_start = jiffies;
5225
5226 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
5227 netif_stop_queue(dev);
5228 if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
5229 netif_wake_queue(dev);
5230 }
5231
5232 return NETDEV_TX_OK;
5233 }
5234
5235 /* Called with rtnl_lock */
5236 static int
5237 bnx2_close(struct net_device *dev)
5238 {
5239 struct bnx2 *bp = netdev_priv(dev);
5240 u32 reset_code;
5241
5242 /* Calling flush_scheduled_work() may deadlock because
5243 * linkwatch_event() may be on the workqueue and it will try to get
5244 * the rtnl_lock which we are holding.
5245 */
5246 while (bp->in_reset_task)
5247 msleep(1);
5248
5249 bnx2_disable_int_sync(bp);
5250 napi_disable(&bp->napi);
5251 del_timer_sync(&bp->timer);
5252 if (bp->flags & NO_WOL_FLAG)
5253 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5254 else if (bp->wol)
5255 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5256 else
5257 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5258 bnx2_reset_chip(bp, reset_code);
5259 bnx2_free_irq(bp);
5260 bnx2_free_skbs(bp);
5261 bnx2_free_mem(bp);
5262 bp->link_up = 0;
5263 netif_carrier_off(bp->dev);
5264 bnx2_set_power_state(bp, PCI_D3hot);
5265 return 0;
5266 }
5267
5268 #define GET_NET_STATS64(ctr) \
5269 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5270 (unsigned long) (ctr##_lo)
5271
5272 #define GET_NET_STATS32(ctr) \
5273 (ctr##_lo)
5274
5275 #if (BITS_PER_LONG == 64)
5276 #define GET_NET_STATS GET_NET_STATS64
5277 #else
5278 #define GET_NET_STATS GET_NET_STATS32
5279 #endif
5280
5281 static struct net_device_stats *
5282 bnx2_get_stats(struct net_device *dev)
5283 {
5284 struct bnx2 *bp = netdev_priv(dev);
5285 struct statistics_block *stats_blk = bp->stats_blk;
5286 struct net_device_stats *net_stats = &bp->net_stats;
5287
5288 if (bp->stats_blk == NULL) {
5289 return net_stats;
5290 }
5291 net_stats->rx_packets =
5292 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5293 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5294 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5295
5296 net_stats->tx_packets =
5297 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5298 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5299 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5300
5301 net_stats->rx_bytes =
5302 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5303
5304 net_stats->tx_bytes =
5305 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5306
5307 net_stats->multicast =
5308 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5309
5310 net_stats->collisions =
5311 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5312
5313 net_stats->rx_length_errors =
5314 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5315 stats_blk->stat_EtherStatsOverrsizePkts);
5316
5317 net_stats->rx_over_errors =
5318 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5319
5320 net_stats->rx_frame_errors =
5321 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5322
5323 net_stats->rx_crc_errors =
5324 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5325
5326 net_stats->rx_errors = net_stats->rx_length_errors +
5327 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5328 net_stats->rx_crc_errors;
5329
5330 net_stats->tx_aborted_errors =
5331 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5332 stats_blk->stat_Dot3StatsLateCollisions);
5333
5334 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5335 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5336 net_stats->tx_carrier_errors = 0;
5337 else {
5338 net_stats->tx_carrier_errors =
5339 (unsigned long)
5340 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5341 }
5342
5343 net_stats->tx_errors =
5344 (unsigned long)
5345 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5346 +
5347 net_stats->tx_aborted_errors +
5348 net_stats->tx_carrier_errors;
5349
5350 net_stats->rx_missed_errors =
5351 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5352 stats_blk->stat_FwRxDrop);
5353
5354 return net_stats;
5355 }
5356
5357 /* All ethtool functions called with rtnl_lock */
5358
5359 static int
5360 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5361 {
5362 struct bnx2 *bp = netdev_priv(dev);
5363 int support_serdes = 0, support_copper = 0;
5364
5365 cmd->supported = SUPPORTED_Autoneg;
5366 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5367 support_serdes = 1;
5368 support_copper = 1;
5369 } else if (bp->phy_port == PORT_FIBRE)
5370 support_serdes = 1;
5371 else
5372 support_copper = 1;
5373
5374 if (support_serdes) {
5375 cmd->supported |= SUPPORTED_1000baseT_Full |
5376 SUPPORTED_FIBRE;
5377 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
5378 cmd->supported |= SUPPORTED_2500baseX_Full;
5379
5380 }
5381 if (support_copper) {
5382 cmd->supported |= SUPPORTED_10baseT_Half |
5383 SUPPORTED_10baseT_Full |
5384 SUPPORTED_100baseT_Half |
5385 SUPPORTED_100baseT_Full |
5386 SUPPORTED_1000baseT_Full |
5387 SUPPORTED_TP;
5388
5389 }
5390
5391 spin_lock_bh(&bp->phy_lock);
5392 cmd->port = bp->phy_port;
5393 cmd->advertising = bp->advertising;
5394
5395 if (bp->autoneg & AUTONEG_SPEED) {
5396 cmd->autoneg = AUTONEG_ENABLE;
5397 }
5398 else {
5399 cmd->autoneg = AUTONEG_DISABLE;
5400 }
5401
5402 if (netif_carrier_ok(dev)) {
5403 cmd->speed = bp->line_speed;
5404 cmd->duplex = bp->duplex;
5405 }
5406 else {
5407 cmd->speed = -1;
5408 cmd->duplex = -1;
5409 }
5410 spin_unlock_bh(&bp->phy_lock);
5411
5412 cmd->transceiver = XCVR_INTERNAL;
5413 cmd->phy_address = bp->phy_addr;
5414
5415 return 0;
5416 }
5417
5418 static int
5419 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5420 {
5421 struct bnx2 *bp = netdev_priv(dev);
5422 u8 autoneg = bp->autoneg;
5423 u8 req_duplex = bp->req_duplex;
5424 u16 req_line_speed = bp->req_line_speed;
5425 u32 advertising = bp->advertising;
5426 int err = -EINVAL;
5427
5428 spin_lock_bh(&bp->phy_lock);
5429
5430 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
5431 goto err_out_unlock;
5432
5433 if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG))
5434 goto err_out_unlock;
5435
5436 if (cmd->autoneg == AUTONEG_ENABLE) {
5437 autoneg |= AUTONEG_SPEED;
5438
5439 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
5440
5441 /* allow advertising 1 speed */
5442 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
5443 (cmd->advertising == ADVERTISED_10baseT_Full) ||
5444 (cmd->advertising == ADVERTISED_100baseT_Half) ||
5445 (cmd->advertising == ADVERTISED_100baseT_Full)) {
5446
5447 if (cmd->port == PORT_FIBRE)
5448 goto err_out_unlock;
5449
5450 advertising = cmd->advertising;
5451
5452 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
5453 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ||
5454 (cmd->port == PORT_TP))
5455 goto err_out_unlock;
5456 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
5457 advertising = cmd->advertising;
5458 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
5459 goto err_out_unlock;
5460 else {
5461 if (cmd->port == PORT_FIBRE)
5462 advertising = ETHTOOL_ALL_FIBRE_SPEED;
5463 else
5464 advertising = ETHTOOL_ALL_COPPER_SPEED;
5465 }
5466 advertising |= ADVERTISED_Autoneg;
5467 }
5468 else {
5469 if (cmd->port == PORT_FIBRE) {
5470 if ((cmd->speed != SPEED_1000 &&
5471 cmd->speed != SPEED_2500) ||
5472 (cmd->duplex != DUPLEX_FULL))
5473 goto err_out_unlock;
5474
5475 if (cmd->speed == SPEED_2500 &&
5476 !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
5477 goto err_out_unlock;
5478 }
5479 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
5480 goto err_out_unlock;
5481
5482 autoneg &= ~AUTONEG_SPEED;
5483 req_line_speed = cmd->speed;
5484 req_duplex = cmd->duplex;
5485 advertising = 0;
5486 }
5487
5488 bp->autoneg = autoneg;
5489 bp->advertising = advertising;
5490 bp->req_line_speed = req_line_speed;
5491 bp->req_duplex = req_duplex;
5492
5493 err = bnx2_setup_phy(bp, cmd->port);
5494
5495 err_out_unlock:
5496 spin_unlock_bh(&bp->phy_lock);
5497
5498 return err;
5499 }
5500
5501 static void
5502 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5503 {
5504 struct bnx2 *bp = netdev_priv(dev);
5505
5506 strcpy(info->driver, DRV_MODULE_NAME);
5507 strcpy(info->version, DRV_MODULE_VERSION);
5508 strcpy(info->bus_info, pci_name(bp->pdev));
5509 strcpy(info->fw_version, bp->fw_version);
5510 }
5511
5512 #define BNX2_REGDUMP_LEN (32 * 1024)
5513
5514 static int
5515 bnx2_get_regs_len(struct net_device *dev)
5516 {
5517 return BNX2_REGDUMP_LEN;
5518 }
5519
5520 static void
5521 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
5522 {
5523 u32 *p = _p, i, offset;
5524 u8 *orig_p = _p;
5525 struct bnx2 *bp = netdev_priv(dev);
5526 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
5527 0x0800, 0x0880, 0x0c00, 0x0c10,
5528 0x0c30, 0x0d08, 0x1000, 0x101c,
5529 0x1040, 0x1048, 0x1080, 0x10a4,
5530 0x1400, 0x1490, 0x1498, 0x14f0,
5531 0x1500, 0x155c, 0x1580, 0x15dc,
5532 0x1600, 0x1658, 0x1680, 0x16d8,
5533 0x1800, 0x1820, 0x1840, 0x1854,
5534 0x1880, 0x1894, 0x1900, 0x1984,
5535 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
5536 0x1c80, 0x1c94, 0x1d00, 0x1d84,
5537 0x2000, 0x2030, 0x23c0, 0x2400,
5538 0x2800, 0x2820, 0x2830, 0x2850,
5539 0x2b40, 0x2c10, 0x2fc0, 0x3058,
5540 0x3c00, 0x3c94, 0x4000, 0x4010,
5541 0x4080, 0x4090, 0x43c0, 0x4458,
5542 0x4c00, 0x4c18, 0x4c40, 0x4c54,
5543 0x4fc0, 0x5010, 0x53c0, 0x5444,
5544 0x5c00, 0x5c18, 0x5c80, 0x5c90,
5545 0x5fc0, 0x6000, 0x6400, 0x6428,
5546 0x6800, 0x6848, 0x684c, 0x6860,
5547 0x6888, 0x6910, 0x8000 };
5548
5549 regs->version = 0;
5550
5551 memset(p, 0, BNX2_REGDUMP_LEN);
5552
5553 if (!netif_running(bp->dev))
5554 return;
5555
5556 i = 0;
5557 offset = reg_boundaries[0];
5558 p += offset;
5559 while (offset < BNX2_REGDUMP_LEN) {
5560 *p++ = REG_RD(bp, offset);
5561 offset += 4;
5562 if (offset == reg_boundaries[i + 1]) {
5563 offset = reg_boundaries[i + 2];
5564 p = (u32 *) (orig_p + offset);
5565 i += 2;
5566 }
5567 }
5568 }
5569
5570 static void
5571 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5572 {
5573 struct bnx2 *bp = netdev_priv(dev);
5574
5575 if (bp->flags & NO_WOL_FLAG) {
5576 wol->supported = 0;
5577 wol->wolopts = 0;
5578 }
5579 else {
5580 wol->supported = WAKE_MAGIC;
5581 if (bp->wol)
5582 wol->wolopts = WAKE_MAGIC;
5583 else
5584 wol->wolopts = 0;
5585 }
5586 memset(&wol->sopass, 0, sizeof(wol->sopass));
5587 }
5588
5589 static int
5590 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5591 {
5592 struct bnx2 *bp = netdev_priv(dev);
5593
5594 if (wol->wolopts & ~WAKE_MAGIC)
5595 return -EINVAL;
5596
5597 if (wol->wolopts & WAKE_MAGIC) {
5598 if (bp->flags & NO_WOL_FLAG)
5599 return -EINVAL;
5600
5601 bp->wol = 1;
5602 }
5603 else {
5604 bp->wol = 0;
5605 }
5606 return 0;
5607 }
5608
5609 static int
5610 bnx2_nway_reset(struct net_device *dev)
5611 {
5612 struct bnx2 *bp = netdev_priv(dev);
5613 u32 bmcr;
5614
5615 if (!(bp->autoneg & AUTONEG_SPEED)) {
5616 return -EINVAL;
5617 }
5618
5619 spin_lock_bh(&bp->phy_lock);
5620
5621 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5622 int rc;
5623
5624 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
5625 spin_unlock_bh(&bp->phy_lock);
5626 return rc;
5627 }
5628
5629 /* Force a link down visible on the other side */
5630 if (bp->phy_flags & PHY_SERDES_FLAG) {
5631 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
5632 spin_unlock_bh(&bp->phy_lock);
5633
5634 msleep(20);
5635
5636 spin_lock_bh(&bp->phy_lock);
5637
5638 bp->current_interval = SERDES_AN_TIMEOUT;
5639 bp->serdes_an_pending = 1;
5640 mod_timer(&bp->timer, jiffies + bp->current_interval);
5641 }
5642
5643 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5644 bmcr &= ~BMCR_LOOPBACK;
5645 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5646
5647 spin_unlock_bh(&bp->phy_lock);
5648
5649 return 0;
5650 }
5651
5652 static int
5653 bnx2_get_eeprom_len(struct net_device *dev)
5654 {
5655 struct bnx2 *bp = netdev_priv(dev);
5656
5657 if (bp->flash_info == NULL)
5658 return 0;
5659
5660 return (int) bp->flash_size;
5661 }
5662
5663 static int
5664 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5665 u8 *eebuf)
5666 {
5667 struct bnx2 *bp = netdev_priv(dev);
5668 int rc;
5669
5670 /* parameters already validated in ethtool_get_eeprom */
5671
5672 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
5673
5674 return rc;
5675 }
5676
5677 static int
5678 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5679 u8 *eebuf)
5680 {
5681 struct bnx2 *bp = netdev_priv(dev);
5682 int rc;
5683
5684 /* parameters already validated in ethtool_set_eeprom */
5685
5686 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
5687
5688 return rc;
5689 }
5690
5691 static int
5692 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5693 {
5694 struct bnx2 *bp = netdev_priv(dev);
5695
5696 memset(coal, 0, sizeof(struct ethtool_coalesce));
5697
5698 coal->rx_coalesce_usecs = bp->rx_ticks;
5699 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
5700 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
5701 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
5702
5703 coal->tx_coalesce_usecs = bp->tx_ticks;
5704 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
5705 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
5706 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
5707
5708 coal->stats_block_coalesce_usecs = bp->stats_ticks;
5709
5710 return 0;
5711 }
5712
5713 static int
5714 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5715 {
5716 struct bnx2 *bp = netdev_priv(dev);
5717
5718 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
5719 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
5720
5721 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
5722 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
5723
5724 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
5725 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
5726
5727 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
5728 if (bp->rx_quick_cons_trip_int > 0xff)
5729 bp->rx_quick_cons_trip_int = 0xff;
5730
5731 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5732 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5733
5734 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5735 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5736
5737 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5738 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5739
5740 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5741 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5742 0xff;
5743
5744 bp->stats_ticks = coal->stats_block_coalesce_usecs;
5745 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5746 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
5747 bp->stats_ticks = USEC_PER_SEC;
5748 }
5749 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
5750 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5751 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5752
5753 if (netif_running(bp->dev)) {
5754 bnx2_netif_stop(bp);
5755 bnx2_init_nic(bp);
5756 bnx2_netif_start(bp);
5757 }
5758
5759 return 0;
5760 }
5761
5762 static void
5763 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5764 {
5765 struct bnx2 *bp = netdev_priv(dev);
5766
5767 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5768 ering->rx_mini_max_pending = 0;
5769 ering->rx_jumbo_max_pending = 0;
5770
5771 ering->rx_pending = bp->rx_ring_size;
5772 ering->rx_mini_pending = 0;
5773 ering->rx_jumbo_pending = 0;
5774
5775 ering->tx_max_pending = MAX_TX_DESC_CNT;
5776 ering->tx_pending = bp->tx_ring_size;
5777 }
5778
5779 static int
5780 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5781 {
5782 struct bnx2 *bp = netdev_priv(dev);
5783
5784 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5785 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5786 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5787
5788 return -EINVAL;
5789 }
5790 if (netif_running(bp->dev)) {
5791 bnx2_netif_stop(bp);
5792 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5793 bnx2_free_skbs(bp);
5794 bnx2_free_mem(bp);
5795 }
5796
5797 bnx2_set_rx_ring_size(bp, ering->rx_pending);
5798 bp->tx_ring_size = ering->tx_pending;
5799
5800 if (netif_running(bp->dev)) {
5801 int rc;
5802
5803 rc = bnx2_alloc_mem(bp);
5804 if (rc)
5805 return rc;
5806 bnx2_init_nic(bp);
5807 bnx2_netif_start(bp);
5808 }
5809
5810 return 0;
5811 }
5812
5813 static void
5814 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5815 {
5816 struct bnx2 *bp = netdev_priv(dev);
5817
5818 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5819 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5820 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5821 }
5822
5823 static int
5824 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5825 {
5826 struct bnx2 *bp = netdev_priv(dev);
5827
5828 bp->req_flow_ctrl = 0;
5829 if (epause->rx_pause)
5830 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5831 if (epause->tx_pause)
5832 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5833
5834 if (epause->autoneg) {
5835 bp->autoneg |= AUTONEG_FLOW_CTRL;
5836 }
5837 else {
5838 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5839 }
5840
5841 spin_lock_bh(&bp->phy_lock);
5842
5843 bnx2_setup_phy(bp, bp->phy_port);
5844
5845 spin_unlock_bh(&bp->phy_lock);
5846
5847 return 0;
5848 }
5849
5850 static u32
5851 bnx2_get_rx_csum(struct net_device *dev)
5852 {
5853 struct bnx2 *bp = netdev_priv(dev);
5854
5855 return bp->rx_csum;
5856 }
5857
5858 static int
5859 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5860 {
5861 struct bnx2 *bp = netdev_priv(dev);
5862
5863 bp->rx_csum = data;
5864 return 0;
5865 }
5866
5867 static int
5868 bnx2_set_tso(struct net_device *dev, u32 data)
5869 {
5870 struct bnx2 *bp = netdev_priv(dev);
5871
5872 if (data) {
5873 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5874 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5875 dev->features |= NETIF_F_TSO6;
5876 } else
5877 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
5878 NETIF_F_TSO_ECN);
5879 return 0;
5880 }
5881
5882 #define BNX2_NUM_STATS 46
5883
5884 static struct {
5885 char string[ETH_GSTRING_LEN];
5886 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5887 { "rx_bytes" },
5888 { "rx_error_bytes" },
5889 { "tx_bytes" },
5890 { "tx_error_bytes" },
5891 { "rx_ucast_packets" },
5892 { "rx_mcast_packets" },
5893 { "rx_bcast_packets" },
5894 { "tx_ucast_packets" },
5895 { "tx_mcast_packets" },
5896 { "tx_bcast_packets" },
5897 { "tx_mac_errors" },
5898 { "tx_carrier_errors" },
5899 { "rx_crc_errors" },
5900 { "rx_align_errors" },
5901 { "tx_single_collisions" },
5902 { "tx_multi_collisions" },
5903 { "tx_deferred" },
5904 { "tx_excess_collisions" },
5905 { "tx_late_collisions" },
5906 { "tx_total_collisions" },
5907 { "rx_fragments" },
5908 { "rx_jabbers" },
5909 { "rx_undersize_packets" },
5910 { "rx_oversize_packets" },
5911 { "rx_64_byte_packets" },
5912 { "rx_65_to_127_byte_packets" },
5913 { "rx_128_to_255_byte_packets" },
5914 { "rx_256_to_511_byte_packets" },
5915 { "rx_512_to_1023_byte_packets" },
5916 { "rx_1024_to_1522_byte_packets" },
5917 { "rx_1523_to_9022_byte_packets" },
5918 { "tx_64_byte_packets" },
5919 { "tx_65_to_127_byte_packets" },
5920 { "tx_128_to_255_byte_packets" },
5921 { "tx_256_to_511_byte_packets" },
5922 { "tx_512_to_1023_byte_packets" },
5923 { "tx_1024_to_1522_byte_packets" },
5924 { "tx_1523_to_9022_byte_packets" },
5925 { "rx_xon_frames" },
5926 { "rx_xoff_frames" },
5927 { "tx_xon_frames" },
5928 { "tx_xoff_frames" },
5929 { "rx_mac_ctrl_frames" },
5930 { "rx_filtered_packets" },
5931 { "rx_discards" },
5932 { "rx_fw_discards" },
5933 };
5934
5935 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5936
5937 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5938 STATS_OFFSET32(stat_IfHCInOctets_hi),
5939 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5940 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5941 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5942 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5943 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5944 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5945 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5946 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5947 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5948 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5949 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5950 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5951 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5952 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5953 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5954 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5955 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5956 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5957 STATS_OFFSET32(stat_EtherStatsCollisions),
5958 STATS_OFFSET32(stat_EtherStatsFragments),
5959 STATS_OFFSET32(stat_EtherStatsJabbers),
5960 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5961 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5962 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5963 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5964 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5965 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5966 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5967 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5968 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5969 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5970 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5971 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5972 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5973 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5974 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5975 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5976 STATS_OFFSET32(stat_XonPauseFramesReceived),
5977 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5978 STATS_OFFSET32(stat_OutXonSent),
5979 STATS_OFFSET32(stat_OutXoffSent),
5980 STATS_OFFSET32(stat_MacControlFramesReceived),
5981 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5982 STATS_OFFSET32(stat_IfInMBUFDiscards),
5983 STATS_OFFSET32(stat_FwRxDrop),
5984 };
5985
5986 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5987 * skipped because of errata.
5988 */
5989 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5990 8,0,8,8,8,8,8,8,8,8,
5991 4,0,4,4,4,4,4,4,4,4,
5992 4,4,4,4,4,4,4,4,4,4,
5993 4,4,4,4,4,4,4,4,4,4,
5994 4,4,4,4,4,4,
5995 };
5996
5997 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5998 8,0,8,8,8,8,8,8,8,8,
5999 4,4,4,4,4,4,4,4,4,4,
6000 4,4,4,4,4,4,4,4,4,4,
6001 4,4,4,4,4,4,4,4,4,4,
6002 4,4,4,4,4,4,
6003 };
6004
6005 #define BNX2_NUM_TESTS 6
6006
6007 static struct {
6008 char string[ETH_GSTRING_LEN];
6009 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6010 { "register_test (offline)" },
6011 { "memory_test (offline)" },
6012 { "loopback_test (offline)" },
6013 { "nvram_test (online)" },
6014 { "interrupt_test (online)" },
6015 { "link_test (online)" },
6016 };
6017
6018 static int
6019 bnx2_get_sset_count(struct net_device *dev, int sset)
6020 {
6021 switch (sset) {
6022 case ETH_SS_TEST:
6023 return BNX2_NUM_TESTS;
6024 case ETH_SS_STATS:
6025 return BNX2_NUM_STATS;
6026 default:
6027 return -EOPNOTSUPP;
6028 }
6029 }
6030
6031 static void
6032 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6033 {
6034 struct bnx2 *bp = netdev_priv(dev);
6035
6036 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6037 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6038 int i;
6039
6040 bnx2_netif_stop(bp);
6041 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6042 bnx2_free_skbs(bp);
6043
6044 if (bnx2_test_registers(bp) != 0) {
6045 buf[0] = 1;
6046 etest->flags |= ETH_TEST_FL_FAILED;
6047 }
6048 if (bnx2_test_memory(bp) != 0) {
6049 buf[1] = 1;
6050 etest->flags |= ETH_TEST_FL_FAILED;
6051 }
6052 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6053 etest->flags |= ETH_TEST_FL_FAILED;
6054
6055 if (!netif_running(bp->dev)) {
6056 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6057 }
6058 else {
6059 bnx2_init_nic(bp);
6060 bnx2_netif_start(bp);
6061 }
6062
6063 /* wait for link up */
6064 for (i = 0; i < 7; i++) {
6065 if (bp->link_up)
6066 break;
6067 msleep_interruptible(1000);
6068 }
6069 }
6070
6071 if (bnx2_test_nvram(bp) != 0) {
6072 buf[3] = 1;
6073 etest->flags |= ETH_TEST_FL_FAILED;
6074 }
6075 if (bnx2_test_intr(bp) != 0) {
6076 buf[4] = 1;
6077 etest->flags |= ETH_TEST_FL_FAILED;
6078 }
6079
6080 if (bnx2_test_link(bp) != 0) {
6081 buf[5] = 1;
6082 etest->flags |= ETH_TEST_FL_FAILED;
6083
6084 }
6085 }
6086
6087 static void
6088 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6089 {
6090 switch (stringset) {
6091 case ETH_SS_STATS:
6092 memcpy(buf, bnx2_stats_str_arr,
6093 sizeof(bnx2_stats_str_arr));
6094 break;
6095 case ETH_SS_TEST:
6096 memcpy(buf, bnx2_tests_str_arr,
6097 sizeof(bnx2_tests_str_arr));
6098 break;
6099 }
6100 }
6101
6102 static void
6103 bnx2_get_ethtool_stats(struct net_device *dev,
6104 struct ethtool_stats *stats, u64 *buf)
6105 {
6106 struct bnx2 *bp = netdev_priv(dev);
6107 int i;
6108 u32 *hw_stats = (u32 *) bp->stats_blk;
6109 u8 *stats_len_arr = NULL;
6110
6111 if (hw_stats == NULL) {
6112 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6113 return;
6114 }
6115
6116 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6117 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6118 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6119 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6120 stats_len_arr = bnx2_5706_stats_len_arr;
6121 else
6122 stats_len_arr = bnx2_5708_stats_len_arr;
6123
6124 for (i = 0; i < BNX2_NUM_STATS; i++) {
6125 if (stats_len_arr[i] == 0) {
6126 /* skip this counter */
6127 buf[i] = 0;
6128 continue;
6129 }
6130 if (stats_len_arr[i] == 4) {
6131 /* 4-byte counter */
6132 buf[i] = (u64)
6133 *(hw_stats + bnx2_stats_offset_arr[i]);
6134 continue;
6135 }
6136 /* 8-byte counter */
6137 buf[i] = (((u64) *(hw_stats +
6138 bnx2_stats_offset_arr[i])) << 32) +
6139 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6140 }
6141 }
6142
6143 static int
6144 bnx2_phys_id(struct net_device *dev, u32 data)
6145 {
6146 struct bnx2 *bp = netdev_priv(dev);
6147 int i;
6148 u32 save;
6149
6150 if (data == 0)
6151 data = 2;
6152
6153 save = REG_RD(bp, BNX2_MISC_CFG);
6154 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6155
6156 for (i = 0; i < (data * 2); i++) {
6157 if ((i % 2) == 0) {
6158 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6159 }
6160 else {
6161 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6162 BNX2_EMAC_LED_1000MB_OVERRIDE |
6163 BNX2_EMAC_LED_100MB_OVERRIDE |
6164 BNX2_EMAC_LED_10MB_OVERRIDE |
6165 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6166 BNX2_EMAC_LED_TRAFFIC);
6167 }
6168 msleep_interruptible(500);
6169 if (signal_pending(current))
6170 break;
6171 }
6172 REG_WR(bp, BNX2_EMAC_LED, 0);
6173 REG_WR(bp, BNX2_MISC_CFG, save);
6174 return 0;
6175 }
6176
6177 static int
6178 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6179 {
6180 struct bnx2 *bp = netdev_priv(dev);
6181
6182 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6183 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6184 else
6185 return (ethtool_op_set_tx_csum(dev, data));
6186 }
6187
6188 static const struct ethtool_ops bnx2_ethtool_ops = {
6189 .get_settings = bnx2_get_settings,
6190 .set_settings = bnx2_set_settings,
6191 .get_drvinfo = bnx2_get_drvinfo,
6192 .get_regs_len = bnx2_get_regs_len,
6193 .get_regs = bnx2_get_regs,
6194 .get_wol = bnx2_get_wol,
6195 .set_wol = bnx2_set_wol,
6196 .nway_reset = bnx2_nway_reset,
6197 .get_link = ethtool_op_get_link,
6198 .get_eeprom_len = bnx2_get_eeprom_len,
6199 .get_eeprom = bnx2_get_eeprom,
6200 .set_eeprom = bnx2_set_eeprom,
6201 .get_coalesce = bnx2_get_coalesce,
6202 .set_coalesce = bnx2_set_coalesce,
6203 .get_ringparam = bnx2_get_ringparam,
6204 .set_ringparam = bnx2_set_ringparam,
6205 .get_pauseparam = bnx2_get_pauseparam,
6206 .set_pauseparam = bnx2_set_pauseparam,
6207 .get_rx_csum = bnx2_get_rx_csum,
6208 .set_rx_csum = bnx2_set_rx_csum,
6209 .set_tx_csum = bnx2_set_tx_csum,
6210 .set_sg = ethtool_op_set_sg,
6211 .set_tso = bnx2_set_tso,
6212 .self_test = bnx2_self_test,
6213 .get_strings = bnx2_get_strings,
6214 .phys_id = bnx2_phys_id,
6215 .get_ethtool_stats = bnx2_get_ethtool_stats,
6216 .get_sset_count = bnx2_get_sset_count,
6217 };
6218
6219 /* Called with rtnl_lock */
6220 static int
6221 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6222 {
6223 struct mii_ioctl_data *data = if_mii(ifr);
6224 struct bnx2 *bp = netdev_priv(dev);
6225 int err;
6226
6227 switch(cmd) {
6228 case SIOCGMIIPHY:
6229 data->phy_id = bp->phy_addr;
6230
6231 /* fallthru */
6232 case SIOCGMIIREG: {
6233 u32 mii_regval;
6234
6235 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6236 return -EOPNOTSUPP;
6237
6238 if (!netif_running(dev))
6239 return -EAGAIN;
6240
6241 spin_lock_bh(&bp->phy_lock);
6242 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6243 spin_unlock_bh(&bp->phy_lock);
6244
6245 data->val_out = mii_regval;
6246
6247 return err;
6248 }
6249
6250 case SIOCSMIIREG:
6251 if (!capable(CAP_NET_ADMIN))
6252 return -EPERM;
6253
6254 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6255 return -EOPNOTSUPP;
6256
6257 if (!netif_running(dev))
6258 return -EAGAIN;
6259
6260 spin_lock_bh(&bp->phy_lock);
6261 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6262 spin_unlock_bh(&bp->phy_lock);
6263
6264 return err;
6265
6266 default:
6267 /* do nothing */
6268 break;
6269 }
6270 return -EOPNOTSUPP;
6271 }
6272
6273 /* Called with rtnl_lock */
6274 static int
6275 bnx2_change_mac_addr(struct net_device *dev, void *p)
6276 {
6277 struct sockaddr *addr = p;
6278 struct bnx2 *bp = netdev_priv(dev);
6279
6280 if (!is_valid_ether_addr(addr->sa_data))
6281 return -EINVAL;
6282
6283 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6284 if (netif_running(dev))
6285 bnx2_set_mac_addr(bp);
6286
6287 return 0;
6288 }
6289
6290 /* Called with rtnl_lock */
6291 static int
6292 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6293 {
6294 struct bnx2 *bp = netdev_priv(dev);
6295
6296 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6297 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6298 return -EINVAL;
6299
6300 dev->mtu = new_mtu;
6301 if (netif_running(dev)) {
6302 bnx2_netif_stop(bp);
6303
6304 bnx2_init_nic(bp);
6305
6306 bnx2_netif_start(bp);
6307 }
6308 return 0;
6309 }
6310
6311 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6312 static void
6313 poll_bnx2(struct net_device *dev)
6314 {
6315 struct bnx2 *bp = netdev_priv(dev);
6316
6317 disable_irq(bp->pdev->irq);
6318 bnx2_interrupt(bp->pdev->irq, dev);
6319 enable_irq(bp->pdev->irq);
6320 }
6321 #endif
6322
6323 static void __devinit
6324 bnx2_get_5709_media(struct bnx2 *bp)
6325 {
6326 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6327 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6328 u32 strap;
6329
6330 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6331 return;
6332 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
6333 bp->phy_flags |= PHY_SERDES_FLAG;
6334 return;
6335 }
6336
6337 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6338 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6339 else
6340 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6341
6342 if (PCI_FUNC(bp->pdev->devfn) == 0) {
6343 switch (strap) {
6344 case 0x4:
6345 case 0x5:
6346 case 0x6:
6347 bp->phy_flags |= PHY_SERDES_FLAG;
6348 return;
6349 }
6350 } else {
6351 switch (strap) {
6352 case 0x1:
6353 case 0x2:
6354 case 0x4:
6355 bp->phy_flags |= PHY_SERDES_FLAG;
6356 return;
6357 }
6358 }
6359 }
6360
6361 static void __devinit
6362 bnx2_get_pci_speed(struct bnx2 *bp)
6363 {
6364 u32 reg;
6365
6366 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
6367 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
6368 u32 clkreg;
6369
6370 bp->flags |= PCIX_FLAG;
6371
6372 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
6373
6374 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
6375 switch (clkreg) {
6376 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
6377 bp->bus_speed_mhz = 133;
6378 break;
6379
6380 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
6381 bp->bus_speed_mhz = 100;
6382 break;
6383
6384 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
6385 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
6386 bp->bus_speed_mhz = 66;
6387 break;
6388
6389 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
6390 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
6391 bp->bus_speed_mhz = 50;
6392 break;
6393
6394 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
6395 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
6396 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
6397 bp->bus_speed_mhz = 33;
6398 break;
6399 }
6400 }
6401 else {
6402 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
6403 bp->bus_speed_mhz = 66;
6404 else
6405 bp->bus_speed_mhz = 33;
6406 }
6407
6408 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
6409 bp->flags |= PCI_32BIT_FLAG;
6410
6411 }
6412
6413 static int __devinit
6414 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
6415 {
6416 struct bnx2 *bp;
6417 unsigned long mem_len;
6418 int rc, i, j;
6419 u32 reg;
6420 u64 dma_mask, persist_dma_mask;
6421
6422 SET_NETDEV_DEV(dev, &pdev->dev);
6423 bp = netdev_priv(dev);
6424
6425 bp->flags = 0;
6426 bp->phy_flags = 0;
6427
6428 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6429 rc = pci_enable_device(pdev);
6430 if (rc) {
6431 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
6432 goto err_out;
6433 }
6434
6435 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6436 dev_err(&pdev->dev,
6437 "Cannot find PCI device base address, aborting.\n");
6438 rc = -ENODEV;
6439 goto err_out_disable;
6440 }
6441
6442 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6443 if (rc) {
6444 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
6445 goto err_out_disable;
6446 }
6447
6448 pci_set_master(pdev);
6449
6450 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
6451 if (bp->pm_cap == 0) {
6452 dev_err(&pdev->dev,
6453 "Cannot find power management capability, aborting.\n");
6454 rc = -EIO;
6455 goto err_out_release;
6456 }
6457
6458 bp->dev = dev;
6459 bp->pdev = pdev;
6460
6461 spin_lock_init(&bp->phy_lock);
6462 spin_lock_init(&bp->indirect_lock);
6463 INIT_WORK(&bp->reset_task, bnx2_reset_task);
6464
6465 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
6466 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
6467 dev->mem_end = dev->mem_start + mem_len;
6468 dev->irq = pdev->irq;
6469
6470 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
6471
6472 if (!bp->regview) {
6473 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
6474 rc = -ENOMEM;
6475 goto err_out_release;
6476 }
6477
6478 /* Configure byte swap and enable write to the reg_window registers.
6479 * Rely on CPU to do target byte swapping on big endian systems
6480 * The chip's target access swapping will not swap all accesses
6481 */
6482 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
6483 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
6484 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
6485
6486 bnx2_set_power_state(bp, PCI_D0);
6487
6488 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
6489
6490 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6491 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
6492 dev_err(&pdev->dev,
6493 "Cannot find PCIE capability, aborting.\n");
6494 rc = -EIO;
6495 goto err_out_unmap;
6496 }
6497 bp->flags |= PCIE_FLAG;
6498 } else {
6499 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
6500 if (bp->pcix_cap == 0) {
6501 dev_err(&pdev->dev,
6502 "Cannot find PCIX capability, aborting.\n");
6503 rc = -EIO;
6504 goto err_out_unmap;
6505 }
6506 }
6507
6508 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
6509 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
6510 bp->flags |= MSI_CAP_FLAG;
6511 }
6512
6513 /* 5708 cannot support DMA addresses > 40-bit. */
6514 if (CHIP_NUM(bp) == CHIP_NUM_5708)
6515 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
6516 else
6517 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
6518
6519 /* Configure DMA attributes. */
6520 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
6521 dev->features |= NETIF_F_HIGHDMA;
6522 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
6523 if (rc) {
6524 dev_err(&pdev->dev,
6525 "pci_set_consistent_dma_mask failed, aborting.\n");
6526 goto err_out_unmap;
6527 }
6528 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
6529 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
6530 goto err_out_unmap;
6531 }
6532
6533 if (!(bp->flags & PCIE_FLAG))
6534 bnx2_get_pci_speed(bp);
6535
6536 /* 5706A0 may falsely detect SERR and PERR. */
6537 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6538 reg = REG_RD(bp, PCI_COMMAND);
6539 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
6540 REG_WR(bp, PCI_COMMAND, reg);
6541 }
6542 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
6543 !(bp->flags & PCIX_FLAG)) {
6544
6545 dev_err(&pdev->dev,
6546 "5706 A1 can only be used in a PCIX bus, aborting.\n");
6547 goto err_out_unmap;
6548 }
6549
6550 bnx2_init_nvram(bp);
6551
6552 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
6553
6554 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
6555 BNX2_SHM_HDR_SIGNATURE_SIG) {
6556 u32 off = PCI_FUNC(pdev->devfn) << 2;
6557
6558 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
6559 } else
6560 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
6561
6562 /* Get the permanent MAC address. First we need to make sure the
6563 * firmware is actually running.
6564 */
6565 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
6566
6567 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
6568 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
6569 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
6570 rc = -ENODEV;
6571 goto err_out_unmap;
6572 }
6573
6574 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
6575 for (i = 0, j = 0; i < 3; i++) {
6576 u8 num, k, skip0;
6577
6578 num = (u8) (reg >> (24 - (i * 8)));
6579 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
6580 if (num >= k || !skip0 || k == 1) {
6581 bp->fw_version[j++] = (num / k) + '0';
6582 skip0 = 0;
6583 }
6584 }
6585 if (i != 2)
6586 bp->fw_version[j++] = '.';
6587 }
6588 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);
6589 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
6590 bp->wol = 1;
6591
6592 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
6593 bp->flags |= ASF_ENABLE_FLAG;
6594
6595 for (i = 0; i < 30; i++) {
6596 reg = REG_RD_IND(bp, bp->shmem_base +
6597 BNX2_BC_STATE_CONDITION);
6598 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
6599 break;
6600 msleep(10);
6601 }
6602 }
6603 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);
6604 reg &= BNX2_CONDITION_MFW_RUN_MASK;
6605 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
6606 reg != BNX2_CONDITION_MFW_RUN_NONE) {
6607 int i;
6608 u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR);
6609
6610 bp->fw_version[j++] = ' ';
6611 for (i = 0; i < 3; i++) {
6612 reg = REG_RD_IND(bp, addr + i * 4);
6613 reg = swab32(reg);
6614 memcpy(&bp->fw_version[j], &reg, 4);
6615 j += 4;
6616 }
6617 }
6618
6619 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
6620 bp->mac_addr[0] = (u8) (reg >> 8);
6621 bp->mac_addr[1] = (u8) reg;
6622
6623 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
6624 bp->mac_addr[2] = (u8) (reg >> 24);
6625 bp->mac_addr[3] = (u8) (reg >> 16);
6626 bp->mac_addr[4] = (u8) (reg >> 8);
6627 bp->mac_addr[5] = (u8) reg;
6628
6629 bp->tx_ring_size = MAX_TX_DESC_CNT;
6630 bnx2_set_rx_ring_size(bp, 255);
6631
6632 bp->rx_csum = 1;
6633
6634 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
6635
6636 bp->tx_quick_cons_trip_int = 20;
6637 bp->tx_quick_cons_trip = 20;
6638 bp->tx_ticks_int = 80;
6639 bp->tx_ticks = 80;
6640
6641 bp->rx_quick_cons_trip_int = 6;
6642 bp->rx_quick_cons_trip = 6;
6643 bp->rx_ticks_int = 18;
6644 bp->rx_ticks = 18;
6645
6646 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6647
6648 bp->timer_interval = HZ;
6649 bp->current_interval = HZ;
6650
6651 bp->phy_addr = 1;
6652
6653 /* Disable WOL support if we are running on a SERDES chip. */
6654 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6655 bnx2_get_5709_media(bp);
6656 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
6657 bp->phy_flags |= PHY_SERDES_FLAG;
6658
6659 bp->phy_port = PORT_TP;
6660 if (bp->phy_flags & PHY_SERDES_FLAG) {
6661 bp->phy_port = PORT_FIBRE;
6662 reg = REG_RD_IND(bp, bp->shmem_base +
6663 BNX2_SHARED_HW_CFG_CONFIG);
6664 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
6665 bp->flags |= NO_WOL_FLAG;
6666 bp->wol = 0;
6667 }
6668 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
6669 bp->phy_addr = 2;
6670 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
6671 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
6672 }
6673 bnx2_init_remote_phy(bp);
6674
6675 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
6676 CHIP_NUM(bp) == CHIP_NUM_5708)
6677 bp->phy_flags |= PHY_CRC_FIX_FLAG;
6678 else if (CHIP_ID(bp) == CHIP_ID_5709_A0 ||
6679 CHIP_ID(bp) == CHIP_ID_5709_A1)
6680 bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG;
6681
6682 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
6683 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
6684 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
6685 bp->flags |= NO_WOL_FLAG;
6686 bp->wol = 0;
6687 }
6688
6689 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6690 bp->tx_quick_cons_trip_int =
6691 bp->tx_quick_cons_trip;
6692 bp->tx_ticks_int = bp->tx_ticks;
6693 bp->rx_quick_cons_trip_int =
6694 bp->rx_quick_cons_trip;
6695 bp->rx_ticks_int = bp->rx_ticks;
6696 bp->comp_prod_trip_int = bp->comp_prod_trip;
6697 bp->com_ticks_int = bp->com_ticks;
6698 bp->cmd_ticks_int = bp->cmd_ticks;
6699 }
6700
6701 /* Disable MSI on 5706 if AMD 8132 bridge is found.
6702 *
6703 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
6704 * with byte enables disabled on the unused 32-bit word. This is legal
6705 * but causes problems on the AMD 8132 which will eventually stop
6706 * responding after a while.
6707 *
6708 * AMD believes this incompatibility is unique to the 5706, and
6709 * prefers to locally disable MSI rather than globally disabling it.
6710 */
6711 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
6712 struct pci_dev *amd_8132 = NULL;
6713
6714 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
6715 PCI_DEVICE_ID_AMD_8132_BRIDGE,
6716 amd_8132))) {
6717
6718 if (amd_8132->revision >= 0x10 &&
6719 amd_8132->revision <= 0x13) {
6720 disable_msi = 1;
6721 pci_dev_put(amd_8132);
6722 break;
6723 }
6724 }
6725 }
6726
6727 bnx2_set_default_link(bp);
6728 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
6729
6730 init_timer(&bp->timer);
6731 bp->timer.expires = RUN_AT(bp->timer_interval);
6732 bp->timer.data = (unsigned long) bp;
6733 bp->timer.function = bnx2_timer;
6734
6735 return 0;
6736
6737 err_out_unmap:
6738 if (bp->regview) {
6739 iounmap(bp->regview);
6740 bp->regview = NULL;
6741 }
6742
6743 err_out_release:
6744 pci_release_regions(pdev);
6745
6746 err_out_disable:
6747 pci_disable_device(pdev);
6748 pci_set_drvdata(pdev, NULL);
6749
6750 err_out:
6751 return rc;
6752 }
6753
6754 static char * __devinit
6755 bnx2_bus_string(struct bnx2 *bp, char *str)
6756 {
6757 char *s = str;
6758
6759 if (bp->flags & PCIE_FLAG) {
6760 s += sprintf(s, "PCI Express");
6761 } else {
6762 s += sprintf(s, "PCI");
6763 if (bp->flags & PCIX_FLAG)
6764 s += sprintf(s, "-X");
6765 if (bp->flags & PCI_32BIT_FLAG)
6766 s += sprintf(s, " 32-bit");
6767 else
6768 s += sprintf(s, " 64-bit");
6769 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
6770 }
6771 return str;
6772 }
6773
6774 static int __devinit
6775 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6776 {
6777 static int version_printed = 0;
6778 struct net_device *dev = NULL;
6779 struct bnx2 *bp;
6780 int rc;
6781 char str[40];
6782 DECLARE_MAC_BUF(mac);
6783
6784 if (version_printed++ == 0)
6785 printk(KERN_INFO "%s", version);
6786
6787 /* dev zeroed in init_etherdev */
6788 dev = alloc_etherdev(sizeof(*bp));
6789
6790 if (!dev)
6791 return -ENOMEM;
6792
6793 rc = bnx2_init_board(pdev, dev);
6794 if (rc < 0) {
6795 free_netdev(dev);
6796 return rc;
6797 }
6798
6799 dev->open = bnx2_open;
6800 dev->hard_start_xmit = bnx2_start_xmit;
6801 dev->stop = bnx2_close;
6802 dev->get_stats = bnx2_get_stats;
6803 dev->set_multicast_list = bnx2_set_rx_mode;
6804 dev->do_ioctl = bnx2_ioctl;
6805 dev->set_mac_address = bnx2_change_mac_addr;
6806 dev->change_mtu = bnx2_change_mtu;
6807 dev->tx_timeout = bnx2_tx_timeout;
6808 dev->watchdog_timeo = TX_TIMEOUT;
6809 #ifdef BCM_VLAN
6810 dev->vlan_rx_register = bnx2_vlan_rx_register;
6811 #endif
6812 dev->ethtool_ops = &bnx2_ethtool_ops;
6813
6814 bp = netdev_priv(dev);
6815 netif_napi_add(dev, &bp->napi, bnx2_poll, 64);
6816
6817 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6818 dev->poll_controller = poll_bnx2;
6819 #endif
6820
6821 pci_set_drvdata(pdev, dev);
6822
6823 memcpy(dev->dev_addr, bp->mac_addr, 6);
6824 memcpy(dev->perm_addr, bp->mac_addr, 6);
6825 bp->name = board_info[ent->driver_data].name;
6826
6827 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
6828 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6829 dev->features |= NETIF_F_IPV6_CSUM;
6830
6831 #ifdef BCM_VLAN
6832 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6833 #endif
6834 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6835 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6836 dev->features |= NETIF_F_TSO6;
6837
6838 if ((rc = register_netdev(dev))) {
6839 dev_err(&pdev->dev, "Cannot register net device\n");
6840 if (bp->regview)
6841 iounmap(bp->regview);
6842 pci_release_regions(pdev);
6843 pci_disable_device(pdev);
6844 pci_set_drvdata(pdev, NULL);
6845 free_netdev(dev);
6846 return rc;
6847 }
6848
6849 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
6850 "IRQ %d, node addr %s\n",
6851 dev->name,
6852 bp->name,
6853 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
6854 ((CHIP_ID(bp) & 0x0ff0) >> 4),
6855 bnx2_bus_string(bp, str),
6856 dev->base_addr,
6857 bp->pdev->irq, print_mac(mac, dev->dev_addr));
6858
6859 return 0;
6860 }
6861
6862 static void __devexit
6863 bnx2_remove_one(struct pci_dev *pdev)
6864 {
6865 struct net_device *dev = pci_get_drvdata(pdev);
6866 struct bnx2 *bp = netdev_priv(dev);
6867
6868 flush_scheduled_work();
6869
6870 unregister_netdev(dev);
6871
6872 if (bp->regview)
6873 iounmap(bp->regview);
6874
6875 free_netdev(dev);
6876 pci_release_regions(pdev);
6877 pci_disable_device(pdev);
6878 pci_set_drvdata(pdev, NULL);
6879 }
6880
6881 static int
6882 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
6883 {
6884 struct net_device *dev = pci_get_drvdata(pdev);
6885 struct bnx2 *bp = netdev_priv(dev);
6886 u32 reset_code;
6887
6888 /* PCI register 4 needs to be saved whether netif_running() or not.
6889 * MSI address and data need to be saved if using MSI and
6890 * netif_running().
6891 */
6892 pci_save_state(pdev);
6893 if (!netif_running(dev))
6894 return 0;
6895
6896 flush_scheduled_work();
6897 bnx2_netif_stop(bp);
6898 netif_device_detach(dev);
6899 del_timer_sync(&bp->timer);
6900 if (bp->flags & NO_WOL_FLAG)
6901 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
6902 else if (bp->wol)
6903 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
6904 else
6905 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
6906 bnx2_reset_chip(bp, reset_code);
6907 bnx2_free_skbs(bp);
6908 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
6909 return 0;
6910 }
6911
6912 static int
6913 bnx2_resume(struct pci_dev *pdev)
6914 {
6915 struct net_device *dev = pci_get_drvdata(pdev);
6916 struct bnx2 *bp = netdev_priv(dev);
6917
6918 pci_restore_state(pdev);
6919 if (!netif_running(dev))
6920 return 0;
6921
6922 bnx2_set_power_state(bp, PCI_D0);
6923 netif_device_attach(dev);
6924 bnx2_init_nic(bp);
6925 bnx2_netif_start(bp);
6926 return 0;
6927 }
6928
6929 static struct pci_driver bnx2_pci_driver = {
6930 .name = DRV_MODULE_NAME,
6931 .id_table = bnx2_pci_tbl,
6932 .probe = bnx2_init_one,
6933 .remove = __devexit_p(bnx2_remove_one),
6934 .suspend = bnx2_suspend,
6935 .resume = bnx2_resume,
6936 };
6937
6938 static int __init bnx2_init(void)
6939 {
6940 return pci_register_driver(&bnx2_pci_driver);
6941 }
6942
6943 static void __exit bnx2_cleanup(void)
6944 {
6945 pci_unregister_driver(&bnx2_pci_driver);
6946 }
6947
6948 module_init(bnx2_init);
6949 module_exit(bnx2_cleanup);
6950
6951
6952
Linus' kernel tree