2 * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
4 * Written by : Luke Lee
5 * Copyright (C) 2005 Faraday Corp.
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 * These are the low level assembler for performing cache and TLB
15 * functions on the fa526.
17 #include <linux/linkage.h>
18 #include <linux/init.h>
19 #include <asm/assembler.h>
20 #include <asm/hwcap.h>
21 #include <asm/pgtable-hwdef.h>
22 #include <asm/pgtable.h>
24 #include <asm/ptrace.h>
25 #include <asm/system.h>
27 #include "proc-macros.S"
29 #define CACHE_DLINESIZE 16
33 * cpu_fa526_proc_init()
35 ENTRY(cpu_fa526_proc_init)
39 * cpu_fa526_proc_fin()
41 ENTRY(cpu_fa526_proc_fin)
42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
43 bic r0, r0, #0x1000 @ ...i............
44 bic r0, r0, #0x000e @ ............wca.
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 * cpu_fa526_reset(loc)
53 * Perform a soft reset of the system. Put the CPU into the
54 * same state as it would be if it had been reset, and branch
55 * to what would be the reset vector.
57 * loc: location to jump to for soft reset
60 ENTRY(cpu_fa526_reset)
61 /* TODO: Use CP8 if possible... */
63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
69 bic ip, ip, #0x000f @ ............wcam
70 bic ip, ip, #0x1100 @ ...i...s........
71 bic ip, ip, #0x0800 @ BTB off
72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
81 ENTRY(cpu_fa526_do_idle)
82 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
86 ENTRY(cpu_fa526_dcache_clean_area)
87 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
88 add r0, r0, #CACHE_DLINESIZE
89 subs r1, r1, #CACHE_DLINESIZE
91 mcr p15, 0, r0, c7, c10, 4 @ drain WB
94 /* =============================== PageTable ============================== */
97 * cpu_fa526_switch_mm(pgd)
99 * Set the translation base pointer to be as described by pgd.
101 * pgd: new page tables
104 ENTRY(cpu_fa526_switch_mm)
107 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
114 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
115 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
116 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
122 * cpu_fa526_set_pte_ext(ptep, pte, ext)
124 * Set a PTE and flush it out
127 ENTRY(cpu_fa526_set_pte_ext)
131 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
133 mcr p15, 0, r0, c7, c10, 4 @ drain WB
139 .type __fa526_setup, #function
141 /* On return of this routine, r0 must carry correct flags for CFG register */
143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
148 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
151 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
154 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
155 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
156 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
158 mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client
159 mcr p15, 0, r0, c3, c0 @ load domain access register
161 mrc p15, 0, r0, c1, c0 @ get control register v4
162 ldr r5, fa526_cr1_clear
164 ldr r5, fa526_cr1_set
167 .size __fa526_setup, . - __fa526_setup
170 * .RVI ZFRS BLDP WCAM
171 * ..11 1001 .111 1101
174 .type fa526_cr1_clear, #object
175 .type fa526_cr1_set, #object
184 * Purpose : Function pointers used to access above functions - all calls
187 .type fa526_processor_functions, #object
188 fa526_processor_functions:
191 .word cpu_fa526_proc_init
192 .word cpu_fa526_proc_fin
193 .word cpu_fa526_reset
194 .word cpu_fa526_do_idle
195 .word cpu_fa526_dcache_clean_area
196 .word cpu_fa526_switch_mm
197 .word cpu_fa526_set_pte_ext
198 .size fa526_processor_functions, . - fa526_processor_functions
202 .type cpu_arch_name, #object
205 .size cpu_arch_name, . - cpu_arch_name
207 .type cpu_elf_name, #object
210 .size cpu_elf_name, . - cpu_elf_name
212 .type cpu_fa526_name, #object
215 .size cpu_fa526_name, . - cpu_fa526_name
219 .section ".proc.info.init", #alloc, #execinstr
221 .type __fa526_proc_info,#object
225 .long PMD_TYPE_SECT | \
226 PMD_SECT_BUFFERABLE | \
227 PMD_SECT_CACHEABLE | \
229 PMD_SECT_AP_WRITE | \
231 .long PMD_TYPE_SECT | \
233 PMD_SECT_AP_WRITE | \
238 .long HWCAP_SWP | HWCAP_HALF
240 .long fa526_processor_functions
244 .size __fa526_proc_info, . - __fa526_proc_info