2 * linux/arch/arm/mm/arm940.S: utility functions for ARM940T
4 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <linux/init.h>
13 #include <asm/assembler.h>
14 #include <asm/hwcap.h>
15 #include <asm/pgtable-hwdef.h>
16 #include <asm/pgtable.h>
17 #include <asm/ptrace.h>
18 #include "proc-macros.S"
20 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
21 #define CACHE_DLINESIZE 16
22 #define CACHE_DSEGMENTS 4
23 #define CACHE_DENTRIES 64
27 * cpu_arm940_proc_init()
28 * cpu_arm940_switch_mm()
30 * These are not required.
32 ENTRY(cpu_arm940_proc_init)
33 ENTRY(cpu_arm940_switch_mm)
37 * cpu_arm940_proc_fin()
39 ENTRY(cpu_arm940_proc_fin)
40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
41 bic r0, r0, #0x00001000 @ i-cache
42 bic r0, r0, #0x00000004 @ d-cache
43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
47 * cpu_arm940_reset(loc)
48 * Params : r0 = address to jump to
49 * Notes : This sets up everything for a reset
51 ENTRY(cpu_arm940_reset)
53 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
54 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
55 mcr p15, 0, ip, c7, c10, 4 @ drain WB
56 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
57 bic ip, ip, #0x00000005 @ .............c.p
58 bic ip, ip, #0x00001000 @ i-cache
59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
63 * cpu_arm940_do_idle()
66 ENTRY(cpu_arm940_do_idle)
67 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
73 * Unconditionally clean and invalidate the entire icache.
75 ENTRY(arm940_flush_icache_all)
77 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
79 ENDPROC(arm940_flush_icache_all)
82 * flush_user_cache_all()
84 ENTRY(arm940_flush_user_cache_all)
88 * flush_kern_cache_all()
90 * Clean and invalidate the entire cache.
92 ENTRY(arm940_flush_kern_cache_all)
97 * flush_user_cache_range(start, end, flags)
99 * There is no efficient way to flush a range of cache entries
100 * in the specified address range. Thus, flushes all.
102 * - start - start address (inclusive)
103 * - end - end address (exclusive)
104 * - flags - vm_flags describing address space
106 ENTRY(arm940_flush_user_cache_range)
108 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
109 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
111 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
112 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
113 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
114 subs r3, r3, #1 << 26
115 bcs 2b @ entries 63 to 0
117 bcs 1b @ segments 3 to 0
120 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
121 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
125 * coherent_kern_range(start, end)
127 * Ensure coherency between the Icache and the Dcache in the
128 * region described by start, end. If you have non-snooping
129 * Harvard caches, you need to implement this function.
131 * - start - virtual start address
132 * - end - virtual end address
134 ENTRY(arm940_coherent_kern_range)
138 * coherent_user_range(start, end)
140 * Ensure coherency between the Icache and the Dcache in the
141 * region described by start, end. If you have non-snooping
142 * Harvard caches, you need to implement this function.
144 * - start - virtual start address
145 * - end - virtual end address
147 ENTRY(arm940_coherent_user_range)
151 * flush_kern_dcache_area(void *addr, size_t size)
153 * Ensure no D cache aliasing occurs, either with itself or
156 * - addr - kernel address
157 * - size - region size
159 ENTRY(arm940_flush_kern_dcache_area)
161 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
162 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
163 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
164 subs r3, r3, #1 << 26
165 bcs 2b @ entries 63 to 0
167 bcs 1b @ segments 7 to 0
168 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 mcr p15, 0, ip, c7, c10, 4 @ drain WB
173 * dma_inv_range(start, end)
175 * There is no efficient way to invalidate a specifid virtual
176 * address range. Thus, invalidates all.
178 * - start - virtual start address
179 * - end - virtual end address
181 arm940_dma_inv_range:
183 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
184 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
185 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
186 subs r3, r3, #1 << 26
187 bcs 2b @ entries 63 to 0
189 bcs 1b @ segments 7 to 0
190 mcr p15, 0, ip, c7, c10, 4 @ drain WB
194 * dma_clean_range(start, end)
196 * There is no efficient way to clean a specifid virtual
197 * address range. Thus, cleans all.
199 * - start - virtual start address
200 * - end - virtual end address
202 arm940_dma_clean_range:
203 ENTRY(cpu_arm940_dcache_clean_area)
205 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
206 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
207 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
208 2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
209 subs r3, r3, #1 << 26
210 bcs 2b @ entries 63 to 0
212 bcs 1b @ segments 7 to 0
214 mcr p15, 0, ip, c7, c10, 4 @ drain WB
218 * dma_flush_range(start, end)
220 * There is no efficient way to clean and invalidate a specifid
221 * virtual address range.
223 * - start - virtual start address
224 * - end - virtual end address
226 ENTRY(arm940_dma_flush_range)
228 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
229 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
231 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
232 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
234 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
236 subs r3, r3, #1 << 26
237 bcs 2b @ entries 63 to 0
239 bcs 1b @ segments 7 to 0
240 mcr p15, 0, ip, c7, c10, 4 @ drain WB
244 * dma_map_area(start, size, dir)
245 * - start - kernel virtual start address
246 * - size - size of region
247 * - dir - DMA direction
249 ENTRY(arm940_dma_map_area)
251 cmp r2, #DMA_TO_DEVICE
252 beq arm940_dma_clean_range
253 bcs arm940_dma_inv_range
254 b arm940_dma_flush_range
255 ENDPROC(arm940_dma_map_area)
258 * dma_unmap_area(start, size, dir)
259 * - start - kernel virtual start address
260 * - size - size of region
261 * - dir - DMA direction
263 ENTRY(arm940_dma_unmap_area)
265 ENDPROC(arm940_dma_unmap_area)
267 ENTRY(arm940_cache_fns)
268 .long arm940_flush_icache_all
269 .long arm940_flush_kern_cache_all
270 .long arm940_flush_user_cache_all
271 .long arm940_flush_user_cache_range
272 .long arm940_coherent_kern_range
273 .long arm940_coherent_user_range
274 .long arm940_flush_kern_dcache_area
275 .long arm940_dma_map_area
276 .long arm940_dma_unmap_area
277 .long arm940_dma_flush_range
281 .type __arm940_setup, #function
284 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
285 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
288 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
289 mcr p15, 0, r0, c6, c4, 0
290 mcr p15, 0, r0, c6, c5, 0
291 mcr p15, 0, r0, c6, c6, 0
292 mcr p15, 0, r0, c6, c7, 0
294 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
295 mcr p15, 0, r0, c6, c4, 1
296 mcr p15, 0, r0, c6, c5, 1
297 mcr p15, 0, r0, c6, c6, 1
298 mcr p15, 0, r0, c6, c7, 1
300 mov r0, #0x0000003F @ base = 0, size = 4GB
301 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
302 mcr p15, 0, r0, c6, c0, 1
304 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
305 ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
306 mov r2, #10 @ 11 is the minimum (4KB)
307 1: add r2, r2, #1 @ area size *= 2
309 bne 1b @ count not zero r-shift
310 orr r0, r0, r2, lsl #1 @ the area register value
311 orr r0, r0, #1 @ set enable bit
312 mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
313 mcr p15, 0, r0, c6, c1, 1
315 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
316 ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
317 mov r2, #10 @ 11 is the minimum (4KB)
318 1: add r2, r2, #1 @ area size *= 2
320 bne 1b @ count not zero r-shift
321 orr r0, r0, r2, lsl #1 @ the area register value
322 orr r0, r0, #1 @ set enable bit
323 mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
324 mcr p15, 0, r0, c6, c2, 1
327 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
328 mcr p15, 0, r0, c2, c0, 1
329 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
330 mov r0, #0x00 @ disable whole write buffer
332 mov r0, #0x02 @ Region 1 write bufferred
334 mcr p15, 0, r0, c3, c0, 0
337 sub r0, r0, #1 @ r0 = 0xffff
338 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
339 mcr p15, 0, r0, c5, c0, 1
341 mrc p15, 0, r0, c1, c0 @ get control register
342 orr r0, r0, #0x00001000 @ I-cache
343 orr r0, r0, #0x00000005 @ MPU/D-cache
347 .size __arm940_setup, . - __arm940_setup
352 * Purpose : Function pointers used to access above functions - all calls
355 .type arm940_processor_functions, #object
356 ENTRY(arm940_processor_functions)
357 .word nommu_early_abort
359 .word cpu_arm940_proc_init
360 .word cpu_arm940_proc_fin
361 .word cpu_arm940_reset
362 .word cpu_arm940_do_idle
363 .word cpu_arm940_dcache_clean_area
364 .word cpu_arm940_switch_mm
365 .word 0 @ cpu_*_set_pte
366 .size arm940_processor_functions, . - arm940_processor_functions
370 .type cpu_arch_name, #object
373 .size cpu_arch_name, . - cpu_arch_name
375 .type cpu_elf_name, #object
378 .size cpu_elf_name, . - cpu_elf_name
380 .type cpu_arm940_name, #object
383 .size cpu_arm940_name, . - cpu_arm940_name
387 .section ".proc.info.init", #alloc, #execinstr
389 .type __arm940_proc_info,#object
397 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
398 .long cpu_arm940_name
399 .long arm940_processor_functions
402 .long arm940_cache_fns
403 .size __arm940_proc_info, . - __arm940_proc_info