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x86, cpu: Call verify_cpu during 32bit CPU startup
[linux-2.6.git] / arch / arm / mach-mx3 / mach-pcm043.c
blob4e1de87995d48da64c76bb558abf3bbab815919f
1 /*
2 * Copyright (C) 2009 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/types.h>
16 #include <linux/init.h>
17
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20 #include <linux/mtd/plat-ram.h>
21 #include <linux/memory.h>
22 #include <linux/gpio.h>
23 #include <linux/smc911x.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c/at24.h>
28 #include <linux/usb/otg.h>
29 #include <linux/usb/ulpi.h>
30 #include <linux/fsl_devices.h>
31
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/time.h>
35 #include <asm/mach/map.h>
36
37 #include <mach/hardware.h>
38 #include <mach/common.h>
39 #include <mach/iomux-mx35.h>
40 #include <mach/ipu.h>
41 #include <mach/mx3fb.h>
42 #include <mach/mxc_ehci.h>
43 #include <mach/ulpi.h>
44 #include <mach/audmux.h>
45
46 #include "devices-imx35.h"
47 #include "devices.h"
48
49 static const struct fb_videomode fb_modedb[] = {
50 {
51 /* 240x320 @ 60 Hz */
52 .name = "Sharp-LQ035Q7",
53 .refresh = 60,
54 .xres = 240,
55 .yres = 320,
56 .pixclock = 185925,
57 .left_margin = 9,
58 .right_margin = 16,
59 .upper_margin = 7,
60 .lower_margin = 9,
61 .hsync_len = 1,
62 .vsync_len = 1,
63 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
64 .vmode = FB_VMODE_NONINTERLACED,
65 .flag = 0,
66 }, {
67 /* 240x320 @ 60 Hz */
68 .name = "TX090",
69 .refresh = 60,
70 .xres = 240,
71 .yres = 320,
72 .pixclock = 38255,
73 .left_margin = 144,
74 .right_margin = 0,
75 .upper_margin = 7,
76 .lower_margin = 40,
77 .hsync_len = 96,
78 .vsync_len = 1,
79 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
80 .vmode = FB_VMODE_NONINTERLACED,
81 .flag = 0,
82 },
83 };
84
85 static struct ipu_platform_data mx3_ipu_data = {
86 .irq_base = MXC_IPU_IRQ_START,
87 };
88
89 static struct mx3fb_platform_data mx3fb_pdata = {
90 .dma_dev = &mx3_ipu.dev,
91 .name = "Sharp-LQ035Q7",
92 .mode = fb_modedb,
93 .num_modes = ARRAY_SIZE(fb_modedb),
94 };
95
96 static struct physmap_flash_data pcm043_flash_data = {
97 .width = 2,
98 };
99
100 static struct resource pcm043_flash_resource = {
101 .start = 0xa0000000,
102 .end = 0xa1ffffff,
103 .flags = IORESOURCE_MEM,
104 };
105
106 static struct platform_device pcm043_flash = {
107 .name = "physmap-flash",
108 .id = 0,
109 .dev = {
110 .platform_data = &pcm043_flash_data,
111 },
112 .resource = &pcm043_flash_resource,
113 .num_resources = 1,
114 };
115
116 static const struct imxuart_platform_data uart_pdata __initconst = {
117 .flags = IMXUART_HAVE_RTSCTS,
118 };
119
120 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
121 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
122 .bitrate = 50000,
123 };
124
125 static struct at24_platform_data board_eeprom = {
126 .byte_len = 4096,
127 .page_size = 32,
128 .flags = AT24_FLAG_ADDR16,
129 };
130
131 static struct i2c_board_info pcm043_i2c_devices[] = {
132 {
133 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
134 .platform_data = &board_eeprom,
135 }, {
136 I2C_BOARD_INFO("pcf8563", 0x51),
137 }
138 };
139 #endif
140
141 static struct platform_device *devices[] __initdata = {
142 &pcm043_flash,
143 &imx_wdt_device0,
144 };
145
146 static struct pad_desc pcm043_pads[] = {
147 /* UART1 */
148 MX35_PAD_CTS1__UART1_CTS,
149 MX35_PAD_RTS1__UART1_RTS,
150 MX35_PAD_TXD1__UART1_TXD_MUX,
151 MX35_PAD_RXD1__UART1_RXD_MUX,
152 /* UART2 */
153 MX35_PAD_CTS2__UART2_CTS,
154 MX35_PAD_RTS2__UART2_RTS,
155 MX35_PAD_TXD2__UART2_TXD_MUX,
156 MX35_PAD_RXD2__UART2_RXD_MUX,
157 /* FEC */
158 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
159 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
160 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
161 MX35_PAD_FEC_COL__FEC_COL,
162 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
163 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
164 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
165 MX35_PAD_FEC_MDC__FEC_MDC,
166 MX35_PAD_FEC_MDIO__FEC_MDIO,
167 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
168 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
169 MX35_PAD_FEC_CRS__FEC_CRS,
170 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
171 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
172 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
173 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
174 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
175 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
176 /* I2C1 */
177 MX35_PAD_I2C1_CLK__I2C1_SCL,
178 MX35_PAD_I2C1_DAT__I2C1_SDA,
179 /* Display */
180 MX35_PAD_LD0__IPU_DISPB_DAT_0,
181 MX35_PAD_LD1__IPU_DISPB_DAT_1,
182 MX35_PAD_LD2__IPU_DISPB_DAT_2,
183 MX35_PAD_LD3__IPU_DISPB_DAT_3,
184 MX35_PAD_LD4__IPU_DISPB_DAT_4,
185 MX35_PAD_LD5__IPU_DISPB_DAT_5,
186 MX35_PAD_LD6__IPU_DISPB_DAT_6,
187 MX35_PAD_LD7__IPU_DISPB_DAT_7,
188 MX35_PAD_LD8__IPU_DISPB_DAT_8,
189 MX35_PAD_LD9__IPU_DISPB_DAT_9,
190 MX35_PAD_LD10__IPU_DISPB_DAT_10,
191 MX35_PAD_LD11__IPU_DISPB_DAT_11,
192 MX35_PAD_LD12__IPU_DISPB_DAT_12,
193 MX35_PAD_LD13__IPU_DISPB_DAT_13,
194 MX35_PAD_LD14__IPU_DISPB_DAT_14,
195 MX35_PAD_LD15__IPU_DISPB_DAT_15,
196 MX35_PAD_LD16__IPU_DISPB_DAT_16,
197 MX35_PAD_LD17__IPU_DISPB_DAT_17,
198 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
199 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
200 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
201 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
202 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
203 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
204 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
205 /* gpio */
206 MX35_PAD_ATA_CS0__GPIO2_6,
207 /* USB host */
208 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
209 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
210 /* SSI */
211 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
212 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
213 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
214 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
215 /* CAN2 */
216 MX35_PAD_TX5_RX0__CAN2_TXCAN,
217 MX35_PAD_TX4_RX1__CAN2_RXCAN,
218 /* esdhc */
219 MX35_PAD_SD1_CMD__ESDHC1_CMD,
220 MX35_PAD_SD1_CLK__ESDHC1_CLK,
221 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
222 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
223 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
224 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
225 };
226
227 #define AC97_GPIO_TXFS (1 * 32 + 31)
228 #define AC97_GPIO_TXD (1 * 32 + 28)
229 #define AC97_GPIO_RESET (1 * 32 + 0)
230
231 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
232 {
233 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
234 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
235 int ret;
236
237 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
238 if (ret) {
239 printk("failed to get GPIO_TXFS: %d\n", ret);
240 return;
241 }
242
243 mxc_iomux_v3_setup_pad(&txfs_gpio);
244
245 /* warm reset */
246 gpio_direction_output(AC97_GPIO_TXFS, 1);
247 udelay(2);
248 gpio_set_value(AC97_GPIO_TXFS, 0);
249
250 gpio_free(AC97_GPIO_TXFS);
251 mxc_iomux_v3_setup_pad(&txfs);
252 }
253
254 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
255 {
256 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
257 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
258 struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
259 struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
260 struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
261 int ret;
262
263 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
264 if (ret)
265 goto err1;
266
267 ret = gpio_request(AC97_GPIO_TXD, "SSI");
268 if (ret)
269 goto err2;
270
271 ret = gpio_request(AC97_GPIO_RESET, "SSI");
272 if (ret)
273 goto err3;
274
275 mxc_iomux_v3_setup_pad(&txfs_gpio);
276 mxc_iomux_v3_setup_pad(&txd_gpio);
277 mxc_iomux_v3_setup_pad(&reset_gpio);
278
279 gpio_direction_output(AC97_GPIO_TXFS, 0);
280 gpio_direction_output(AC97_GPIO_TXD, 0);
281
282 /* cold reset */
283 gpio_direction_output(AC97_GPIO_RESET, 0);
284 udelay(10);
285 gpio_direction_output(AC97_GPIO_RESET, 1);
286
287 mxc_iomux_v3_setup_pad(&txd);
288 mxc_iomux_v3_setup_pad(&txfs);
289
290 gpio_free(AC97_GPIO_RESET);
291 err3:
292 gpio_free(AC97_GPIO_TXD);
293 err2:
294 gpio_free(AC97_GPIO_TXFS);
295 err1:
296 if (ret)
297 printk("%s failed with %d\n", __func__, ret);
298 mdelay(1);
299 }
300
301 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
302 .ac97_reset = pcm043_ac97_cold_reset,
303 .ac97_warm_reset = pcm043_ac97_warm_reset,
304 .flags = IMX_SSI_USE_AC97,
305 };
306
307 static const struct mxc_nand_platform_data
308 pcm037_nand_board_info __initconst = {
309 .width = 1,
310 .hw_ecc = 1,
311 };
312
313 #if defined(CONFIG_USB_ULPI)
314 static struct mxc_usbh_platform_data otg_pdata = {
315 .portsc = MXC_EHCI_MODE_UTMI,
316 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
317 };
318
319 static struct mxc_usbh_platform_data usbh1_pdata = {
320 .portsc = MXC_EHCI_MODE_SERIAL,
321 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
322 MXC_EHCI_IPPUE_DOWN,
323 };
324 #endif
325
326 static struct fsl_usb2_platform_data otg_device_pdata = {
327 .operating_mode = FSL_USB2_DR_DEVICE,
328 .phy_mode = FSL_USB2_PHY_UTMI,
329 };
330
331 static int otg_mode_host;
332
333 static int __init pcm043_otg_mode(char *options)
334 {
335 if (!strcmp(options, "host"))
336 otg_mode_host = 1;
337 else if (!strcmp(options, "device"))
338 otg_mode_host = 0;
339 else
340 pr_info("otg_mode neither \"host\" nor \"device\". "
341 "Defaulting to device\n");
342 return 0;
343 }
344 __setup("otg_mode=", pcm043_otg_mode);
345
346 /*
347 * Board specific initialization.
348 */
349 static void __init mxc_board_init(void)
350 {
351 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
352
353 mxc_audmux_v2_configure_port(3,
354 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
355 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
356 MXC_AUDMUX_V2_PTCR_TFSDIR,
357 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
358
359 mxc_audmux_v2_configure_port(0,
360 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
361 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
362 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
363 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
364
365 imx35_add_fec(NULL);
366 platform_add_devices(devices, ARRAY_SIZE(devices));
367
368 imx35_add_imx_uart0(&uart_pdata);
369 imx35_add_mxc_nand(&pcm037_nand_board_info);
370 imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
371
372 imx35_add_imx_uart1(&uart_pdata);
373
374 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
375 i2c_register_board_info(0, pcm043_i2c_devices,
376 ARRAY_SIZE(pcm043_i2c_devices));
377
378 imx35_add_imx_i2c0(&pcm043_i2c0_data);
379 #endif
380
381 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
382 mxc_register_device(&mx3_fb, &mx3fb_pdata);
383
384 #if defined(CONFIG_USB_ULPI)
385 if (otg_mode_host) {
386 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
387 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
388
389 mxc_register_device(&mxc_otg_host, &otg_pdata);
390 }
391
392 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
393 #endif
394 if (!otg_mode_host)
395 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
396
397 imx35_add_flexcan1(NULL);
398 imx35_add_esdhc(0, NULL);
399 }
400
401 static void __init pcm043_timer_init(void)
402 {
403 mx35_clocks_init();
404 }
405
406 struct sys_timer pcm043_timer = {
407 .init = pcm043_timer_init,
408 };
409
410 MACHINE_START(PCM043, "Phytec Phycore pcm043")
411 /* Maintainer: Pengutronix */
412 .boot_params = MX3x_PHYS_OFFSET + 0x100,
413 .map_io = mx35_map_io,
414 .init_irq = mx35_init_irq,
415 .init_machine = mxc_board_init,
416 .timer = &pcm043_timer,
417 MACHINE_END
418
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