x86, cpu: Call verify_cpu during 32bit CPU startup
[linux-2.6.git] / arch / arm / mach-mx3 / devices.c
blobd4da9496089a6ea08eba3cd86714822f811475c5
1 /*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/gpio.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <mach/common.h>
28 #include <mach/mx3_camera.h>
30 #include "devices.h"
32 /* GPIO port description */
33 static struct mxc_gpio_port imx_gpio_ports[] = {
35 .chip.label = "gpio-0",
36 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
37 .irq = MXC_INT_GPIO1,
38 .virtual_irq_start = MXC_GPIO_IRQ_START,
39 }, {
40 .chip.label = "gpio-1",
41 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
42 .irq = MXC_INT_GPIO2,
43 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
44 }, {
45 .chip.label = "gpio-2",
46 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
47 .irq = MXC_INT_GPIO3,
48 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
52 int __init imx3x_register_gpios(void)
54 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
57 static struct resource mxc_w1_master_resources[] = {
59 .start = OWIRE_BASE_ADDR,
60 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
61 .flags = IORESOURCE_MEM,
65 struct platform_device mxc_w1_master_device = {
66 .name = "mxc_w1",
67 .id = 0,
68 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
69 .resource = mxc_w1_master_resources,
72 #ifdef CONFIG_ARCH_MX31
73 static struct resource mxcsdhc0_resources[] = {
75 .start = MX31_MMC_SDHC1_BASE_ADDR,
76 .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX31_INT_MMC_SDHC1,
80 .end = MX31_INT_MMC_SDHC1,
81 .flags = IORESOURCE_IRQ,
85 static struct resource mxcsdhc1_resources[] = {
87 .start = MX31_MMC_SDHC2_BASE_ADDR,
88 .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .start = MX31_INT_MMC_SDHC2,
92 .end = MX31_INT_MMC_SDHC2,
93 .flags = IORESOURCE_IRQ,
97 struct platform_device mxcsdhc_device0 = {
98 .name = "mxc-mmc",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
101 .resource = mxcsdhc0_resources,
104 struct platform_device mxcsdhc_device1 = {
105 .name = "mxc-mmc",
106 .id = 1,
107 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
108 .resource = mxcsdhc1_resources,
111 static struct resource rnga_resources[] = {
113 .start = RNGA_BASE_ADDR,
114 .end = RNGA_BASE_ADDR + 0x28,
115 .flags = IORESOURCE_MEM,
119 struct platform_device mxc_rnga_device = {
120 .name = "mxc_rnga",
121 .id = -1,
122 .num_resources = 1,
123 .resource = rnga_resources,
125 #endif /* CONFIG_ARCH_MX31 */
127 /* i.MX31 Image Processing Unit */
129 /* The resource order is important! */
130 static struct resource mx3_ipu_rsrc[] = {
132 .start = IPU_CTRL_BASE_ADDR,
133 .end = IPU_CTRL_BASE_ADDR + 0x5F,
134 .flags = IORESOURCE_MEM,
135 }, {
136 .start = IPU_CTRL_BASE_ADDR + 0x88,
137 .end = IPU_CTRL_BASE_ADDR + 0xB3,
138 .flags = IORESOURCE_MEM,
139 }, {
140 .start = MXC_INT_IPU_SYN,
141 .end = MXC_INT_IPU_SYN,
142 .flags = IORESOURCE_IRQ,
143 }, {
144 .start = MXC_INT_IPU_ERR,
145 .end = MXC_INT_IPU_ERR,
146 .flags = IORESOURCE_IRQ,
150 struct platform_device mx3_ipu = {
151 .name = "ipu-core",
152 .id = -1,
153 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
154 .resource = mx3_ipu_rsrc,
157 static struct resource fb_resources[] = {
159 .start = IPU_CTRL_BASE_ADDR + 0xB4,
160 .end = IPU_CTRL_BASE_ADDR + 0x1BF,
161 .flags = IORESOURCE_MEM,
165 struct platform_device mx3_fb = {
166 .name = "mx3_sdc_fb",
167 .id = -1,
168 .num_resources = ARRAY_SIZE(fb_resources),
169 .resource = fb_resources,
170 .dev = {
171 .coherent_dma_mask = DMA_BIT_MASK(32),
175 static struct resource camera_resources[] = {
177 .start = IPU_CTRL_BASE_ADDR + 0x60,
178 .end = IPU_CTRL_BASE_ADDR + 0x87,
179 .flags = IORESOURCE_MEM,
183 struct platform_device mx3_camera = {
184 .name = "mx3-camera",
185 .id = 0,
186 .num_resources = ARRAY_SIZE(camera_resources),
187 .resource = camera_resources,
188 .dev = {
189 .coherent_dma_mask = DMA_BIT_MASK(32),
193 static struct resource otg_resources[] = {
195 .start = MX31_OTG_BASE_ADDR,
196 .end = MX31_OTG_BASE_ADDR + 0x1ff,
197 .flags = IORESOURCE_MEM,
198 }, {
199 .start = MXC_INT_USB3,
200 .end = MXC_INT_USB3,
201 .flags = IORESOURCE_IRQ,
205 static u64 otg_dmamask = DMA_BIT_MASK(32);
207 /* OTG gadget device */
208 struct platform_device mxc_otg_udc_device = {
209 .name = "fsl-usb2-udc",
210 .id = -1,
211 .dev = {
212 .dma_mask = &otg_dmamask,
213 .coherent_dma_mask = DMA_BIT_MASK(32),
215 .resource = otg_resources,
216 .num_resources = ARRAY_SIZE(otg_resources),
219 /* OTG host */
220 struct platform_device mxc_otg_host = {
221 .name = "mxc-ehci",
222 .id = 0,
223 .dev = {
224 .coherent_dma_mask = 0xffffffff,
225 .dma_mask = &otg_dmamask,
227 .resource = otg_resources,
228 .num_resources = ARRAY_SIZE(otg_resources),
231 /* USB host 1 */
233 static u64 usbh1_dmamask = ~(u32)0;
235 static struct resource mxc_usbh1_resources[] = {
237 .start = MX31_OTG_BASE_ADDR + 0x200,
238 .end = MX31_OTG_BASE_ADDR + 0x3ff,
239 .flags = IORESOURCE_MEM,
240 }, {
241 .start = MXC_INT_USB1,
242 .end = MXC_INT_USB1,
243 .flags = IORESOURCE_IRQ,
247 struct platform_device mxc_usbh1 = {
248 .name = "mxc-ehci",
249 .id = 1,
250 .dev = {
251 .coherent_dma_mask = 0xffffffff,
252 .dma_mask = &usbh1_dmamask,
254 .resource = mxc_usbh1_resources,
255 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
258 /* USB host 2 */
259 static u64 usbh2_dmamask = ~(u32)0;
261 static struct resource mxc_usbh2_resources[] = {
263 .start = MX31_OTG_BASE_ADDR + 0x400,
264 .end = MX31_OTG_BASE_ADDR + 0x5ff,
265 .flags = IORESOURCE_MEM,
266 }, {
267 .start = MXC_INT_USB2,
268 .end = MXC_INT_USB2,
269 .flags = IORESOURCE_IRQ,
273 struct platform_device mxc_usbh2 = {
274 .name = "mxc-ehci",
275 .id = 2,
276 .dev = {
277 .coherent_dma_mask = 0xffffffff,
278 .dma_mask = &usbh2_dmamask,
280 .resource = mxc_usbh2_resources,
281 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
284 static struct resource imx_wdt_resources[] = {
286 .flags = IORESOURCE_MEM,
290 struct platform_device imx_wdt_device0 = {
291 .name = "imx2-wdt",
292 .id = 0,
293 .num_resources = ARRAY_SIZE(imx_wdt_resources),
294 .resource = imx_wdt_resources,
297 static struct resource imx_rtc_resources[] = {
299 .start = MX31_RTC_BASE_ADDR,
300 .end = MX31_RTC_BASE_ADDR + 0x3fff,
301 .flags = IORESOURCE_MEM,
304 .start = MX31_INT_RTC,
305 .flags = IORESOURCE_IRQ,
309 struct platform_device imx_rtc_device0 = {
310 .name = "mxc_rtc",
311 .id = -1,
312 .num_resources = ARRAY_SIZE(imx_rtc_resources),
313 .resource = imx_rtc_resources,
316 static struct resource imx_kpp_resources[] = {
318 .start = MX3x_KPP_BASE_ADDR,
319 .end = MX3x_KPP_BASE_ADDR + 0xf,
320 .flags = IORESOURCE_MEM
321 }, {
322 .start = MX3x_INT_KPP,
323 .end = MX3x_INT_KPP,
324 .flags = IORESOURCE_IRQ,
328 struct platform_device imx_kpp_device = {
329 .name = "imx-keypad",
330 .id = -1,
331 .num_resources = ARRAY_SIZE(imx_kpp_resources),
332 .resource = imx_kpp_resources,
335 static int __init mx3_devices_init(void)
337 #if defined(CONFIG_ARCH_MX31)
338 if (cpu_is_mx31()) {
339 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
340 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
341 mxc_register_device(&mxc_rnga_device, NULL);
343 #endif
344 #if defined(CONFIG_ARCH_MX35)
345 if (cpu_is_mx35()) {
346 otg_resources[0].start = MX35_OTG_BASE_ADDR;
347 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
348 otg_resources[1].start = MXC_INT_USBOTG;
349 otg_resources[1].end = MXC_INT_USBOTG;
350 mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
351 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
352 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
353 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
354 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
355 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
357 #endif
359 return 0;
362 subsys_initcall(mx3_devices_init);