2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/clk.h>
25 #include <asm/clkdev.h>
27 #include <mach/clock.h>
28 #include <mach/hardware.h>
29 #include <mach/common.h>
31 #define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
40 #define CCM_MPCTL 0x1C
41 #define CCM_PPCTL 0x20
49 #ifdef HAVE_SET_RATE_SUPPORT
50 static void calc_dividers(u32 div
, u32
*pre
, u32
*post
, u32 maxpost
)
52 u32 min_pre
, temp_pre
, old_err
, err
;
54 min_pre
= (div
- 1) / maxpost
+ 1;
57 for (temp_pre
= 8; temp_pre
>= min_pre
; temp_pre
--) {
58 if (div
> (temp_pre
* maxpost
))
61 if (div
< (temp_pre
* temp_pre
))
79 *post
= (div
+ *pre
- 1) / *pre
;
82 /* get the best values for a 3-bit divider combined with a 6-bit divider */
83 static void calc_dividers_3_6(u32 div
, u32
*pre
, u32
*post
)
88 } else if (div
>= 64) {
89 calc_dividers(div
, pre
, post
, 64);
90 } else if (div
<= 8) {
99 /* get the best values for two cascaded 3-bit dividers */
100 static void calc_dividers_3_3(u32 div
, u32
*pre
, u32
*post
)
104 } else if (div
> 8) {
105 calc_dividers(div
, pre
, post
, 8);
113 static unsigned long get_rate_mpll(void)
115 ulong mpctl
= __raw_readl(CCM_BASE
+ CCM_MPCTL
);
117 return mxc_decode_pll(mpctl
, 24000000);
120 static unsigned long get_rate_ppll(void)
122 ulong ppctl
= __raw_readl(CCM_BASE
+ CCM_PPCTL
);
124 return mxc_decode_pll(ppctl
, 24000000);
128 unsigned char arm
, ahb
, sel
;
131 static struct arm_ahb_div clk_consumer
[] = {
132 { .arm
= 1, .ahb
= 4, .sel
= 0},
133 { .arm
= 1, .ahb
= 3, .sel
= 1},
134 { .arm
= 2, .ahb
= 2, .sel
= 0},
135 { .arm
= 0, .ahb
= 0, .sel
= 0},
136 { .arm
= 0, .ahb
= 0, .sel
= 0},
137 { .arm
= 0, .ahb
= 0, .sel
= 0},
138 { .arm
= 4, .ahb
= 1, .sel
= 0},
139 { .arm
= 1, .ahb
= 5, .sel
= 0},
140 { .arm
= 1, .ahb
= 8, .sel
= 0},
141 { .arm
= 1, .ahb
= 6, .sel
= 1},
142 { .arm
= 2, .ahb
= 4, .sel
= 0},
143 { .arm
= 0, .ahb
= 0, .sel
= 0},
144 { .arm
= 0, .ahb
= 0, .sel
= 0},
145 { .arm
= 0, .ahb
= 0, .sel
= 0},
146 { .arm
= 4, .ahb
= 2, .sel
= 0},
147 { .arm
= 0, .ahb
= 0, .sel
= 0},
150 static unsigned long get_rate_arm(void)
152 unsigned long pdr0
= __raw_readl(CCM_BASE
+ CCM_PDR0
);
153 struct arm_ahb_div
*aad
;
154 unsigned long fref
= get_rate_mpll();
156 aad
= &clk_consumer
[(pdr0
>> 16) & 0xf];
160 return fref
/ aad
->arm
;
163 static unsigned long get_rate_ahb(struct clk
*clk
)
165 unsigned long pdr0
= __raw_readl(CCM_BASE
+ CCM_PDR0
);
166 struct arm_ahb_div
*aad
;
167 unsigned long fref
= get_rate_arm();
169 aad
= &clk_consumer
[(pdr0
>> 16) & 0xf];
171 return fref
/ aad
->ahb
;
174 static unsigned long get_rate_ipg(struct clk
*clk
)
176 return get_rate_ahb(NULL
) >> 1;
179 static unsigned long get_rate_uart(struct clk
*clk
)
181 unsigned long pdr3
= __raw_readl(CCM_BASE
+ CCM_PDR3
);
182 unsigned long pdr4
= __raw_readl(CCM_BASE
+ CCM_PDR4
);
183 unsigned long div
= ((pdr4
>> 10) & 0x3f) + 1;
185 if (pdr3
& (1 << 14))
186 return get_rate_arm() / div
;
188 return get_rate_ppll() / div
;
191 static unsigned long get_rate_sdhc(struct clk
*clk
)
193 unsigned long pdr3
= __raw_readl(CCM_BASE
+ CCM_PDR3
);
194 unsigned long div
, rate
;
197 rate
= get_rate_arm();
199 rate
= get_rate_ppll();
207 div
= (pdr3
>> 8) & 0x3f;
210 div
= (pdr3
>> 16) & 0x3f;
214 return rate
/ (div
+ 1);
217 static unsigned long get_rate_mshc(struct clk
*clk
)
219 unsigned long pdr1
= __raw_readl(CCM_BASE
+ CCM_PDR1
);
220 unsigned long div1
, div2
, rate
;
223 rate
= get_rate_arm();
225 rate
= get_rate_ppll();
227 div1
= (pdr1
>> 29) & 0x7;
228 div2
= (pdr1
>> 22) & 0x3f;
230 return rate
/ ((div1
+ 1) * (div2
+ 1));
233 static unsigned long get_rate_ssi(struct clk
*clk
)
235 unsigned long pdr2
= __raw_readl(CCM_BASE
+ CCM_PDR2
);
236 unsigned long div1
, div2
, rate
;
239 rate
= get_rate_arm();
241 rate
= get_rate_ppll();
247 div2
= (pdr2
>> 24) & 0x7;
250 div1
= (pdr2
>> 8) & 0x3f;
251 div2
= (pdr2
>> 27) & 0x7;
255 return rate
/ ((div1
+ 1) * (div2
+ 1));
258 static unsigned long get_rate_csi(struct clk
*clk
)
260 unsigned long pdr2
= __raw_readl(CCM_BASE
+ CCM_PDR2
);
264 rate
= get_rate_arm();
266 rate
= get_rate_ppll();
268 return rate
/ (((pdr2
>> 16) & 0x3f) + 1);
271 static unsigned long get_rate_otg(struct clk
*clk
)
273 unsigned long pdr4
= __raw_readl(CCM_BASE
+ CCM_PDR4
);
277 rate
= get_rate_arm();
279 rate
= get_rate_ppll();
281 return rate
/ (((pdr4
>> 22) & 0x3f) + 1);
284 static unsigned long get_rate_ipg_per(struct clk
*clk
)
286 unsigned long pdr0
= __raw_readl(CCM_BASE
+ CCM_PDR0
);
287 unsigned long pdr4
= __raw_readl(CCM_BASE
+ CCM_PDR4
);
290 if (pdr0
& (1 << 26)) {
291 div
= (pdr4
>> 16) & 0x3f;
292 return get_rate_arm() / (div
+ 1);
294 div
= (pdr0
>> 12) & 0x7;
295 return get_rate_ahb(NULL
) / (div
+ 1);
299 static unsigned long get_rate_hsp(struct clk
*clk
)
301 unsigned long hsp_podf
= (__raw_readl(CCM_BASE
+ CCM_PDR0
) >> 20) & 0x03;
302 unsigned long fref
= get_rate_mpll();
304 if (fref
> 400 * 1000 * 1000) {
326 static int clk_cgr_enable(struct clk
*clk
)
330 reg
= __raw_readl(clk
->enable_reg
);
331 reg
|= 3 << clk
->enable_shift
;
332 __raw_writel(reg
, clk
->enable_reg
);
337 static void clk_cgr_disable(struct clk
*clk
)
341 reg
= __raw_readl(clk
->enable_reg
);
342 reg
&= ~(3 << clk
->enable_shift
);
343 __raw_writel(reg
, clk
->enable_reg
);
346 #define DEFINE_CLOCK(name, i, er, es, gr, sr) \
347 static struct clk name = { \
349 .enable_reg = CCM_BASE + er, \
350 .enable_shift = es, \
353 .enable = clk_cgr_enable, \
354 .disable = clk_cgr_disable, \
357 DEFINE_CLOCK(asrc_clk
, 0, CCM_CGR0
, 0, NULL
, NULL
);
358 DEFINE_CLOCK(ata_clk
, 0, CCM_CGR0
, 2, get_rate_ipg
, NULL
);
359 /* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
360 DEFINE_CLOCK(can1_clk
, 0, CCM_CGR0
, 6, get_rate_ipg
, NULL
);
361 DEFINE_CLOCK(can2_clk
, 1, CCM_CGR0
, 8, get_rate_ipg
, NULL
);
362 DEFINE_CLOCK(cspi1_clk
, 0, CCM_CGR0
, 10, get_rate_ipg
, NULL
);
363 DEFINE_CLOCK(cspi2_clk
, 1, CCM_CGR0
, 12, get_rate_ipg
, NULL
);
364 DEFINE_CLOCK(ect_clk
, 0, CCM_CGR0
, 14, get_rate_ipg
, NULL
);
365 DEFINE_CLOCK(edio_clk
, 0, CCM_CGR0
, 16, NULL
, NULL
);
366 DEFINE_CLOCK(emi_clk
, 0, CCM_CGR0
, 18, get_rate_ipg
, NULL
);
367 DEFINE_CLOCK(epit1_clk
, 0, CCM_CGR0
, 20, get_rate_ipg
, NULL
);
368 DEFINE_CLOCK(epit2_clk
, 1, CCM_CGR0
, 22, get_rate_ipg
, NULL
);
369 DEFINE_CLOCK(esai_clk
, 0, CCM_CGR0
, 24, NULL
, NULL
);
370 DEFINE_CLOCK(esdhc1_clk
, 0, CCM_CGR0
, 26, get_rate_sdhc
, NULL
);
371 DEFINE_CLOCK(esdhc2_clk
, 1, CCM_CGR0
, 28, get_rate_sdhc
, NULL
);
372 DEFINE_CLOCK(esdhc3_clk
, 2, CCM_CGR0
, 30, get_rate_sdhc
, NULL
);
374 DEFINE_CLOCK(fec_clk
, 0, CCM_CGR1
, 0, get_rate_ipg
, NULL
);
375 DEFINE_CLOCK(gpio1_clk
, 0, CCM_CGR1
, 2, NULL
, NULL
);
376 DEFINE_CLOCK(gpio2_clk
, 1, CCM_CGR1
, 4, NULL
, NULL
);
377 DEFINE_CLOCK(gpio3_clk
, 2, CCM_CGR1
, 6, NULL
, NULL
);
378 DEFINE_CLOCK(gpt_clk
, 0, CCM_CGR1
, 8, get_rate_ipg
, NULL
);
379 DEFINE_CLOCK(i2c1_clk
, 0, CCM_CGR1
, 10, get_rate_ipg_per
, NULL
);
380 DEFINE_CLOCK(i2c2_clk
, 1, CCM_CGR1
, 12, get_rate_ipg_per
, NULL
);
381 DEFINE_CLOCK(i2c3_clk
, 2, CCM_CGR1
, 14, get_rate_ipg_per
, NULL
);
382 DEFINE_CLOCK(iomuxc_clk
, 0, CCM_CGR1
, 16, NULL
, NULL
);
383 DEFINE_CLOCK(ipu_clk
, 0, CCM_CGR1
, 18, get_rate_hsp
, NULL
);
384 DEFINE_CLOCK(kpp_clk
, 0, CCM_CGR1
, 20, get_rate_ipg
, NULL
);
385 DEFINE_CLOCK(mlb_clk
, 0, CCM_CGR1
, 22, get_rate_ahb
, NULL
);
386 DEFINE_CLOCK(mshc_clk
, 0, CCM_CGR1
, 24, get_rate_mshc
, NULL
);
387 DEFINE_CLOCK(owire_clk
, 0, CCM_CGR1
, 26, get_rate_ipg_per
, NULL
);
388 DEFINE_CLOCK(pwm_clk
, 0, CCM_CGR1
, 28, get_rate_ipg_per
, NULL
);
389 DEFINE_CLOCK(rngc_clk
, 0, CCM_CGR1
, 30, get_rate_ipg
, NULL
);
391 DEFINE_CLOCK(rtc_clk
, 0, CCM_CGR2
, 0, get_rate_ipg
, NULL
);
392 DEFINE_CLOCK(rtic_clk
, 0, CCM_CGR2
, 2, get_rate_ahb
, NULL
);
393 DEFINE_CLOCK(scc_clk
, 0, CCM_CGR2
, 4, get_rate_ipg
, NULL
);
394 DEFINE_CLOCK(sdma_clk
, 0, CCM_CGR2
, 6, NULL
, NULL
);
395 DEFINE_CLOCK(spba_clk
, 0, CCM_CGR2
, 8, get_rate_ipg
, NULL
);
396 DEFINE_CLOCK(spdif_clk
, 0, CCM_CGR2
, 10, NULL
, NULL
);
397 DEFINE_CLOCK(ssi1_clk
, 0, CCM_CGR2
, 12, get_rate_ssi
, NULL
);
398 DEFINE_CLOCK(ssi2_clk
, 1, CCM_CGR2
, 14, get_rate_ssi
, NULL
);
399 DEFINE_CLOCK(uart1_clk
, 0, CCM_CGR2
, 16, get_rate_uart
, NULL
);
400 DEFINE_CLOCK(uart2_clk
, 1, CCM_CGR2
, 18, get_rate_uart
, NULL
);
401 DEFINE_CLOCK(uart3_clk
, 2, CCM_CGR2
, 20, get_rate_uart
, NULL
);
402 DEFINE_CLOCK(usbotg_clk
, 0, CCM_CGR2
, 22, get_rate_otg
, NULL
);
403 DEFINE_CLOCK(wdog_clk
, 0, CCM_CGR2
, 24, NULL
, NULL
);
404 DEFINE_CLOCK(max_clk
, 0, CCM_CGR2
, 26, NULL
, NULL
);
405 DEFINE_CLOCK(audmux_clk
, 0, CCM_CGR2
, 30, NULL
, NULL
);
407 DEFINE_CLOCK(csi_clk
, 0, CCM_CGR3
, 0, get_rate_csi
, NULL
);
408 DEFINE_CLOCK(iim_clk
, 0, CCM_CGR3
, 2, NULL
, NULL
);
409 DEFINE_CLOCK(gpu2d_clk
, 0, CCM_CGR3
, 4, NULL
, NULL
);
411 DEFINE_CLOCK(usbahb_clk
, 0, 0, 0, get_rate_ahb
, NULL
);
413 static int clk_dummy_enable(struct clk
*clk
)
418 static void clk_dummy_disable(struct clk
*clk
)
422 static unsigned long get_rate_nfc(struct clk
*clk
)
426 div1
= (__raw_readl(CCM_BASE
+ CCM_PDR4
) >> 28) + 1;
428 return get_rate_ahb(NULL
) / div1
;
431 /* NAND Controller: It seems it can't be disabled */
432 static struct clk nfc_clk
= {
436 .get_rate
= get_rate_nfc
,
437 .set_rate
= NULL
, /* set_rate_nfc, */
438 .enable
= clk_dummy_enable
,
439 .disable
= clk_dummy_disable
442 #define _REGISTER_CLOCK(d, n, c) \
449 static struct clk_lookup lookups
[] = {
450 _REGISTER_CLOCK(NULL
, "asrc", asrc_clk
)
451 _REGISTER_CLOCK(NULL
, "ata", ata_clk
)
452 _REGISTER_CLOCK("flexcan.0", NULL
, can1_clk
)
453 _REGISTER_CLOCK("flexcan.1", NULL
, can2_clk
)
454 _REGISTER_CLOCK("imx35-cspi.0", NULL
, cspi1_clk
)
455 _REGISTER_CLOCK("imx35-cspi.1", NULL
, cspi2_clk
)
456 _REGISTER_CLOCK(NULL
, "ect", ect_clk
)
457 _REGISTER_CLOCK(NULL
, "edio", edio_clk
)
458 _REGISTER_CLOCK(NULL
, "emi", emi_clk
)
459 _REGISTER_CLOCK("imx-epit.0", NULL
, epit1_clk
)
460 _REGISTER_CLOCK("imx-epit.1", NULL
, epit2_clk
)
461 _REGISTER_CLOCK(NULL
, "esai", esai_clk
)
462 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL
, esdhc1_clk
)
463 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL
, esdhc2_clk
)
464 _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL
, esdhc3_clk
)
465 _REGISTER_CLOCK("fec.0", NULL
, fec_clk
)
466 _REGISTER_CLOCK(NULL
, "gpio", gpio1_clk
)
467 _REGISTER_CLOCK(NULL
, "gpio", gpio2_clk
)
468 _REGISTER_CLOCK(NULL
, "gpio", gpio3_clk
)
469 _REGISTER_CLOCK("gpt.0", NULL
, gpt_clk
)
470 _REGISTER_CLOCK("imx-i2c.0", NULL
, i2c1_clk
)
471 _REGISTER_CLOCK("imx-i2c.1", NULL
, i2c2_clk
)
472 _REGISTER_CLOCK("imx-i2c.2", NULL
, i2c3_clk
)
473 _REGISTER_CLOCK(NULL
, "iomuxc", iomuxc_clk
)
474 _REGISTER_CLOCK("ipu-core", NULL
, ipu_clk
)
475 _REGISTER_CLOCK("mx3_sdc_fb", NULL
, ipu_clk
)
476 _REGISTER_CLOCK(NULL
, "kpp", kpp_clk
)
477 _REGISTER_CLOCK(NULL
, "mlb", mlb_clk
)
478 _REGISTER_CLOCK(NULL
, "mshc", mshc_clk
)
479 _REGISTER_CLOCK("mxc_w1", NULL
, owire_clk
)
480 _REGISTER_CLOCK(NULL
, "pwm", pwm_clk
)
481 _REGISTER_CLOCK(NULL
, "rngc", rngc_clk
)
482 _REGISTER_CLOCK(NULL
, "rtc", rtc_clk
)
483 _REGISTER_CLOCK(NULL
, "rtic", rtic_clk
)
484 _REGISTER_CLOCK(NULL
, "scc", scc_clk
)
485 _REGISTER_CLOCK("imx-sdma", NULL
, sdma_clk
)
486 _REGISTER_CLOCK(NULL
, "spba", spba_clk
)
487 _REGISTER_CLOCK(NULL
, "spdif", spdif_clk
)
488 _REGISTER_CLOCK("imx-ssi.0", NULL
, ssi1_clk
)
489 _REGISTER_CLOCK("imx-ssi.1", NULL
, ssi2_clk
)
490 _REGISTER_CLOCK("imx-uart.0", NULL
, uart1_clk
)
491 _REGISTER_CLOCK("imx-uart.1", NULL
, uart2_clk
)
492 _REGISTER_CLOCK("imx-uart.2", NULL
, uart3_clk
)
493 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk
)
494 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk
)
495 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk
)
496 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk
)
497 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk
)
498 _REGISTER_CLOCK("imx-wdt.0", NULL
, wdog_clk
)
499 _REGISTER_CLOCK(NULL
, "max", max_clk
)
500 _REGISTER_CLOCK(NULL
, "audmux", audmux_clk
)
501 _REGISTER_CLOCK(NULL
, "csi", csi_clk
)
502 _REGISTER_CLOCK(NULL
, "iim", iim_clk
)
503 _REGISTER_CLOCK(NULL
, "gpu2d", gpu2d_clk
)
504 _REGISTER_CLOCK("mxc_nand.0", NULL
, nfc_clk
)
507 int __init
mx35_clocks_init()
509 unsigned int cgr2
= 3 << 26, cgr3
= 0;
511 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
515 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
517 /* Turn off all clocks except the ones we need to survive, namely:
518 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
520 __raw_writel((3 << 18), CCM_BASE
+ CCM_CGR0
);
521 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
522 CCM_BASE
+ CCM_CGR1
);
525 * Check if we came up in internal boot mode. If yes, we need some
526 * extra clocks turned on, otherwise the MX35 boot ROM code will
527 * hang after a watchdog reset.
529 if (!(__raw_readl(CCM_BASE
+ CCM_RCSR
) & (3 << 10))) {
530 /* Additionally turn on UART1, SCC, and IIM clocks */
531 cgr2
|= 3 << 16 | 3 << 4;
535 __raw_writel(cgr2
, CCM_BASE
+ CCM_CGR2
);
536 __raw_writel(cgr3
, CCM_BASE
+ CCM_CGR3
);
538 clk_enable(&iim_clk
);
541 #ifdef CONFIG_MXC_USE_EPIT
542 epit_timer_init(&epit1_clk
,
543 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR
), MX35_INT_EPIT1
);
545 mxc_timer_init(&gpt_clk
,
546 MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR
), MX35_INT_GPT
);