?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
omap_hsmmc: only MMC1 allows HCTL.SDVS != 1.8V
[linux-2.6.git] / drivers / mmc / host / omap_hsmmc.c
blob3bfd0facb794e15c5f628aa7876901718d2eeaa7
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
28 #include <linux/io.h>
29 #include <linux/semaphore.h>
30 #include <mach/dma.h>
31 #include <mach/hardware.h>
32 #include <mach/board.h>
33 #include <mach/mmc.h>
34 #include <mach/cpu.h>
35
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
53
54 #define VS18 (1 << 26)
55 #define VS30 (1 << 25)
56 #define SDVS18 (0x5 << 9)
57 #define SDVS30 (0x6 << 9)
58 #define SDVS33 (0x7 << 9)
59 #define SDVSCLR 0xFFFFF1FF
60 #define SDVSDET 0x00000400
61 #define AUTOIDLE 0x1
62 #define SDBP (1 << 8)
63 #define DTO 0xe
64 #define ICE 0x1
65 #define ICS 0x2
66 #define CEN (1 << 2)
67 #define CLKD_MASK 0x0000FFC0
68 #define CLKD_SHIFT 6
69 #define DTO_MASK 0x000F0000
70 #define DTO_SHIFT 16
71 #define INT_EN_MASK 0x307F0033
72 #define INIT_STREAM (1 << 1)
73 #define DP_SELECT (1 << 21)
74 #define DDIR (1 << 4)
75 #define DMA_EN 0x1
76 #define MSBS (1 << 5)
77 #define BCE (1 << 1)
78 #define FOUR_BIT (1 << 1)
79 #define CC 0x1
80 #define TC 0x02
81 #define OD 0x1
82 #define ERR (1 << 15)
83 #define CMD_TIMEOUT (1 << 16)
84 #define DATA_TIMEOUT (1 << 20)
85 #define CMD_CRC (1 << 17)
86 #define DATA_CRC (1 << 21)
87 #define CARD_ERR (1 << 28)
88 #define STAT_CLEAR 0xFFFFFFFF
89 #define INIT_STREAM_CMD 0x00000000
90 #define DUAL_VOLT_OCR_BIT 7
91 #define SRC (1 << 25)
92 #define SRD (1 << 26)
93
94 /*
95 * FIXME: Most likely all the data using these _DEVID defines should come
96 * from the platform_data, or implemented in controller and slot specific
97 * functions.
98 */
99 #define OMAP_MMC1_DEVID 0
100 #define OMAP_MMC2_DEVID 1
101
102 #define OMAP_MMC_DATADIR_NONE 0
103 #define OMAP_MMC_DATADIR_READ 1
104 #define OMAP_MMC_DATADIR_WRITE 2
105 #define MMC_TIMEOUT_MS 20
106 #define OMAP_MMC_MASTER_CLOCK 96000000
107 #define DRIVER_NAME "mmci-omap-hs"
108
109 /*
110 * One controller can have multiple slots, like on some omap boards using
111 * omap.c controller driver. Luckily this is not currently done on any known
112 * omap_hsmmc.c device.
113 */
114 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
115
116 /*
117 * MMC Host controller read/write API's
118 */
119 #define OMAP_HSMMC_READ(base, reg) \
120 __raw_readl((base) + OMAP_HSMMC_##reg)
121
122 #define OMAP_HSMMC_WRITE(base, reg, val) \
123 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
124
125 struct mmc_omap_host {
126 struct device *dev;
127 struct mmc_host *mmc;
128 struct mmc_request *mrq;
129 struct mmc_command *cmd;
130 struct mmc_data *data;
131 struct clk *fclk;
132 struct clk *iclk;
133 struct clk *dbclk;
134 struct semaphore sem;
135 struct work_struct mmc_carddetect_work;
136 void __iomem *base;
137 resource_size_t mapbase;
138 unsigned int id;
139 unsigned int dma_len;
140 unsigned int dma_dir;
141 unsigned char bus_mode;
142 unsigned char datadir;
143 u32 *buffer;
144 u32 bytesleft;
145 int suspended;
146 int irq;
147 int carddetect;
148 int use_dma, dma_ch;
149 int initstr;
150 int slot_id;
151 int dbclk_enabled;
152 struct omap_mmc_platform_data *pdata;
153 };
154
155 /*
156 * Stop clock to the card
157 */
158 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
159 {
160 OMAP_HSMMC_WRITE(host->base, SYSCTL,
161 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
162 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
163 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
164 }
165
166 /*
167 * Send init stream sequence to card
168 * before sending IDLE command
169 */
170 static void send_init_stream(struct mmc_omap_host *host)
171 {
172 int reg = 0;
173 unsigned long timeout;
174
175 disable_irq(host->irq);
176 OMAP_HSMMC_WRITE(host->base, CON,
177 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
178 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
179
180 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
181 while ((reg != CC) && time_before(jiffies, timeout))
182 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
183
184 OMAP_HSMMC_WRITE(host->base, CON,
185 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
186 enable_irq(host->irq);
187 }
188
189 static inline
190 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
191 {
192 int r = 1;
193
194 if (host->pdata->slots[host->slot_id].get_cover_state)
195 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
196 host->slot_id);
197 return r;
198 }
199
200 static ssize_t
201 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
202 char *buf)
203 {
204 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
205 struct mmc_omap_host *host = mmc_priv(mmc);
206
207 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
208 "open");
209 }
210
211 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
212
213 static ssize_t
214 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
215 char *buf)
216 {
217 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
218 struct mmc_omap_host *host = mmc_priv(mmc);
219 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
220
221 return sprintf(buf, "slot:%s\n", slot.name);
222 }
223
224 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
225
226 /*
227 * Configure the response type and send the cmd.
228 */
229 static void
230 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
231 struct mmc_data *data)
232 {
233 int cmdreg = 0, resptype = 0, cmdtype = 0;
234
235 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
236 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
237 host->cmd = cmd;
238
239 /*
240 * Clear status bits and enable interrupts
241 */
242 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
243 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
244 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
245
246 if (cmd->flags & MMC_RSP_PRESENT) {
247 if (cmd->flags & MMC_RSP_136)
248 resptype = 1;
249 else
250 resptype = 2;
251 }
252
253 /*
254 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
255 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
256 * a val of 0x3, rest 0x0.
257 */
258 if (cmd == host->mrq->stop)
259 cmdtype = 0x3;
260
261 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
262
263 if (data) {
264 cmdreg |= DP_SELECT | MSBS | BCE;
265 if (data->flags & MMC_DATA_READ)
266 cmdreg |= DDIR;
267 else
268 cmdreg &= ~(DDIR);
269 }
270
271 if (host->use_dma)
272 cmdreg |= DMA_EN;
273
274 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
275 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
276 }
277
278 /*
279 * Notify the transfer complete to MMC core
280 */
281 static void
282 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
283 {
284 host->data = NULL;
285
286 if (host->use_dma && host->dma_ch != -1)
287 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
288 host->dma_dir);
289
290 host->datadir = OMAP_MMC_DATADIR_NONE;
291
292 if (!data->error)
293 data->bytes_xfered += data->blocks * (data->blksz);
294 else
295 data->bytes_xfered = 0;
296
297 if (!data->stop) {
298 host->mrq = NULL;
299 mmc_request_done(host->mmc, data->mrq);
300 return;
301 }
302 mmc_omap_start_command(host, data->stop, NULL);
303 }
304
305 /*
306 * Notify the core about command completion
307 */
308 static void
309 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
310 {
311 host->cmd = NULL;
312
313 if (cmd->flags & MMC_RSP_PRESENT) {
314 if (cmd->flags & MMC_RSP_136) {
315 /* response type 2 */
316 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
317 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
318 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
319 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
320 } else {
321 /* response types 1, 1b, 3, 4, 5, 6 */
322 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
323 }
324 }
325 if (host->data == NULL || cmd->error) {
326 host->mrq = NULL;
327 mmc_request_done(host->mmc, cmd->mrq);
328 }
329 }
330
331 /*
332 * DMA clean up for command errors
333 */
334 static void mmc_dma_cleanup(struct mmc_omap_host *host)
335 {
336 host->data->error = -ETIMEDOUT;
337
338 if (host->use_dma && host->dma_ch != -1) {
339 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
340 host->dma_dir);
341 omap_free_dma(host->dma_ch);
342 host->dma_ch = -1;
343 up(&host->sem);
344 }
345 host->data = NULL;
346 host->datadir = OMAP_MMC_DATADIR_NONE;
347 }
348
349 /*
350 * Readable error output
351 */
352 #ifdef CONFIG_MMC_DEBUG
353 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
354 {
355 /* --- means reserved bit without definition at documentation */
356 static const char *mmc_omap_status_bits[] = {
357 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
358 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
359 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
360 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
361 };
362 char res[256];
363 char *buf = res;
364 int len, i;
365
366 len = sprintf(buf, "MMC IRQ 0x%x :", status);
367 buf += len;
368
369 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
370 if (status & (1 << i)) {
371 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
372 buf += len;
373 }
374
375 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
376 }
377 #endif /* CONFIG_MMC_DEBUG */
378
379
380 /*
381 * MMC controller IRQ handler
382 */
383 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
384 {
385 struct mmc_omap_host *host = dev_id;
386 struct mmc_data *data;
387 int end_cmd = 0, end_trans = 0, status;
388
389 if (host->cmd == NULL && host->data == NULL) {
390 OMAP_HSMMC_WRITE(host->base, STAT,
391 OMAP_HSMMC_READ(host->base, STAT));
392 return IRQ_HANDLED;
393 }
394
395 data = host->data;
396 status = OMAP_HSMMC_READ(host->base, STAT);
397 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
398
399 if (status & ERR) {
400 #ifdef CONFIG_MMC_DEBUG
401 mmc_omap_report_irq(host, status);
402 #endif
403 if ((status & CMD_TIMEOUT) ||
404 (status & CMD_CRC)) {
405 if (host->cmd) {
406 if (status & CMD_TIMEOUT) {
407 OMAP_HSMMC_WRITE(host->base, SYSCTL,
408 OMAP_HSMMC_READ(host->base,
409 SYSCTL) | SRC);
410 while (OMAP_HSMMC_READ(host->base,
411 SYSCTL) & SRC)
412 ;
413
414 host->cmd->error = -ETIMEDOUT;
415 } else {
416 host->cmd->error = -EILSEQ;
417 }
418 end_cmd = 1;
419 }
420 if (host->data)
421 mmc_dma_cleanup(host);
422 }
423 if ((status & DATA_TIMEOUT) ||
424 (status & DATA_CRC)) {
425 if (host->data) {
426 if (status & DATA_TIMEOUT)
427 mmc_dma_cleanup(host);
428 else
429 host->data->error = -EILSEQ;
430 OMAP_HSMMC_WRITE(host->base, SYSCTL,
431 OMAP_HSMMC_READ(host->base,
432 SYSCTL) | SRD);
433 while (OMAP_HSMMC_READ(host->base,
434 SYSCTL) & SRD)
435 ;
436 end_trans = 1;
437 }
438 }
439 if (status & CARD_ERR) {
440 dev_dbg(mmc_dev(host->mmc),
441 "Ignoring card err CMD%d\n", host->cmd->opcode);
442 if (host->cmd)
443 end_cmd = 1;
444 if (host->data)
445 end_trans = 1;
446 }
447 }
448
449 OMAP_HSMMC_WRITE(host->base, STAT, status);
450
451 if (end_cmd || (status & CC))
452 mmc_omap_cmd_done(host, host->cmd);
453 if (end_trans || (status & TC))
454 mmc_omap_xfer_done(host, data);
455
456 return IRQ_HANDLED;
457 }
458
459 /*
460 * Switch MMC interface voltage ... only relevant for MMC1.
461 *
462 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
463 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
464 * Some chips, like eMMC ones, use internal transceivers.
465 */
466 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
467 {
468 u32 reg_val = 0;
469 int ret;
470
471 if (host->id != OMAP_MMC1_DEVID)
472 return 0;
473
474 /* Disable the clocks */
475 clk_disable(host->fclk);
476 clk_disable(host->iclk);
477 clk_disable(host->dbclk);
478
479 /* Turn the power off */
480 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
481 if (ret != 0)
482 goto err;
483
484 /* Turn the power ON with given VDD 1.8 or 3.0v */
485 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
486 if (ret != 0)
487 goto err;
488
489 clk_enable(host->fclk);
490 clk_enable(host->iclk);
491 clk_enable(host->dbclk);
492
493 OMAP_HSMMC_WRITE(host->base, HCTL,
494 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
495 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
496
497 /*
498 * If a MMC dual voltage card is detected, the set_ios fn calls
499 * this fn with VDD bit set for 1.8V. Upon card removal from the
500 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
501 *
502 * Cope with a bit of slop in the range ... per data sheets:
503 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
504 * but recommended values are 1.71V to 1.89V
505 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
506 * but recommended values are 2.7V to 3.3V
507 *
508 * Board setup code shouldn't permit anything very out-of-range.
509 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
510 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
511 */
512 if ((1 << vdd) <= MMC_VDD_23_24)
513 reg_val |= SDVS18;
514 else
515 reg_val |= SDVS30;
516
517 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
518
519 OMAP_HSMMC_WRITE(host->base, HCTL,
520 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
521
522 return 0;
523 err:
524 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
525 return ret;
526 }
527
528 /*
529 * Work Item to notify the core about card insertion/removal
530 */
531 static void mmc_omap_detect(struct work_struct *work)
532 {
533 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
534 mmc_carddetect_work);
535 struct omap_mmc_slot_data *slot = &mmc_slot(host);
536
537 host->carddetect = slot->card_detect(slot->card_detect_irq);
538
539 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
540 if (host->carddetect) {
541 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
542 } else {
543 OMAP_HSMMC_WRITE(host->base, SYSCTL,
544 OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
545 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD)
546 ;
547
548 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
549 }
550 }
551
552 /*
553 * ISR for handling card insertion and removal
554 */
555 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
556 {
557 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
558
559 schedule_work(&host->mmc_carddetect_work);
560
561 return IRQ_HANDLED;
562 }
563
564 /*
565 * DMA call back function
566 */
567 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
568 {
569 struct mmc_omap_host *host = data;
570
571 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
572 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
573
574 if (host->dma_ch < 0)
575 return;
576
577 omap_free_dma(host->dma_ch);
578 host->dma_ch = -1;
579 /*
580 * DMA Callback: run in interrupt context.
581 * mutex_unlock will through a kernel warning if used.
582 */
583 up(&host->sem);
584 }
585
586 /*
587 * Configure dma src and destination parameters
588 */
589 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
590 struct mmc_data *data)
591 {
592 if (sync_dir == 0) {
593 omap_set_dma_dest_params(host->dma_ch, 0,
594 OMAP_DMA_AMODE_CONSTANT,
595 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
596 omap_set_dma_src_params(host->dma_ch, 0,
597 OMAP_DMA_AMODE_POST_INC,
598 sg_dma_address(&data->sg[0]), 0, 0);
599 } else {
600 omap_set_dma_src_params(host->dma_ch, 0,
601 OMAP_DMA_AMODE_CONSTANT,
602 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
603 omap_set_dma_dest_params(host->dma_ch, 0,
604 OMAP_DMA_AMODE_POST_INC,
605 sg_dma_address(&data->sg[0]), 0, 0);
606 }
607 return 0;
608 }
609 /*
610 * Routine to configure and start DMA for the MMC card
611 */
612 static int
613 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
614 {
615 int sync_dev, sync_dir = 0;
616 int dma_ch = 0, ret = 0, err = 1;
617 struct mmc_data *data = req->data;
618
619 /*
620 * If for some reason the DMA transfer is still active,
621 * we wait for timeout period and free the dma
622 */
623 if (host->dma_ch != -1) {
624 set_current_state(TASK_UNINTERRUPTIBLE);
625 schedule_timeout(100);
626 if (down_trylock(&host->sem)) {
627 omap_free_dma(host->dma_ch);
628 host->dma_ch = -1;
629 up(&host->sem);
630 return err;
631 }
632 } else {
633 if (down_trylock(&host->sem))
634 return err;
635 }
636
637 if (!(data->flags & MMC_DATA_WRITE)) {
638 host->dma_dir = DMA_FROM_DEVICE;
639 if (host->id == OMAP_MMC1_DEVID)
640 sync_dev = OMAP24XX_DMA_MMC1_RX;
641 else
642 sync_dev = OMAP24XX_DMA_MMC2_RX;
643 } else {
644 host->dma_dir = DMA_TO_DEVICE;
645 if (host->id == OMAP_MMC1_DEVID)
646 sync_dev = OMAP24XX_DMA_MMC1_TX;
647 else
648 sync_dev = OMAP24XX_DMA_MMC2_TX;
649 }
650
651 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
652 host, &dma_ch);
653 if (ret != 0) {
654 dev_dbg(mmc_dev(host->mmc),
655 "%s: omap_request_dma() failed with %d\n",
656 mmc_hostname(host->mmc), ret);
657 return ret;
658 }
659
660 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
661 data->sg_len, host->dma_dir);
662 host->dma_ch = dma_ch;
663
664 if (!(data->flags & MMC_DATA_WRITE))
665 mmc_omap_config_dma_param(1, host, data);
666 else
667 mmc_omap_config_dma_param(0, host, data);
668
669 if ((data->blksz % 4) == 0)
670 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
671 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
672 sync_dev, sync_dir);
673 else
674 /* REVISIT: The MMC buffer increments only when MSB is written.
675 * Return error for blksz which is non multiple of four.
676 */
677 return -EINVAL;
678
679 omap_start_dma(dma_ch);
680 return 0;
681 }
682
683 static void set_data_timeout(struct mmc_omap_host *host,
684 struct mmc_request *req)
685 {
686 unsigned int timeout, cycle_ns;
687 uint32_t reg, clkd, dto = 0;
688
689 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
690 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
691 if (clkd == 0)
692 clkd = 1;
693
694 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
695 timeout = req->data->timeout_ns / cycle_ns;
696 timeout += req->data->timeout_clks;
697 if (timeout) {
698 while ((timeout & 0x80000000) == 0) {
699 dto += 1;
700 timeout <<= 1;
701 }
702 dto = 31 - dto;
703 timeout <<= 1;
704 if (timeout && dto)
705 dto += 1;
706 if (dto >= 13)
707 dto -= 13;
708 else
709 dto = 0;
710 if (dto > 14)
711 dto = 14;
712 }
713
714 reg &= ~DTO_MASK;
715 reg |= dto << DTO_SHIFT;
716 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
717 }
718
719 /*
720 * Configure block length for MMC/SD cards and initiate the transfer.
721 */
722 static int
723 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
724 {
725 int ret;
726 host->data = req->data;
727
728 if (req->data == NULL) {
729 host->datadir = OMAP_MMC_DATADIR_NONE;
730 OMAP_HSMMC_WRITE(host->base, BLK, 0);
731 return 0;
732 }
733
734 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
735 | (req->data->blocks << 16));
736 set_data_timeout(host, req);
737
738 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
739 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
740
741 if (host->use_dma) {
742 ret = mmc_omap_start_dma_transfer(host, req);
743 if (ret != 0) {
744 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
745 return ret;
746 }
747 }
748 return 0;
749 }
750
751 /*
752 * Request function. for read/write operation
753 */
754 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
755 {
756 struct mmc_omap_host *host = mmc_priv(mmc);
757
758 WARN_ON(host->mrq != NULL);
759 host->mrq = req;
760 mmc_omap_prepare_data(host, req);
761 mmc_omap_start_command(host, req->cmd, req->data);
762 }
763
764
765 /* Routine to configure clock values. Exposed API to core */
766 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
767 {
768 struct mmc_omap_host *host = mmc_priv(mmc);
769 u16 dsor = 0;
770 unsigned long regval;
771 unsigned long timeout;
772
773 switch (ios->power_mode) {
774 case MMC_POWER_OFF:
775 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
776 /*
777 * Reset interface voltage to 3V if it's 1.8V now;
778 * only relevant on MMC-1, the others always use 1.8V.
779 *
780 * REVISIT: If we are able to detect cards after unplugging
781 * a 1.8V card, this code should not be needed.
782 */
783 if (host->id != OMAP_MMC1_DEVID)
784 break;
785 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
786 int vdd = fls(host->mmc->ocr_avail) - 1;
787 if (omap_mmc_switch_opcond(host, vdd) != 0)
788 host->mmc->ios.vdd = vdd;
789 }
790 break;
791 case MMC_POWER_UP:
792 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
793 break;
794 }
795
796 switch (mmc->ios.bus_width) {
797 case MMC_BUS_WIDTH_4:
798 OMAP_HSMMC_WRITE(host->base, HCTL,
799 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
800 break;
801 case MMC_BUS_WIDTH_1:
802 OMAP_HSMMC_WRITE(host->base, HCTL,
803 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
804 break;
805 }
806
807 if (host->id == OMAP_MMC1_DEVID) {
808 /* Only MMC1 can interface at 3V without some flavor
809 * of external transceiver; but they all handle 1.8V.
810 */
811 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
812 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
813 /*
814 * The mmc_select_voltage fn of the core does
815 * not seem to set the power_mode to
816 * MMC_POWER_UP upon recalculating the voltage.
817 * vdd 1.8v.
818 */
819 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
820 dev_dbg(mmc_dev(host->mmc),
821 "Switch operation failed\n");
822 }
823 }
824
825 if (ios->clock) {
826 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
827 if (dsor < 1)
828 dsor = 1;
829
830 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
831 dsor++;
832
833 if (dsor > 250)
834 dsor = 250;
835 }
836 omap_mmc_stop_clock(host);
837 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
838 regval = regval & ~(CLKD_MASK);
839 regval = regval | (dsor << 6) | (DTO << 16);
840 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
841 OMAP_HSMMC_WRITE(host->base, SYSCTL,
842 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
843
844 /* Wait till the ICS bit is set */
845 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
846 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
847 && time_before(jiffies, timeout))
848 msleep(1);
849
850 OMAP_HSMMC_WRITE(host->base, SYSCTL,
851 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
852
853 if (ios->power_mode == MMC_POWER_ON)
854 send_init_stream(host);
855
856 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
857 OMAP_HSMMC_WRITE(host->base, CON,
858 OMAP_HSMMC_READ(host->base, CON) | OD);
859 }
860
861 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
862 {
863 struct mmc_omap_host *host = mmc_priv(mmc);
864 struct omap_mmc_platform_data *pdata = host->pdata;
865
866 if (!pdata->slots[0].card_detect)
867 return -ENOSYS;
868 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
869 }
870
871 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
872 {
873 struct mmc_omap_host *host = mmc_priv(mmc);
874 struct omap_mmc_platform_data *pdata = host->pdata;
875
876 if (!pdata->slots[0].get_ro)
877 return -ENOSYS;
878 return pdata->slots[0].get_ro(host->dev, 0);
879 }
880
881 static struct mmc_host_ops mmc_omap_ops = {
882 .request = omap_mmc_request,
883 .set_ios = omap_mmc_set_ios,
884 .get_cd = omap_hsmmc_get_cd,
885 .get_ro = omap_hsmmc_get_ro,
886 /* NYET -- enable_sdio_irq */
887 };
888
889 static int __init omap_mmc_probe(struct platform_device *pdev)
890 {
891 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
892 struct mmc_host *mmc;
893 struct mmc_omap_host *host = NULL;
894 struct resource *res;
895 int ret = 0, irq;
896 u32 hctl, capa;
897
898 if (pdata == NULL) {
899 dev_err(&pdev->dev, "Platform Data is missing\n");
900 return -ENXIO;
901 }
902
903 if (pdata->nr_slots == 0) {
904 dev_err(&pdev->dev, "No Slots\n");
905 return -ENXIO;
906 }
907
908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
909 irq = platform_get_irq(pdev, 0);
910 if (res == NULL || irq < 0)
911 return -ENXIO;
912
913 res = request_mem_region(res->start, res->end - res->start + 1,
914 pdev->name);
915 if (res == NULL)
916 return -EBUSY;
917
918 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
919 if (!mmc) {
920 ret = -ENOMEM;
921 goto err;
922 }
923
924 host = mmc_priv(mmc);
925 host->mmc = mmc;
926 host->pdata = pdata;
927 host->dev = &pdev->dev;
928 host->use_dma = 1;
929 host->dev->dma_mask = &pdata->dma_mask;
930 host->dma_ch = -1;
931 host->irq = irq;
932 host->id = pdev->id;
933 host->slot_id = 0;
934 host->mapbase = res->start;
935 host->base = ioremap(host->mapbase, SZ_4K);
936
937 platform_set_drvdata(pdev, host);
938 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
939
940 mmc->ops = &mmc_omap_ops;
941 mmc->f_min = 400000;
942 mmc->f_max = 52000000;
943
944 sema_init(&host->sem, 1);
945
946 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
947 if (IS_ERR(host->iclk)) {
948 ret = PTR_ERR(host->iclk);
949 host->iclk = NULL;
950 goto err1;
951 }
952 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
953 if (IS_ERR(host->fclk)) {
954 ret = PTR_ERR(host->fclk);
955 host->fclk = NULL;
956 clk_put(host->iclk);
957 goto err1;
958 }
959
960 if (clk_enable(host->fclk) != 0) {
961 clk_put(host->iclk);
962 clk_put(host->fclk);
963 goto err1;
964 }
965
966 if (clk_enable(host->iclk) != 0) {
967 clk_disable(host->fclk);
968 clk_put(host->iclk);
969 clk_put(host->fclk);
970 goto err1;
971 }
972
973 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
974 /*
975 * MMC can still work without debounce clock.
976 */
977 if (IS_ERR(host->dbclk))
978 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
979 else
980 if (clk_enable(host->dbclk) != 0)
981 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
982 " clk failed\n");
983 else
984 host->dbclk_enabled = 1;
985
986 #ifdef CONFIG_MMC_BLOCK_BOUNCE
987 mmc->max_phys_segs = 1;
988 mmc->max_hw_segs = 1;
989 #endif
990 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
991 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
992 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
993 mmc->max_seg_size = mmc->max_req_size;
994
995 mmc->ocr_avail = mmc_slot(host).ocr_mask;
996 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
997
998 if (pdata->slots[host->slot_id].wires >= 4)
999 mmc->caps |= MMC_CAP_4_BIT_DATA;
1000
1001 /* Only MMC1 supports 3.0V */
1002 if (host->id == OMAP_MMC1_DEVID) {
1003 hctl = SDVS30;
1004 capa = VS30 | VS18;
1005 } else {
1006 hctl = SDVS18;
1007 capa = VS18;
1008 }
1009
1010 OMAP_HSMMC_WRITE(host->base, HCTL,
1011 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1012
1013 OMAP_HSMMC_WRITE(host->base, CAPA,
1014 OMAP_HSMMC_READ(host->base, CAPA) | capa);
1015
1016 /* Set the controller to AUTO IDLE mode */
1017 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1018 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1019
1020 /* Set SD bus power bit */
1021 OMAP_HSMMC_WRITE(host->base, HCTL,
1022 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1023
1024 /* Request IRQ for MMC operations */
1025 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1026 mmc_hostname(mmc), host);
1027 if (ret) {
1028 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1029 goto err_irq;
1030 }
1031
1032 if (pdata->init != NULL) {
1033 if (pdata->init(&pdev->dev) != 0) {
1034 dev_dbg(mmc_dev(host->mmc),
1035 "Unable to configure MMC IRQs\n");
1036 goto err_irq_cd_init;
1037 }
1038 }
1039
1040 /* Request IRQ for card detect */
1041 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1042 ret = request_irq(mmc_slot(host).card_detect_irq,
1043 omap_mmc_cd_handler,
1044 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1045 | IRQF_DISABLED,
1046 mmc_hostname(mmc), host);
1047 if (ret) {
1048 dev_dbg(mmc_dev(host->mmc),
1049 "Unable to grab MMC CD IRQ\n");
1050 goto err_irq_cd;
1051 }
1052 }
1053
1054 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1055 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1056
1057 mmc_add_host(mmc);
1058
1059 if (host->pdata->slots[host->slot_id].name != NULL) {
1060 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1061 if (ret < 0)
1062 goto err_slot_name;
1063 }
1064 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1065 host->pdata->slots[host->slot_id].get_cover_state) {
1066 ret = device_create_file(&mmc->class_dev,
1067 &dev_attr_cover_switch);
1068 if (ret < 0)
1069 goto err_cover_switch;
1070 }
1071
1072 return 0;
1073
1074 err_cover_switch:
1075 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1076 err_slot_name:
1077 mmc_remove_host(mmc);
1078 err_irq_cd:
1079 free_irq(mmc_slot(host).card_detect_irq, host);
1080 err_irq_cd_init:
1081 free_irq(host->irq, host);
1082 err_irq:
1083 clk_disable(host->fclk);
1084 clk_disable(host->iclk);
1085 clk_put(host->fclk);
1086 clk_put(host->iclk);
1087 if (host->dbclk_enabled) {
1088 clk_disable(host->dbclk);
1089 clk_put(host->dbclk);
1090 }
1091
1092 err1:
1093 iounmap(host->base);
1094 err:
1095 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1096 release_mem_region(res->start, res->end - res->start + 1);
1097 if (host)
1098 mmc_free_host(mmc);
1099 return ret;
1100 }
1101
1102 static int omap_mmc_remove(struct platform_device *pdev)
1103 {
1104 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1105 struct resource *res;
1106
1107 if (host) {
1108 mmc_remove_host(host->mmc);
1109 if (host->pdata->cleanup)
1110 host->pdata->cleanup(&pdev->dev);
1111 free_irq(host->irq, host);
1112 if (mmc_slot(host).card_detect_irq)
1113 free_irq(mmc_slot(host).card_detect_irq, host);
1114 flush_scheduled_work();
1115
1116 clk_disable(host->fclk);
1117 clk_disable(host->iclk);
1118 clk_put(host->fclk);
1119 clk_put(host->iclk);
1120 if (host->dbclk_enabled) {
1121 clk_disable(host->dbclk);
1122 clk_put(host->dbclk);
1123 }
1124
1125 mmc_free_host(host->mmc);
1126 iounmap(host->base);
1127 }
1128
1129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130 if (res)
1131 release_mem_region(res->start, res->end - res->start + 1);
1132 platform_set_drvdata(pdev, NULL);
1133
1134 return 0;
1135 }
1136
1137 #ifdef CONFIG_PM
1138 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1139 {
1140 int ret = 0;
1141 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1142
1143 if (host && host->suspended)
1144 return 0;
1145
1146 if (host) {
1147 ret = mmc_suspend_host(host->mmc, state);
1148 if (ret == 0) {
1149 host->suspended = 1;
1150
1151 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1152 OMAP_HSMMC_WRITE(host->base, IE, 0);
1153
1154 if (host->pdata->suspend) {
1155 ret = host->pdata->suspend(&pdev->dev,
1156 host->slot_id);
1157 if (ret)
1158 dev_dbg(mmc_dev(host->mmc),
1159 "Unable to handle MMC board"
1160 " level suspend\n");
1161 }
1162
1163 if (host->id == OMAP_MMC1_DEVID
1164 && !(OMAP_HSMMC_READ(host->base, HCTL)
1165 & SDVSDET)) {
1166 OMAP_HSMMC_WRITE(host->base, HCTL,
1167 OMAP_HSMMC_READ(host->base, HCTL)
1168 & SDVSCLR);
1169 OMAP_HSMMC_WRITE(host->base, HCTL,
1170 OMAP_HSMMC_READ(host->base, HCTL)
1171 | SDVS30);
1172 OMAP_HSMMC_WRITE(host->base, HCTL,
1173 OMAP_HSMMC_READ(host->base, HCTL)
1174 | SDBP);
1175 }
1176
1177 clk_disable(host->fclk);
1178 clk_disable(host->iclk);
1179 clk_disable(host->dbclk);
1180 }
1181
1182 }
1183 return ret;
1184 }
1185
1186 /* Routine to resume the MMC device */
1187 static int omap_mmc_resume(struct platform_device *pdev)
1188 {
1189 int ret = 0;
1190 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1191
1192 if (host && !host->suspended)
1193 return 0;
1194
1195 if (host) {
1196
1197 ret = clk_enable(host->fclk);
1198 if (ret)
1199 goto clk_en_err;
1200
1201 ret = clk_enable(host->iclk);
1202 if (ret) {
1203 clk_disable(host->fclk);
1204 clk_put(host->fclk);
1205 goto clk_en_err;
1206 }
1207
1208 if (clk_enable(host->dbclk) != 0)
1209 dev_dbg(mmc_dev(host->mmc),
1210 "Enabling debounce clk failed\n");
1211
1212 if (host->pdata->resume) {
1213 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1214 if (ret)
1215 dev_dbg(mmc_dev(host->mmc),
1216 "Unmask interrupt failed\n");
1217 }
1218
1219 /* Notify the core to resume the host */
1220 ret = mmc_resume_host(host->mmc);
1221 if (ret == 0)
1222 host->suspended = 0;
1223 }
1224
1225 return ret;
1226
1227 clk_en_err:
1228 dev_dbg(mmc_dev(host->mmc),
1229 "Failed to enable MMC clocks during resume\n");
1230 return ret;
1231 }
1232
1233 #else
1234 #define omap_mmc_suspend NULL
1235 #define omap_mmc_resume NULL
1236 #endif
1237
1238 static struct platform_driver omap_mmc_driver = {
1239 .probe = omap_mmc_probe,
1240 .remove = omap_mmc_remove,
1241 .suspend = omap_mmc_suspend,
1242 .resume = omap_mmc_resume,
1243 .driver = {
1244 .name = DRIVER_NAME,
1245 .owner = THIS_MODULE,
1246 },
1247 };
1248
1249 static int __init omap_mmc_init(void)
1250 {
1251 /* Register the MMC driver */
1252 return platform_driver_register(&omap_mmc_driver);
1253 }
1254
1255 static void __exit omap_mmc_cleanup(void)
1256 {
1257 /* Unregister MMC driver */
1258 platform_driver_unregister(&omap_mmc_driver);
1259 }
1260
1261 module_init(omap_mmc_init);
1262 module_exit(omap_mmc_cleanup);
1263
1264 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1265 MODULE_LICENSE("GPL");
1266 MODULE_ALIAS("platform:" DRIVER_NAME);
1267 MODULE_AUTHOR("Texas Instruments Inc");
Linus' kernel tree