2 * adv7604 - Analog Devices ADV7604 video decoder driver
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/i2c.h>
35 #include <linux/delay.h>
36 #include <linux/videodev2.h>
37 #include <linux/workqueue.h>
38 #include <linux/v4l2-dv-timings.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-ctrls.h>
41 #include <media/v4l2-dv-timings.h>
42 #include <media/adv7604.h>
45 module_param(debug
, int, 0644);
46 MODULE_PARM_DESC(debug
, "debug level (0-2)");
48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51 MODULE_LICENSE("GPL");
53 /* ADV7604 system clock frequency */
54 #define ADV7604_fsc (28636360)
56 #define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
59 **********************************************************************
61 * Arrays with configuration parameters for the ADV7604
63 **********************************************************************
65 struct adv7604_state
{
66 struct adv7604_platform_data pdata
;
67 struct v4l2_subdev sd
;
69 struct v4l2_ctrl_handler hdl
;
70 enum adv7604_mode mode
;
71 struct v4l2_dv_timings timings
;
74 struct v4l2_fract aspect_ratio
;
75 u32 rgb_quantization_range
;
76 struct workqueue_struct
*work_queues
;
77 struct delayed_work delayed_work_enable_hotplug
;
79 bool restart_stdi_once
;
82 struct i2c_client
*i2c_avlink
;
83 struct i2c_client
*i2c_cec
;
84 struct i2c_client
*i2c_infoframe
;
85 struct i2c_client
*i2c_esdp
;
86 struct i2c_client
*i2c_dpp
;
87 struct i2c_client
*i2c_afe
;
88 struct i2c_client
*i2c_repeater
;
89 struct i2c_client
*i2c_edid
;
90 struct i2c_client
*i2c_hdmi
;
91 struct i2c_client
*i2c_test
;
92 struct i2c_client
*i2c_cp
;
93 struct i2c_client
*i2c_vdp
;
96 struct v4l2_ctrl
*detect_tx_5v_ctrl
;
97 struct v4l2_ctrl
*analog_sampling_phase_ctrl
;
98 struct v4l2_ctrl
*free_run_color_manual_ctrl
;
99 struct v4l2_ctrl
*free_run_color_ctrl
;
100 struct v4l2_ctrl
*rgb_quantization_range_ctrl
;
103 /* Supported CEA and DMT timings */
104 static const struct v4l2_dv_timings adv7604_timings
[] = {
105 V4L2_DV_BT_CEA_720X480P59_94
,
106 V4L2_DV_BT_CEA_720X576P50
,
107 V4L2_DV_BT_CEA_1280X720P24
,
108 V4L2_DV_BT_CEA_1280X720P25
,
109 V4L2_DV_BT_CEA_1280X720P50
,
110 V4L2_DV_BT_CEA_1280X720P60
,
111 V4L2_DV_BT_CEA_1920X1080P24
,
112 V4L2_DV_BT_CEA_1920X1080P25
,
113 V4L2_DV_BT_CEA_1920X1080P30
,
114 V4L2_DV_BT_CEA_1920X1080P50
,
115 V4L2_DV_BT_CEA_1920X1080P60
,
117 /* sorted by DMT ID */
118 V4L2_DV_BT_DMT_640X350P85
,
119 V4L2_DV_BT_DMT_640X400P85
,
120 V4L2_DV_BT_DMT_720X400P85
,
121 V4L2_DV_BT_DMT_640X480P60
,
122 V4L2_DV_BT_DMT_640X480P72
,
123 V4L2_DV_BT_DMT_640X480P75
,
124 V4L2_DV_BT_DMT_640X480P85
,
125 V4L2_DV_BT_DMT_800X600P56
,
126 V4L2_DV_BT_DMT_800X600P60
,
127 V4L2_DV_BT_DMT_800X600P72
,
128 V4L2_DV_BT_DMT_800X600P75
,
129 V4L2_DV_BT_DMT_800X600P85
,
130 V4L2_DV_BT_DMT_848X480P60
,
131 V4L2_DV_BT_DMT_1024X768P60
,
132 V4L2_DV_BT_DMT_1024X768P70
,
133 V4L2_DV_BT_DMT_1024X768P75
,
134 V4L2_DV_BT_DMT_1024X768P85
,
135 V4L2_DV_BT_DMT_1152X864P75
,
136 V4L2_DV_BT_DMT_1280X768P60_RB
,
137 V4L2_DV_BT_DMT_1280X768P60
,
138 V4L2_DV_BT_DMT_1280X768P75
,
139 V4L2_DV_BT_DMT_1280X768P85
,
140 V4L2_DV_BT_DMT_1280X800P60_RB
,
141 V4L2_DV_BT_DMT_1280X800P60
,
142 V4L2_DV_BT_DMT_1280X800P75
,
143 V4L2_DV_BT_DMT_1280X800P85
,
144 V4L2_DV_BT_DMT_1280X960P60
,
145 V4L2_DV_BT_DMT_1280X960P85
,
146 V4L2_DV_BT_DMT_1280X1024P60
,
147 V4L2_DV_BT_DMT_1280X1024P75
,
148 V4L2_DV_BT_DMT_1280X1024P85
,
149 V4L2_DV_BT_DMT_1360X768P60
,
150 V4L2_DV_BT_DMT_1400X1050P60_RB
,
151 V4L2_DV_BT_DMT_1400X1050P60
,
152 V4L2_DV_BT_DMT_1400X1050P75
,
153 V4L2_DV_BT_DMT_1400X1050P85
,
154 V4L2_DV_BT_DMT_1440X900P60_RB
,
155 V4L2_DV_BT_DMT_1440X900P60
,
156 V4L2_DV_BT_DMT_1600X1200P60
,
157 V4L2_DV_BT_DMT_1680X1050P60_RB
,
158 V4L2_DV_BT_DMT_1680X1050P60
,
159 V4L2_DV_BT_DMT_1792X1344P60
,
160 V4L2_DV_BT_DMT_1856X1392P60
,
161 V4L2_DV_BT_DMT_1920X1200P60_RB
,
162 V4L2_DV_BT_DMT_1366X768P60
,
163 V4L2_DV_BT_DMT_1920X1080P60
,
167 struct adv7604_video_standards
{
168 struct v4l2_dv_timings timings
;
173 /* sorted by number of lines */
174 static const struct adv7604_video_standards adv7604_prim_mode_comp
[] = {
175 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
176 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
177 { V4L2_DV_BT_CEA_1280X720P50
, 0x19, 0x01 },
178 { V4L2_DV_BT_CEA_1280X720P60
, 0x19, 0x00 },
179 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
180 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
181 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
182 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
183 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
184 /* TODO add 1920x1080P60_RB (CVT timing) */
188 /* sorted by number of lines */
189 static const struct adv7604_video_standards adv7604_prim_mode_gr
[] = {
190 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
204 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
205 { V4L2_DV_BT_DMT_1360X768P60
, 0x12, 0x00 },
206 { V4L2_DV_BT_DMT_1366X768P60
, 0x13, 0x00 },
207 { V4L2_DV_BT_DMT_1400X1050P60
, 0x14, 0x00 },
208 { V4L2_DV_BT_DMT_1400X1050P75
, 0x15, 0x00 },
209 { V4L2_DV_BT_DMT_1600X1200P60
, 0x16, 0x00 }, /* TODO not tested */
210 /* TODO add 1600X1200P60_RB (not a DMT timing) */
211 { V4L2_DV_BT_DMT_1680X1050P60
, 0x18, 0x00 },
212 { V4L2_DV_BT_DMT_1920X1200P60_RB
, 0x19, 0x00 }, /* TODO not tested */
216 /* sorted by number of lines */
217 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp
[] = {
218 { V4L2_DV_BT_CEA_720X480P59_94
, 0x0a, 0x00 },
219 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
220 { V4L2_DV_BT_CEA_1280X720P50
, 0x13, 0x01 },
221 { V4L2_DV_BT_CEA_1280X720P60
, 0x13, 0x00 },
222 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
223 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
224 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
225 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
226 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
230 /* sorted by number of lines */
231 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr
[] = {
232 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
233 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
234 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
236 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
237 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
241 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
242 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
245 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
246 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
250 /* ----------------------------------------------------------------------- */
252 static inline struct adv7604_state
*to_state(struct v4l2_subdev
*sd
)
254 return container_of(sd
, struct adv7604_state
, sd
);
257 static inline struct v4l2_subdev
*to_sd(struct v4l2_ctrl
*ctrl
)
259 return &container_of(ctrl
->handler
, struct adv7604_state
, hdl
)->sd
;
262 static inline unsigned hblanking(const struct v4l2_bt_timings
*t
)
264 return V4L2_DV_BT_BLANKING_WIDTH(t
);
267 static inline unsigned htotal(const struct v4l2_bt_timings
*t
)
269 return V4L2_DV_BT_FRAME_WIDTH(t
);
272 static inline unsigned vblanking(const struct v4l2_bt_timings
*t
)
274 return V4L2_DV_BT_BLANKING_HEIGHT(t
);
277 static inline unsigned vtotal(const struct v4l2_bt_timings
*t
)
279 return V4L2_DV_BT_FRAME_HEIGHT(t
);
282 /* ----------------------------------------------------------------------- */
284 static s32
adv_smbus_read_byte_data_check(struct i2c_client
*client
,
285 u8 command
, bool check
)
287 union i2c_smbus_data data
;
289 if (!i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
290 I2C_SMBUS_READ
, command
,
291 I2C_SMBUS_BYTE_DATA
, &data
))
294 v4l_err(client
, "error reading %02x, %02x\n",
295 client
->addr
, command
);
299 static s32
adv_smbus_read_byte_data(struct i2c_client
*client
, u8 command
)
301 return adv_smbus_read_byte_data_check(client
, command
, true);
304 static s32
adv_smbus_write_byte_data(struct i2c_client
*client
,
305 u8 command
, u8 value
)
307 union i2c_smbus_data data
;
312 for (i
= 0; i
< 3; i
++) {
313 err
= i2c_smbus_xfer(client
->adapter
, client
->addr
,
315 I2C_SMBUS_WRITE
, command
,
316 I2C_SMBUS_BYTE_DATA
, &data
);
321 v4l_err(client
, "error writing %02x, %02x, %02x\n",
322 client
->addr
, command
, value
);
326 static s32
adv_smbus_write_i2c_block_data(struct i2c_client
*client
,
327 u8 command
, unsigned length
, const u8
*values
)
329 union i2c_smbus_data data
;
331 if (length
> I2C_SMBUS_BLOCK_MAX
)
332 length
= I2C_SMBUS_BLOCK_MAX
;
333 data
.block
[0] = length
;
334 memcpy(data
.block
+ 1, values
, length
);
335 return i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
336 I2C_SMBUS_WRITE
, command
,
337 I2C_SMBUS_I2C_BLOCK_DATA
, &data
);
340 /* ----------------------------------------------------------------------- */
342 static inline int io_read(struct v4l2_subdev
*sd
, u8 reg
)
344 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
346 return adv_smbus_read_byte_data(client
, reg
);
349 static inline int io_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
351 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
353 return adv_smbus_write_byte_data(client
, reg
, val
);
356 static inline int io_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
358 return io_write(sd
, reg
, (io_read(sd
, reg
) & mask
) | val
);
361 static inline int avlink_read(struct v4l2_subdev
*sd
, u8 reg
)
363 struct adv7604_state
*state
= to_state(sd
);
365 return adv_smbus_read_byte_data(state
->i2c_avlink
, reg
);
368 static inline int avlink_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
370 struct adv7604_state
*state
= to_state(sd
);
372 return adv_smbus_write_byte_data(state
->i2c_avlink
, reg
, val
);
375 static inline int cec_read(struct v4l2_subdev
*sd
, u8 reg
)
377 struct adv7604_state
*state
= to_state(sd
);
379 return adv_smbus_read_byte_data(state
->i2c_cec
, reg
);
382 static inline int cec_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
384 struct adv7604_state
*state
= to_state(sd
);
386 return adv_smbus_write_byte_data(state
->i2c_cec
, reg
, val
);
389 static inline int cec_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
391 return cec_write(sd
, reg
, (cec_read(sd
, reg
) & mask
) | val
);
394 static inline int infoframe_read(struct v4l2_subdev
*sd
, u8 reg
)
396 struct adv7604_state
*state
= to_state(sd
);
398 return adv_smbus_read_byte_data(state
->i2c_infoframe
, reg
);
401 static inline int infoframe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
403 struct adv7604_state
*state
= to_state(sd
);
405 return adv_smbus_write_byte_data(state
->i2c_infoframe
, reg
, val
);
408 static inline int esdp_read(struct v4l2_subdev
*sd
, u8 reg
)
410 struct adv7604_state
*state
= to_state(sd
);
412 return adv_smbus_read_byte_data(state
->i2c_esdp
, reg
);
415 static inline int esdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
417 struct adv7604_state
*state
= to_state(sd
);
419 return adv_smbus_write_byte_data(state
->i2c_esdp
, reg
, val
);
422 static inline int dpp_read(struct v4l2_subdev
*sd
, u8 reg
)
424 struct adv7604_state
*state
= to_state(sd
);
426 return adv_smbus_read_byte_data(state
->i2c_dpp
, reg
);
429 static inline int dpp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
431 struct adv7604_state
*state
= to_state(sd
);
433 return adv_smbus_write_byte_data(state
->i2c_dpp
, reg
, val
);
436 static inline int afe_read(struct v4l2_subdev
*sd
, u8 reg
)
438 struct adv7604_state
*state
= to_state(sd
);
440 return adv_smbus_read_byte_data(state
->i2c_afe
, reg
);
443 static inline int afe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
445 struct adv7604_state
*state
= to_state(sd
);
447 return adv_smbus_write_byte_data(state
->i2c_afe
, reg
, val
);
450 static inline int rep_read(struct v4l2_subdev
*sd
, u8 reg
)
452 struct adv7604_state
*state
= to_state(sd
);
454 return adv_smbus_read_byte_data(state
->i2c_repeater
, reg
);
457 static inline int rep_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
459 struct adv7604_state
*state
= to_state(sd
);
461 return adv_smbus_write_byte_data(state
->i2c_repeater
, reg
, val
);
464 static inline int rep_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
466 return rep_write(sd
, reg
, (rep_read(sd
, reg
) & mask
) | val
);
469 static inline int edid_read(struct v4l2_subdev
*sd
, u8 reg
)
471 struct adv7604_state
*state
= to_state(sd
);
473 return adv_smbus_read_byte_data(state
->i2c_edid
, reg
);
476 static inline int edid_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
478 struct adv7604_state
*state
= to_state(sd
);
480 return adv_smbus_write_byte_data(state
->i2c_edid
, reg
, val
);
483 static inline int edid_read_block(struct v4l2_subdev
*sd
, unsigned len
, u8
*val
)
485 struct adv7604_state
*state
= to_state(sd
);
486 struct i2c_client
*client
= state
->i2c_edid
;
487 u8 msgbuf0
[1] = { 0 };
489 struct i2c_msg msg
[2] = {
491 .addr
= client
->addr
,
496 .addr
= client
->addr
,
503 if (i2c_transfer(client
->adapter
, msg
, 2) < 0)
505 memcpy(val
, msgbuf1
, len
);
509 static void adv7604_delayed_work_enable_hotplug(struct work_struct
*work
)
511 struct delayed_work
*dwork
= to_delayed_work(work
);
512 struct adv7604_state
*state
= container_of(dwork
, struct adv7604_state
,
513 delayed_work_enable_hotplug
);
514 struct v4l2_subdev
*sd
= &state
->sd
;
516 v4l2_dbg(2, debug
, sd
, "%s: enable hotplug\n", __func__
);
518 v4l2_subdev_notify(sd
, ADV7604_HOTPLUG
, (void *)1);
521 static inline int edid_write_block(struct v4l2_subdev
*sd
,
522 unsigned len
, const u8
*val
)
524 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
525 struct adv7604_state
*state
= to_state(sd
);
529 v4l2_dbg(2, debug
, sd
, "%s: write EDID block (%d byte)\n", __func__
, len
);
531 v4l2_subdev_notify(sd
, ADV7604_HOTPLUG
, (void *)0);
533 /* Disables I2C access to internal EDID ram from DDC port */
534 rep_write_and_or(sd
, 0x77, 0xf0, 0x0);
536 for (i
= 0; !err
&& i
< len
; i
+= I2C_SMBUS_BLOCK_MAX
)
537 err
= adv_smbus_write_i2c_block_data(state
->i2c_edid
, i
,
538 I2C_SMBUS_BLOCK_MAX
, val
+ i
);
542 /* adv7604 calculates the checksums and enables I2C access to internal
543 EDID ram from DDC port. */
544 rep_write_and_or(sd
, 0x77, 0xf0, 0x1);
546 for (i
= 0; i
< 1000; i
++) {
547 if (rep_read(sd
, 0x7d) & 1)
552 v4l_err(client
, "error enabling edid\n");
556 /* enable hotplug after 100 ms */
557 queue_delayed_work(state
->work_queues
,
558 &state
->delayed_work_enable_hotplug
, HZ
/ 10);
562 static inline int hdmi_read(struct v4l2_subdev
*sd
, u8 reg
)
564 struct adv7604_state
*state
= to_state(sd
);
566 return adv_smbus_read_byte_data(state
->i2c_hdmi
, reg
);
569 static inline int hdmi_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
571 struct adv7604_state
*state
= to_state(sd
);
573 return adv_smbus_write_byte_data(state
->i2c_hdmi
, reg
, val
);
576 static inline int test_read(struct v4l2_subdev
*sd
, u8 reg
)
578 struct adv7604_state
*state
= to_state(sd
);
580 return adv_smbus_read_byte_data(state
->i2c_test
, reg
);
583 static inline int test_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
585 struct adv7604_state
*state
= to_state(sd
);
587 return adv_smbus_write_byte_data(state
->i2c_test
, reg
, val
);
590 static inline int cp_read(struct v4l2_subdev
*sd
, u8 reg
)
592 struct adv7604_state
*state
= to_state(sd
);
594 return adv_smbus_read_byte_data(state
->i2c_cp
, reg
);
597 static inline int cp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
599 struct adv7604_state
*state
= to_state(sd
);
601 return adv_smbus_write_byte_data(state
->i2c_cp
, reg
, val
);
604 static inline int cp_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
606 return cp_write(sd
, reg
, (cp_read(sd
, reg
) & mask
) | val
);
609 static inline int vdp_read(struct v4l2_subdev
*sd
, u8 reg
)
611 struct adv7604_state
*state
= to_state(sd
);
613 return adv_smbus_read_byte_data(state
->i2c_vdp
, reg
);
616 static inline int vdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
618 struct adv7604_state
*state
= to_state(sd
);
620 return adv_smbus_write_byte_data(state
->i2c_vdp
, reg
, val
);
623 /* ----------------------------------------------------------------------- */
625 #ifdef CONFIG_VIDEO_ADV_DEBUG
626 static void adv7604_inv_register(struct v4l2_subdev
*sd
)
628 v4l2_info(sd
, "0x000-0x0ff: IO Map\n");
629 v4l2_info(sd
, "0x100-0x1ff: AVLink Map\n");
630 v4l2_info(sd
, "0x200-0x2ff: CEC Map\n");
631 v4l2_info(sd
, "0x300-0x3ff: InfoFrame Map\n");
632 v4l2_info(sd
, "0x400-0x4ff: ESDP Map\n");
633 v4l2_info(sd
, "0x500-0x5ff: DPP Map\n");
634 v4l2_info(sd
, "0x600-0x6ff: AFE Map\n");
635 v4l2_info(sd
, "0x700-0x7ff: Repeater Map\n");
636 v4l2_info(sd
, "0x800-0x8ff: EDID Map\n");
637 v4l2_info(sd
, "0x900-0x9ff: HDMI Map\n");
638 v4l2_info(sd
, "0xa00-0xaff: Test Map\n");
639 v4l2_info(sd
, "0xb00-0xbff: CP Map\n");
640 v4l2_info(sd
, "0xc00-0xcff: VDP Map\n");
643 static int adv7604_g_register(struct v4l2_subdev
*sd
,
644 struct v4l2_dbg_register
*reg
)
647 switch (reg
->reg
>> 8) {
649 reg
->val
= io_read(sd
, reg
->reg
& 0xff);
652 reg
->val
= avlink_read(sd
, reg
->reg
& 0xff);
655 reg
->val
= cec_read(sd
, reg
->reg
& 0xff);
658 reg
->val
= infoframe_read(sd
, reg
->reg
& 0xff);
661 reg
->val
= esdp_read(sd
, reg
->reg
& 0xff);
664 reg
->val
= dpp_read(sd
, reg
->reg
& 0xff);
667 reg
->val
= afe_read(sd
, reg
->reg
& 0xff);
670 reg
->val
= rep_read(sd
, reg
->reg
& 0xff);
673 reg
->val
= edid_read(sd
, reg
->reg
& 0xff);
676 reg
->val
= hdmi_read(sd
, reg
->reg
& 0xff);
679 reg
->val
= test_read(sd
, reg
->reg
& 0xff);
682 reg
->val
= cp_read(sd
, reg
->reg
& 0xff);
685 reg
->val
= vdp_read(sd
, reg
->reg
& 0xff);
688 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
689 adv7604_inv_register(sd
);
695 static int adv7604_s_register(struct v4l2_subdev
*sd
,
696 const struct v4l2_dbg_register
*reg
)
698 switch (reg
->reg
>> 8) {
700 io_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
703 avlink_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
706 cec_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
709 infoframe_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
712 esdp_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
715 dpp_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
718 afe_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
721 rep_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
724 edid_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
727 hdmi_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
730 test_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
733 cp_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
736 vdp_write(sd
, reg
->reg
& 0xff, reg
->val
& 0xff);
739 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
740 adv7604_inv_register(sd
);
747 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev
*sd
)
749 struct adv7604_state
*state
= to_state(sd
);
752 return v4l2_ctrl_s_ctrl(state
->detect_tx_5v_ctrl
,
753 ((io_read(sd
, 0x6f) & 0x10) >> 4));
756 static int find_and_set_predefined_video_timings(struct v4l2_subdev
*sd
,
758 const struct adv7604_video_standards
*predef_vid_timings
,
759 const struct v4l2_dv_timings
*timings
)
761 struct adv7604_state
*state
= to_state(sd
);
764 for (i
= 0; predef_vid_timings
[i
].timings
.bt
.width
; i
++) {
765 if (!v4l_match_dv_timings(timings
, &predef_vid_timings
[i
].timings
,
766 DIGITAL_INPUT
? 250000 : 1000000))
768 io_write(sd
, 0x00, predef_vid_timings
[i
].vid_std
); /* video std */
769 io_write(sd
, 0x01, (predef_vid_timings
[i
].v_freq
<< 4) +
770 prim_mode
); /* v_freq and prim mode */
777 static int configure_predefined_video_timings(struct v4l2_subdev
*sd
,
778 struct v4l2_dv_timings
*timings
)
780 struct adv7604_state
*state
= to_state(sd
);
783 v4l2_dbg(1, debug
, sd
, "%s", __func__
);
785 /* reset to default values */
786 io_write(sd
, 0x16, 0x43);
787 io_write(sd
, 0x17, 0x5a);
788 /* disable embedded syncs for auto graphics mode */
789 cp_write_and_or(sd
, 0x81, 0xef, 0x00);
790 cp_write(sd
, 0x8f, 0x00);
791 cp_write(sd
, 0x90, 0x00);
792 cp_write(sd
, 0xa2, 0x00);
793 cp_write(sd
, 0xa3, 0x00);
794 cp_write(sd
, 0xa4, 0x00);
795 cp_write(sd
, 0xa5, 0x00);
796 cp_write(sd
, 0xa6, 0x00);
797 cp_write(sd
, 0xa7, 0x00);
798 cp_write(sd
, 0xab, 0x00);
799 cp_write(sd
, 0xac, 0x00);
801 switch (state
->mode
) {
802 case ADV7604_MODE_COMP
:
803 case ADV7604_MODE_GR
:
804 err
= find_and_set_predefined_video_timings(sd
,
805 0x01, adv7604_prim_mode_comp
, timings
);
807 err
= find_and_set_predefined_video_timings(sd
,
808 0x02, adv7604_prim_mode_gr
, timings
);
810 case ADV7604_MODE_HDMI
:
811 err
= find_and_set_predefined_video_timings(sd
,
812 0x05, adv7604_prim_mode_hdmi_comp
, timings
);
814 err
= find_and_set_predefined_video_timings(sd
,
815 0x06, adv7604_prim_mode_hdmi_gr
, timings
);
818 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
819 __func__
, state
->mode
);
828 static void configure_custom_video_timings(struct v4l2_subdev
*sd
,
829 const struct v4l2_bt_timings
*bt
)
831 struct adv7604_state
*state
= to_state(sd
);
832 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
833 u32 width
= htotal(bt
);
834 u32 height
= vtotal(bt
);
835 u16 cp_start_sav
= bt
->hsync
+ bt
->hbackporch
- 4;
836 u16 cp_start_eav
= width
- bt
->hfrontporch
;
837 u16 cp_start_vbi
= height
- bt
->vfrontporch
;
838 u16 cp_end_vbi
= bt
->vsync
+ bt
->vbackporch
;
839 u16 ch1_fr_ll
= (((u32
)bt
->pixelclock
/ 100) > 0) ?
840 ((width
* (ADV7604_fsc
/ 100)) / ((u32
)bt
->pixelclock
/ 100)) : 0;
842 0xc0 | ((width
>> 8) & 0x1f),
846 v4l2_dbg(2, debug
, sd
, "%s\n", __func__
);
848 switch (state
->mode
) {
849 case ADV7604_MODE_COMP
:
850 case ADV7604_MODE_GR
:
852 io_write(sd
, 0x00, 0x07); /* video std */
853 io_write(sd
, 0x01, 0x02); /* prim mode */
854 /* enable embedded syncs for auto graphics mode */
855 cp_write_and_or(sd
, 0x81, 0xef, 0x10);
857 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
858 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
859 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
860 if (adv_smbus_write_i2c_block_data(client
, 0x16, 2, pll
)) {
861 v4l2_err(sd
, "writing to reg 0x16 and 0x17 failed\n");
865 /* active video - horizontal timing */
866 cp_write(sd
, 0xa2, (cp_start_sav
>> 4) & 0xff);
867 cp_write(sd
, 0xa3, ((cp_start_sav
& 0x0f) << 4) |
868 ((cp_start_eav
>> 8) & 0x0f));
869 cp_write(sd
, 0xa4, cp_start_eav
& 0xff);
871 /* active video - vertical timing */
872 cp_write(sd
, 0xa5, (cp_start_vbi
>> 4) & 0xff);
873 cp_write(sd
, 0xa6, ((cp_start_vbi
& 0xf) << 4) |
874 ((cp_end_vbi
>> 8) & 0xf));
875 cp_write(sd
, 0xa7, cp_end_vbi
& 0xff);
877 case ADV7604_MODE_HDMI
:
878 /* set default prim_mode/vid_std for HDMI
879 accoring to [REF_03, c. 4.2] */
880 io_write(sd
, 0x00, 0x02); /* video std */
881 io_write(sd
, 0x01, 0x06); /* prim mode */
884 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
885 __func__
, state
->mode
);
889 cp_write(sd
, 0x8f, (ch1_fr_ll
>> 8) & 0x7);
890 cp_write(sd
, 0x90, ch1_fr_ll
& 0xff);
891 cp_write(sd
, 0xab, (height
>> 4) & 0xff);
892 cp_write(sd
, 0xac, (height
& 0x0f) << 4);
895 static void set_rgb_quantization_range(struct v4l2_subdev
*sd
)
897 struct adv7604_state
*state
= to_state(sd
);
899 switch (state
->rgb_quantization_range
) {
900 case V4L2_DV_RGB_RANGE_AUTO
:
902 if (DIGITAL_INPUT
&& !(hdmi_read(sd
, 0x05) & 0x80)) {
903 /* receiving DVI-D signal */
905 /* ADV7604 selects RGB limited range regardless of
906 input format (CE/IT) in automatic mode */
907 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
) {
908 /* RGB limited range (16-235) */
909 io_write_and_or(sd
, 0x02, 0x0f, 0x00);
912 /* RGB full range (0-255) */
913 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
916 /* receiving HDMI or analog signal, set automode */
917 io_write_and_or(sd
, 0x02, 0x0f, 0xf0);
920 case V4L2_DV_RGB_RANGE_LIMITED
:
921 /* RGB limited range (16-235) */
922 io_write_and_or(sd
, 0x02, 0x0f, 0x00);
924 case V4L2_DV_RGB_RANGE_FULL
:
925 /* RGB full range (0-255) */
926 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
932 static int adv7604_s_ctrl(struct v4l2_ctrl
*ctrl
)
934 struct v4l2_subdev
*sd
= to_sd(ctrl
);
935 struct adv7604_state
*state
= to_state(sd
);
938 case V4L2_CID_BRIGHTNESS
:
939 cp_write(sd
, 0x3c, ctrl
->val
);
941 case V4L2_CID_CONTRAST
:
942 cp_write(sd
, 0x3a, ctrl
->val
);
944 case V4L2_CID_SATURATION
:
945 cp_write(sd
, 0x3b, ctrl
->val
);
948 cp_write(sd
, 0x3d, ctrl
->val
);
950 case V4L2_CID_DV_RX_RGB_RANGE
:
951 state
->rgb_quantization_range
= ctrl
->val
;
952 set_rgb_quantization_range(sd
);
954 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
:
955 /* Set the analog sampling phase. This is needed to find the
956 best sampling phase for analog video: an application or
957 driver has to try a number of phases and analyze the picture
958 quality before settling on the best performing phase. */
959 afe_write(sd
, 0xc8, ctrl
->val
);
961 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
:
962 /* Use the default blue color for free running mode,
963 or supply your own. */
964 cp_write_and_or(sd
, 0xbf, ~0x04, (ctrl
->val
<< 2));
966 case V4L2_CID_ADV_RX_FREE_RUN_COLOR
:
967 cp_write(sd
, 0xc0, (ctrl
->val
& 0xff0000) >> 16);
968 cp_write(sd
, 0xc1, (ctrl
->val
& 0x00ff00) >> 8);
969 cp_write(sd
, 0xc2, (u8
)(ctrl
->val
& 0x0000ff));
975 /* ----------------------------------------------------------------------- */
977 static inline bool no_power(struct v4l2_subdev
*sd
)
979 /* Entire chip or CP powered off */
980 return io_read(sd
, 0x0c) & 0x24;
983 static inline bool no_signal_tmds(struct v4l2_subdev
*sd
)
985 /* TODO port B, C and D */
986 return !(io_read(sd
, 0x6a) & 0x10);
989 static inline bool no_lock_tmds(struct v4l2_subdev
*sd
)
991 return (io_read(sd
, 0x6a) & 0xe0) != 0xe0;
994 static inline bool no_lock_sspd(struct v4l2_subdev
*sd
)
997 return ((cp_read(sd
, 0xb5) & 0xd0) != 0xd0);
1000 static inline bool no_lock_stdi(struct v4l2_subdev
*sd
)
1002 /* TODO channel 2 */
1003 return !(cp_read(sd
, 0xb1) & 0x80);
1006 static inline bool no_signal(struct v4l2_subdev
*sd
)
1008 struct adv7604_state
*state
= to_state(sd
);
1013 ret
|= no_lock_stdi(sd
);
1014 ret
|= no_lock_sspd(sd
);
1016 if (DIGITAL_INPUT
) {
1017 ret
|= no_lock_tmds(sd
);
1018 ret
|= no_signal_tmds(sd
);
1024 static inline bool no_lock_cp(struct v4l2_subdev
*sd
)
1026 /* CP has detected a non standard number of lines on the incoming
1027 video compared to what it is configured to receive by s_dv_timings */
1028 return io_read(sd
, 0x12) & 0x01;
1031 static int adv7604_g_input_status(struct v4l2_subdev
*sd
, u32
*status
)
1033 struct adv7604_state
*state
= to_state(sd
);
1036 *status
|= no_power(sd
) ? V4L2_IN_ST_NO_POWER
: 0;
1037 *status
|= no_signal(sd
) ? V4L2_IN_ST_NO_SIGNAL
: 0;
1039 *status
|= DIGITAL_INPUT
? V4L2_IN_ST_NO_SYNC
: V4L2_IN_ST_NO_H_LOCK
;
1041 v4l2_dbg(1, debug
, sd
, "%s: status = 0x%x\n", __func__
, *status
);
1046 /* ----------------------------------------------------------------------- */
1048 static void adv7604_print_timings(struct v4l2_subdev
*sd
,
1049 struct v4l2_dv_timings
*timings
, const char *txt
, bool detailed
)
1051 struct v4l2_bt_timings
*bt
= &timings
->bt
;
1054 if (timings
->type
!= V4L2_DV_BT_656_1120
)
1060 v4l2_info(sd
, "%s %dx%d%s%d (%dx%d)",
1061 txt
, bt
->width
, bt
->height
, bt
->interlaced
? "i" : "p",
1062 (htot
* vtot
) > 0 ? ((u32
)bt
->pixelclock
/
1067 v4l2_info(sd
, " horizontal: fp = %d, %ssync = %d, bp = %d\n",
1069 (bt
->polarities
& V4L2_DV_HSYNC_POS_POL
) ? "+" : "-",
1070 bt
->hsync
, bt
->hbackporch
);
1071 v4l2_info(sd
, " vertical: fp = %d, %ssync = %d, bp = %d\n",
1073 (bt
->polarities
& V4L2_DV_VSYNC_POS_POL
) ? "+" : "-",
1074 bt
->vsync
, bt
->vbackporch
);
1075 v4l2_info(sd
, " pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
1076 bt
->pixelclock
, bt
->flags
, bt
->standards
);
1080 struct stdi_readback
{
1086 static int stdi2dv_timings(struct v4l2_subdev
*sd
,
1087 struct stdi_readback
*stdi
,
1088 struct v4l2_dv_timings
*timings
)
1090 struct adv7604_state
*state
= to_state(sd
);
1091 u32 hfreq
= (ADV7604_fsc
* 8) / stdi
->bl
;
1095 for (i
= 0; adv7604_timings
[i
].bt
.height
; i
++) {
1096 if (vtotal(&adv7604_timings
[i
].bt
) != stdi
->lcf
+ 1)
1098 if (adv7604_timings
[i
].bt
.vsync
!= stdi
->lcvs
)
1101 pix_clk
= hfreq
* htotal(&adv7604_timings
[i
].bt
);
1103 if ((pix_clk
< adv7604_timings
[i
].bt
.pixelclock
+ 1000000) &&
1104 (pix_clk
> adv7604_timings
[i
].bt
.pixelclock
- 1000000)) {
1105 *timings
= adv7604_timings
[i
];
1110 if (v4l2_detect_cvt(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1111 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1112 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1115 if (v4l2_detect_gtf(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1116 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1117 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1118 state
->aspect_ratio
, timings
))
1121 v4l2_dbg(2, debug
, sd
,
1122 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1123 __func__
, stdi
->lcvs
, stdi
->lcf
, stdi
->bl
,
1124 stdi
->hs_pol
, stdi
->vs_pol
);
1128 static int read_stdi(struct v4l2_subdev
*sd
, struct stdi_readback
*stdi
)
1130 if (no_lock_stdi(sd
) || no_lock_sspd(sd
)) {
1131 v4l2_dbg(2, debug
, sd
, "%s: STDI and/or SSPD not locked\n", __func__
);
1136 stdi
->bl
= ((cp_read(sd
, 0xb1) & 0x3f) << 8) | cp_read(sd
, 0xb2);
1137 stdi
->lcf
= ((cp_read(sd
, 0xb3) & 0x7) << 8) | cp_read(sd
, 0xb4);
1138 stdi
->lcvs
= cp_read(sd
, 0xb3) >> 3;
1139 stdi
->interlaced
= io_read(sd
, 0x12) & 0x10;
1142 if ((cp_read(sd
, 0xb5) & 0x03) == 0x01) {
1143 stdi
->hs_pol
= ((cp_read(sd
, 0xb5) & 0x10) ?
1144 ((cp_read(sd
, 0xb5) & 0x08) ? '+' : '-') : 'x');
1145 stdi
->vs_pol
= ((cp_read(sd
, 0xb5) & 0x40) ?
1146 ((cp_read(sd
, 0xb5) & 0x20) ? '+' : '-') : 'x');
1152 if (no_lock_stdi(sd
) || no_lock_sspd(sd
)) {
1153 v4l2_dbg(2, debug
, sd
,
1154 "%s: signal lost during readout of STDI/SSPD\n", __func__
);
1158 if (stdi
->lcf
< 239 || stdi
->bl
< 8 || stdi
->bl
== 0x3fff) {
1159 v4l2_dbg(2, debug
, sd
, "%s: invalid signal\n", __func__
);
1160 memset(stdi
, 0, sizeof(struct stdi_readback
));
1164 v4l2_dbg(2, debug
, sd
,
1165 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1166 __func__
, stdi
->lcf
, stdi
->bl
, stdi
->lcvs
,
1167 stdi
->hs_pol
, stdi
->vs_pol
,
1168 stdi
->interlaced
? "interlaced" : "progressive");
1173 static int adv7604_enum_dv_timings(struct v4l2_subdev
*sd
,
1174 struct v4l2_enum_dv_timings
*timings
)
1176 if (timings
->index
>= ARRAY_SIZE(adv7604_timings
) - 1)
1178 memset(timings
->reserved
, 0, sizeof(timings
->reserved
));
1179 timings
->timings
= adv7604_timings
[timings
->index
];
1183 static int adv7604_dv_timings_cap(struct v4l2_subdev
*sd
,
1184 struct v4l2_dv_timings_cap
*cap
)
1186 struct adv7604_state
*state
= to_state(sd
);
1188 cap
->type
= V4L2_DV_BT_656_1120
;
1189 cap
->bt
.max_width
= 1920;
1190 cap
->bt
.max_height
= 1200;
1191 cap
->bt
.min_pixelclock
= 27000000;
1193 cap
->bt
.max_pixelclock
= 225000000;
1195 cap
->bt
.max_pixelclock
= 170000000;
1196 cap
->bt
.standards
= V4L2_DV_BT_STD_CEA861
| V4L2_DV_BT_STD_DMT
|
1197 V4L2_DV_BT_STD_GTF
| V4L2_DV_BT_STD_CVT
;
1198 cap
->bt
.capabilities
= V4L2_DV_BT_CAP_PROGRESSIVE
|
1199 V4L2_DV_BT_CAP_REDUCED_BLANKING
| V4L2_DV_BT_CAP_CUSTOM
;
1203 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1204 if the format is listed in adv7604_timings[] */
1205 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev
*sd
,
1206 struct v4l2_dv_timings
*timings
)
1208 struct adv7604_state
*state
= to_state(sd
);
1211 for (i
= 0; adv7604_timings
[i
].bt
.width
; i
++) {
1212 if (v4l_match_dv_timings(timings
, &adv7604_timings
[i
],
1213 DIGITAL_INPUT
? 250000 : 1000000)) {
1214 *timings
= adv7604_timings
[i
];
1220 static int adv7604_query_dv_timings(struct v4l2_subdev
*sd
,
1221 struct v4l2_dv_timings
*timings
)
1223 struct adv7604_state
*state
= to_state(sd
);
1224 struct v4l2_bt_timings
*bt
= &timings
->bt
;
1225 struct stdi_readback stdi
;
1230 memset(timings
, 0, sizeof(struct v4l2_dv_timings
));
1232 if (no_signal(sd
)) {
1233 v4l2_dbg(1, debug
, sd
, "%s: no valid signal\n", __func__
);
1238 if (read_stdi(sd
, &stdi
)) {
1239 v4l2_dbg(1, debug
, sd
, "%s: STDI/SSPD not locked\n", __func__
);
1242 bt
->interlaced
= stdi
.interlaced
?
1243 V4L2_DV_INTERLACED
: V4L2_DV_PROGRESSIVE
;
1245 if (DIGITAL_INPUT
) {
1246 timings
->type
= V4L2_DV_BT_656_1120
;
1248 bt
->width
= (hdmi_read(sd
, 0x07) & 0x0f) * 256 + hdmi_read(sd
, 0x08);
1249 bt
->height
= (hdmi_read(sd
, 0x09) & 0x0f) * 256 + hdmi_read(sd
, 0x0a);
1250 bt
->pixelclock
= (hdmi_read(sd
, 0x06) * 1000000) +
1251 ((hdmi_read(sd
, 0x3b) & 0x30) >> 4) * 250000;
1252 bt
->hfrontporch
= (hdmi_read(sd
, 0x20) & 0x03) * 256 +
1253 hdmi_read(sd
, 0x21);
1254 bt
->hsync
= (hdmi_read(sd
, 0x22) & 0x03) * 256 +
1255 hdmi_read(sd
, 0x23);
1256 bt
->hbackporch
= (hdmi_read(sd
, 0x24) & 0x03) * 256 +
1257 hdmi_read(sd
, 0x25);
1258 bt
->vfrontporch
= ((hdmi_read(sd
, 0x2a) & 0x1f) * 256 +
1259 hdmi_read(sd
, 0x2b)) / 2;
1260 bt
->vsync
= ((hdmi_read(sd
, 0x2e) & 0x1f) * 256 +
1261 hdmi_read(sd
, 0x2f)) / 2;
1262 bt
->vbackporch
= ((hdmi_read(sd
, 0x32) & 0x1f) * 256 +
1263 hdmi_read(sd
, 0x33)) / 2;
1264 bt
->polarities
= ((hdmi_read(sd
, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL
: 0) |
1265 ((hdmi_read(sd
, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL
: 0);
1266 if (bt
->interlaced
== V4L2_DV_INTERLACED
) {
1267 bt
->height
+= (hdmi_read(sd
, 0x0b) & 0x0f) * 256 +
1268 hdmi_read(sd
, 0x0c);
1269 bt
->il_vfrontporch
= ((hdmi_read(sd
, 0x2c) & 0x1f) * 256 +
1270 hdmi_read(sd
, 0x2d)) / 2;
1271 bt
->il_vsync
= ((hdmi_read(sd
, 0x30) & 0x1f) * 256 +
1272 hdmi_read(sd
, 0x31)) / 2;
1273 bt
->vbackporch
= ((hdmi_read(sd
, 0x34) & 0x1f) * 256 +
1274 hdmi_read(sd
, 0x35)) / 2;
1276 adv7604_fill_optional_dv_timings_fields(sd
, timings
);
1279 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1280 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1282 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1285 v4l2_dbg(1, debug
, sd
, "%s: lcvs + 1 = %d\n", __func__
, stdi
.lcvs
);
1286 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1289 v4l2_dbg(1, debug
, sd
, "%s: lcvs - 1 = %d\n", __func__
, stdi
.lcvs
);
1290 if (stdi2dv_timings(sd
, &stdi
, timings
)) {
1292 * The STDI block may measure wrong values, especially
1293 * for lcvs and lcf. If the driver can not find any
1294 * valid timing, the STDI block is restarted to measure
1295 * the video timings again. The function will return an
1296 * error, but the restart of STDI will generate a new
1297 * STDI interrupt and the format detection process will
1300 if (state
->restart_stdi_once
) {
1301 v4l2_dbg(1, debug
, sd
, "%s: restart STDI\n", __func__
);
1302 /* TODO restart STDI for Sync Channel 2 */
1303 /* enter one-shot mode */
1304 cp_write_and_or(sd
, 0x86, 0xf9, 0x00);
1305 /* trigger STDI restart */
1306 cp_write_and_or(sd
, 0x86, 0xf9, 0x04);
1307 /* reset to continuous mode */
1308 cp_write_and_or(sd
, 0x86, 0xf9, 0x02);
1309 state
->restart_stdi_once
= false;
1312 v4l2_dbg(1, debug
, sd
, "%s: format not supported\n", __func__
);
1315 state
->restart_stdi_once
= true;
1319 if (no_signal(sd
)) {
1320 v4l2_dbg(1, debug
, sd
, "%s: signal lost during readout\n", __func__
);
1321 memset(timings
, 0, sizeof(struct v4l2_dv_timings
));
1325 if ((!DIGITAL_INPUT
&& bt
->pixelclock
> 170000000) ||
1326 (DIGITAL_INPUT
&& bt
->pixelclock
> 225000000)) {
1327 v4l2_dbg(1, debug
, sd
, "%s: pixelclock out of range %d\n",
1328 __func__
, (u32
)bt
->pixelclock
);
1333 adv7604_print_timings(sd
, timings
,
1334 "adv7604_query_dv_timings:", true);
1339 static int adv7604_s_dv_timings(struct v4l2_subdev
*sd
,
1340 struct v4l2_dv_timings
*timings
)
1342 struct adv7604_state
*state
= to_state(sd
);
1343 struct v4l2_bt_timings
*bt
;
1351 if ((!DIGITAL_INPUT
&& bt
->pixelclock
> 170000000) ||
1352 (DIGITAL_INPUT
&& bt
->pixelclock
> 225000000)) {
1353 v4l2_dbg(1, debug
, sd
, "%s: pixelclock out of range %d\n",
1354 __func__
, (u32
)bt
->pixelclock
);
1358 adv7604_fill_optional_dv_timings_fields(sd
, timings
);
1360 state
->timings
= *timings
;
1362 cp_write(sd
, 0x91, bt
->interlaced
? 0x50 : 0x10);
1364 /* Use prim_mode and vid_std when available */
1365 err
= configure_predefined_video_timings(sd
, timings
);
1367 /* custom settings when the video format
1368 does not have prim_mode/vid_std */
1369 configure_custom_video_timings(sd
, bt
);
1372 set_rgb_quantization_range(sd
);
1376 adv7604_print_timings(sd
, timings
,
1377 "adv7604_s_dv_timings:", true);
1381 static int adv7604_g_dv_timings(struct v4l2_subdev
*sd
,
1382 struct v4l2_dv_timings
*timings
)
1384 struct adv7604_state
*state
= to_state(sd
);
1386 *timings
= state
->timings
;
1390 static void enable_input(struct v4l2_subdev
*sd
)
1392 struct adv7604_state
*state
= to_state(sd
);
1394 switch (state
->mode
) {
1395 case ADV7604_MODE_COMP
:
1396 case ADV7604_MODE_GR
:
1398 io_write(sd
, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1400 case ADV7604_MODE_HDMI
:
1402 hdmi_write(sd
, 0x1a, 0x0a); /* Unmute audio */
1403 hdmi_write(sd
, 0x01, 0x00); /* Enable HDMI clock terminators */
1404 io_write(sd
, 0x15, 0xa0); /* Disable Tristate of Pins */
1407 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
1408 __func__
, state
->mode
);
1413 static void disable_input(struct v4l2_subdev
*sd
)
1416 io_write(sd
, 0x15, 0xbe); /* Tristate all outputs from video core */
1417 hdmi_write(sd
, 0x1a, 0x1a); /* Mute audio */
1418 hdmi_write(sd
, 0x01, 0x78); /* Disable HDMI clock terminators */
1421 static void select_input(struct v4l2_subdev
*sd
)
1423 struct adv7604_state
*state
= to_state(sd
);
1425 switch (state
->mode
) {
1426 case ADV7604_MODE_COMP
:
1427 case ADV7604_MODE_GR
:
1428 /* reset ADI recommended settings for HDMI: */
1429 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1430 hdmi_write(sd
, 0x0d, 0x04); /* HDMI filter optimization */
1431 hdmi_write(sd
, 0x3d, 0x00); /* DDC bus active pull-up control */
1432 hdmi_write(sd
, 0x3e, 0x74); /* TMDS PLL optimization */
1433 hdmi_write(sd
, 0x4e, 0x3b); /* TMDS PLL optimization */
1434 hdmi_write(sd
, 0x57, 0x74); /* TMDS PLL optimization */
1435 hdmi_write(sd
, 0x58, 0x63); /* TMDS PLL optimization */
1436 hdmi_write(sd
, 0x8d, 0x18); /* equaliser */
1437 hdmi_write(sd
, 0x8e, 0x34); /* equaliser */
1438 hdmi_write(sd
, 0x93, 0x88); /* equaliser */
1439 hdmi_write(sd
, 0x94, 0x2e); /* equaliser */
1440 hdmi_write(sd
, 0x96, 0x00); /* enable automatic EQ changing */
1442 afe_write(sd
, 0x00, 0x08); /* power up ADC */
1443 afe_write(sd
, 0x01, 0x06); /* power up Analog Front End */
1444 afe_write(sd
, 0xc8, 0x00); /* phase control */
1446 /* set ADI recommended settings for digitizer */
1447 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1448 afe_write(sd
, 0x12, 0x7b); /* ADC noise shaping filter controls */
1449 afe_write(sd
, 0x0c, 0x1f); /* CP core gain controls */
1450 cp_write(sd
, 0x3e, 0x04); /* CP core pre-gain control */
1451 cp_write(sd
, 0xc3, 0x39); /* CP coast control. Graphics mode */
1452 cp_write(sd
, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1455 case ADV7604_MODE_HDMI
:
1456 /* set ADI recommended settings for HDMI: */
1457 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1458 hdmi_write(sd
, 0x0d, 0x84); /* HDMI filter optimization */
1459 hdmi_write(sd
, 0x3d, 0x10); /* DDC bus active pull-up control */
1460 hdmi_write(sd
, 0x3e, 0x39); /* TMDS PLL optimization */
1461 hdmi_write(sd
, 0x4e, 0x3b); /* TMDS PLL optimization */
1462 hdmi_write(sd
, 0x57, 0xb6); /* TMDS PLL optimization */
1463 hdmi_write(sd
, 0x58, 0x03); /* TMDS PLL optimization */
1464 hdmi_write(sd
, 0x8d, 0x18); /* equaliser */
1465 hdmi_write(sd
, 0x8e, 0x34); /* equaliser */
1466 hdmi_write(sd
, 0x93, 0x8b); /* equaliser */
1467 hdmi_write(sd
, 0x94, 0x2d); /* equaliser */
1468 hdmi_write(sd
, 0x96, 0x01); /* enable automatic EQ changing */
1470 afe_write(sd
, 0x00, 0xff); /* power down ADC */
1471 afe_write(sd
, 0x01, 0xfe); /* power down Analog Front End */
1472 afe_write(sd
, 0xc8, 0x40); /* phase control */
1474 /* reset ADI recommended settings for digitizer */
1475 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1476 afe_write(sd
, 0x12, 0xfb); /* ADC noise shaping filter controls */
1477 afe_write(sd
, 0x0c, 0x0d); /* CP core gain controls */
1478 cp_write(sd
, 0x3e, 0x00); /* CP core pre-gain control */
1479 cp_write(sd
, 0xc3, 0x39); /* CP coast control. Graphics mode */
1480 cp_write(sd
, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1484 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
1485 __func__
, state
->mode
);
1490 static int adv7604_s_routing(struct v4l2_subdev
*sd
,
1491 u32 input
, u32 output
, u32 config
)
1493 struct adv7604_state
*state
= to_state(sd
);
1495 v4l2_dbg(2, debug
, sd
, "%s: input %d", __func__
, input
);
1497 state
->mode
= input
;
1508 static int adv7604_enum_mbus_fmt(struct v4l2_subdev
*sd
, unsigned int index
,
1509 enum v4l2_mbus_pixelcode
*code
)
1513 /* Good enough for now */
1514 *code
= V4L2_MBUS_FMT_FIXED
;
1518 static int adv7604_g_mbus_fmt(struct v4l2_subdev
*sd
,
1519 struct v4l2_mbus_framefmt
*fmt
)
1521 struct adv7604_state
*state
= to_state(sd
);
1523 fmt
->width
= state
->timings
.bt
.width
;
1524 fmt
->height
= state
->timings
.bt
.height
;
1525 fmt
->code
= V4L2_MBUS_FMT_FIXED
;
1526 fmt
->field
= V4L2_FIELD_NONE
;
1527 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
) {
1528 fmt
->colorspace
= (state
->timings
.bt
.height
<= 576) ?
1529 V4L2_COLORSPACE_SMPTE170M
: V4L2_COLORSPACE_REC709
;
1534 static int adv7604_isr(struct v4l2_subdev
*sd
, u32 status
, bool *handled
)
1536 struct adv7604_state
*state
= to_state(sd
);
1537 u8 fmt_change
, fmt_change_digital
, tx_5v
;
1540 fmt_change
= io_read(sd
, 0x43) & 0x98;
1542 io_write(sd
, 0x44, fmt_change
);
1543 fmt_change_digital
= DIGITAL_INPUT
? (io_read(sd
, 0x6b) & 0xc0) : 0;
1544 if (fmt_change_digital
)
1545 io_write(sd
, 0x6c, fmt_change_digital
);
1546 if (fmt_change
|| fmt_change_digital
) {
1547 v4l2_dbg(1, debug
, sd
,
1548 "%s: ADV7604_FMT_CHANGE, fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1549 __func__
, fmt_change
, fmt_change_digital
);
1550 v4l2_subdev_notify(sd
, ADV7604_FMT_CHANGE
, NULL
);
1555 tx_5v
= io_read(sd
, 0x70) & 0x10;
1557 v4l2_dbg(1, debug
, sd
, "%s: tx_5v: 0x%x\n", __func__
, tx_5v
);
1558 io_write(sd
, 0x71, tx_5v
);
1559 adv7604_s_detect_tx_5v_ctrl(sd
);
1566 static int adv7604_get_edid(struct v4l2_subdev
*sd
, struct v4l2_subdev_edid
*edid
)
1568 struct adv7604_state
*state
= to_state(sd
);
1572 if (edid
->blocks
== 0)
1574 if (edid
->start_block
>= state
->edid_blocks
)
1576 if (edid
->start_block
+ edid
->blocks
> state
->edid_blocks
)
1577 edid
->blocks
= state
->edid_blocks
- edid
->start_block
;
1580 memcpy(edid
->edid
+ edid
->start_block
* 128,
1581 state
->edid
+ edid
->start_block
* 128,
1582 edid
->blocks
* 128);
1586 static int adv7604_set_edid(struct v4l2_subdev
*sd
, struct v4l2_subdev_edid
*edid
)
1588 struct adv7604_state
*state
= to_state(sd
);
1593 if (edid
->start_block
!= 0)
1595 if (edid
->blocks
== 0) {
1596 /* Pull down the hotplug pin */
1597 v4l2_subdev_notify(sd
, ADV7604_HOTPLUG
, (void *)0);
1598 /* Disables I2C access to internal EDID ram from DDC port */
1599 rep_write_and_or(sd
, 0x77, 0xf0, 0x0);
1600 state
->edid_blocks
= 0;
1601 /* Fall back to a 16:9 aspect ratio */
1602 state
->aspect_ratio
.numerator
= 16;
1603 state
->aspect_ratio
.denominator
= 9;
1606 if (edid
->blocks
> 2)
1610 memcpy(state
->edid
, edid
->edid
, 128 * edid
->blocks
);
1611 state
->edid_blocks
= edid
->blocks
;
1612 state
->aspect_ratio
= v4l2_calc_aspect_ratio(edid
->edid
[0x15],
1614 err
= edid_write_block(sd
, 128 * edid
->blocks
, state
->edid
);
1616 v4l2_err(sd
, "error %d writing edid\n", err
);
1620 /*********** avi info frame CEA-861-E **************/
1622 static void print_avi_infoframe(struct v4l2_subdev
*sd
)
1629 if (!(hdmi_read(sd
, 0x05) & 0x80)) {
1630 v4l2_info(sd
, "receive DVI-D signal (AVI infoframe not supported)\n");
1633 if (!(io_read(sd
, 0x60) & 0x01)) {
1634 v4l2_info(sd
, "AVI infoframe not received\n");
1638 if (io_read(sd
, 0x83) & 0x01) {
1639 v4l2_info(sd
, "AVI infoframe checksum error has occurred earlier\n");
1640 io_write(sd
, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1641 if (io_read(sd
, 0x83) & 0x01) {
1642 v4l2_info(sd
, "AVI infoframe checksum error still present\n");
1643 io_write(sd
, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1647 avi_len
= infoframe_read(sd
, 0xe2);
1648 avi_ver
= infoframe_read(sd
, 0xe1);
1649 v4l2_info(sd
, "AVI infoframe version %d (%d byte)\n",
1652 if (avi_ver
!= 0x02)
1655 for (i
= 0; i
< 14; i
++)
1656 buf
[i
] = infoframe_read(sd
, i
);
1659 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1660 buf
[0], buf
[1], buf
[2], buf
[3], buf
[4], buf
[5], buf
[6], buf
[7],
1661 buf
[8], buf
[9], buf
[10], buf
[11], buf
[12], buf
[13]);
1664 static int adv7604_log_status(struct v4l2_subdev
*sd
)
1666 struct adv7604_state
*state
= to_state(sd
);
1667 struct v4l2_dv_timings timings
;
1668 struct stdi_readback stdi
;
1669 u8 reg_io_0x02
= io_read(sd
, 0x02);
1671 char *csc_coeff_sel_rb
[16] = {
1672 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1673 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1674 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1675 "reserved", "reserved", "reserved", "reserved", "manual"
1677 char *input_color_space_txt
[16] = {
1678 "RGB limited range (16-235)", "RGB full range (0-255)",
1679 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1680 "XvYCC Bt.601", "XvYCC Bt.709",
1681 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1682 "invalid", "invalid", "invalid", "invalid", "invalid",
1683 "invalid", "invalid", "automatic"
1685 char *rgb_quantization_range_txt
[] = {
1687 "RGB limited range (16-235)",
1688 "RGB full range (0-255)",
1691 v4l2_info(sd
, "-----Chip status-----\n");
1692 v4l2_info(sd
, "Chip power: %s\n", no_power(sd
) ? "off" : "on");
1693 v4l2_info(sd
, "Connector type: %s\n", state
->connector_hdmi
?
1694 "HDMI" : (DIGITAL_INPUT
? "DVI-D" : "DVI-A"));
1695 v4l2_info(sd
, "EDID: %s\n", ((rep_read(sd
, 0x7d) & 0x01) &&
1696 (rep_read(sd
, 0x77) & 0x01)) ? "enabled" : "disabled ");
1697 v4l2_info(sd
, "CEC: %s\n", !!(cec_read(sd
, 0x2a) & 0x01) ?
1698 "enabled" : "disabled");
1700 v4l2_info(sd
, "-----Signal status-----\n");
1701 v4l2_info(sd
, "Cable detected (+5V power): %s\n",
1702 (io_read(sd
, 0x6f) & 0x10) ? "true" : "false");
1703 v4l2_info(sd
, "TMDS signal detected: %s\n",
1704 no_signal_tmds(sd
) ? "false" : "true");
1705 v4l2_info(sd
, "TMDS signal locked: %s\n",
1706 no_lock_tmds(sd
) ? "false" : "true");
1707 v4l2_info(sd
, "SSPD locked: %s\n", no_lock_sspd(sd
) ? "false" : "true");
1708 v4l2_info(sd
, "STDI locked: %s\n", no_lock_stdi(sd
) ? "false" : "true");
1709 v4l2_info(sd
, "CP locked: %s\n", no_lock_cp(sd
) ? "false" : "true");
1710 v4l2_info(sd
, "CP free run: %s\n",
1711 (!!(cp_read(sd
, 0xff) & 0x10) ? "on" : "off"));
1712 v4l2_info(sd
, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1713 io_read(sd
, 0x01) & 0x0f, io_read(sd
, 0x00) & 0x3f,
1714 (io_read(sd
, 0x01) & 0x70) >> 4);
1716 v4l2_info(sd
, "-----Video Timings-----\n");
1717 if (read_stdi(sd
, &stdi
))
1718 v4l2_info(sd
, "STDI: not locked\n");
1720 v4l2_info(sd
, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1721 stdi
.lcf
, stdi
.bl
, stdi
.lcvs
,
1722 stdi
.interlaced
? "interlaced" : "progressive",
1723 stdi
.hs_pol
, stdi
.vs_pol
);
1724 if (adv7604_query_dv_timings(sd
, &timings
))
1725 v4l2_info(sd
, "No video detected\n");
1727 adv7604_print_timings(sd
, &timings
, "Detected format:", true);
1728 adv7604_print_timings(sd
, &state
->timings
, "Configured format:", true);
1730 v4l2_info(sd
, "-----Color space-----\n");
1731 v4l2_info(sd
, "RGB quantization range ctrl: %s\n",
1732 rgb_quantization_range_txt
[state
->rgb_quantization_range
]);
1733 v4l2_info(sd
, "Input color space: %s\n",
1734 input_color_space_txt
[reg_io_0x02
>> 4]);
1735 v4l2_info(sd
, "Output color space: %s %s, saturator %s\n",
1736 (reg_io_0x02
& 0x02) ? "RGB" : "YCbCr",
1737 (reg_io_0x02
& 0x04) ? "(16-235)" : "(0-255)",
1738 ((reg_io_0x02
& 0x04) ^ (reg_io_0x02
& 0x01)) ?
1739 "enabled" : "disabled");
1740 v4l2_info(sd
, "Color space conversion: %s\n",
1741 csc_coeff_sel_rb
[cp_read(sd
, 0xfc) >> 4]);
1744 if (DIGITAL_INPUT
) {
1745 v4l2_info(sd
, "-----HDMI status-----\n");
1746 v4l2_info(sd
, "HDCP encrypted content: %s\n",
1747 hdmi_read(sd
, 0x05) & 0x40 ? "true" : "false");
1749 print_avi_infoframe(sd
);
1755 /* ----------------------------------------------------------------------- */
1757 static const struct v4l2_ctrl_ops adv7604_ctrl_ops
= {
1758 .s_ctrl
= adv7604_s_ctrl
,
1761 static const struct v4l2_subdev_core_ops adv7604_core_ops
= {
1762 .log_status
= adv7604_log_status
,
1763 .g_ext_ctrls
= v4l2_subdev_g_ext_ctrls
,
1764 .try_ext_ctrls
= v4l2_subdev_try_ext_ctrls
,
1765 .s_ext_ctrls
= v4l2_subdev_s_ext_ctrls
,
1766 .g_ctrl
= v4l2_subdev_g_ctrl
,
1767 .s_ctrl
= v4l2_subdev_s_ctrl
,
1768 .queryctrl
= v4l2_subdev_queryctrl
,
1769 .querymenu
= v4l2_subdev_querymenu
,
1770 .interrupt_service_routine
= adv7604_isr
,
1771 #ifdef CONFIG_VIDEO_ADV_DEBUG
1772 .g_register
= adv7604_g_register
,
1773 .s_register
= adv7604_s_register
,
1777 static const struct v4l2_subdev_video_ops adv7604_video_ops
= {
1778 .s_routing
= adv7604_s_routing
,
1779 .g_input_status
= adv7604_g_input_status
,
1780 .s_dv_timings
= adv7604_s_dv_timings
,
1781 .g_dv_timings
= adv7604_g_dv_timings
,
1782 .query_dv_timings
= adv7604_query_dv_timings
,
1783 .enum_dv_timings
= adv7604_enum_dv_timings
,
1784 .dv_timings_cap
= adv7604_dv_timings_cap
,
1785 .enum_mbus_fmt
= adv7604_enum_mbus_fmt
,
1786 .g_mbus_fmt
= adv7604_g_mbus_fmt
,
1787 .try_mbus_fmt
= adv7604_g_mbus_fmt
,
1788 .s_mbus_fmt
= adv7604_g_mbus_fmt
,
1791 static const struct v4l2_subdev_pad_ops adv7604_pad_ops
= {
1792 .get_edid
= adv7604_get_edid
,
1793 .set_edid
= adv7604_set_edid
,
1796 static const struct v4l2_subdev_ops adv7604_ops
= {
1797 .core
= &adv7604_core_ops
,
1798 .video
= &adv7604_video_ops
,
1799 .pad
= &adv7604_pad_ops
,
1802 /* -------------------------- custom ctrls ---------------------------------- */
1804 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase
= {
1805 .ops
= &adv7604_ctrl_ops
,
1806 .id
= V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
,
1807 .name
= "Analog Sampling Phase",
1808 .type
= V4L2_CTRL_TYPE_INTEGER
,
1815 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual
= {
1816 .ops
= &adv7604_ctrl_ops
,
1817 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
,
1818 .name
= "Free Running Color, Manual",
1819 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
1826 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color
= {
1827 .ops
= &adv7604_ctrl_ops
,
1828 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR
,
1829 .name
= "Free Running Color",
1830 .type
= V4L2_CTRL_TYPE_INTEGER
,
1837 /* ----------------------------------------------------------------------- */
1839 static int adv7604_core_init(struct v4l2_subdev
*sd
)
1841 struct adv7604_state
*state
= to_state(sd
);
1842 struct adv7604_platform_data
*pdata
= &state
->pdata
;
1844 hdmi_write(sd
, 0x48,
1845 (pdata
->disable_pwrdnb
? 0x80 : 0) |
1846 (pdata
->disable_cable_det_rst
? 0x40 : 0));
1851 io_write(sd
, 0x0c, 0x42); /* Power up part and power down VDP */
1852 io_write(sd
, 0x0b, 0x44); /* Power down ESDP block */
1853 cp_write(sd
, 0xcf, 0x01); /* Power down macrovision */
1856 io_write_and_or(sd
, 0x02, 0xf0,
1857 pdata
->alt_gamma
<< 3 |
1858 pdata
->op_656_range
<< 2 |
1859 pdata
->rgb_out
<< 1 |
1860 pdata
->alt_data_sat
<< 0);
1861 io_write(sd
, 0x03, pdata
->op_format_sel
);
1862 io_write_and_or(sd
, 0x04, 0x1f, pdata
->op_ch_sel
<< 5);
1863 io_write_and_or(sd
, 0x05, 0xf0, pdata
->blank_data
<< 3 |
1864 pdata
->insert_av_codes
<< 2 |
1865 pdata
->replicate_av_codes
<< 1 |
1866 pdata
->invert_cbcr
<< 0);
1868 /* TODO from platform data */
1869 cp_write(sd
, 0x69, 0x30); /* Enable CP CSC */
1870 io_write(sd
, 0x06, 0xa6); /* positive VS and HS */
1871 io_write(sd
, 0x14, 0x7f); /* Drive strength adjusted to max */
1872 cp_write(sd
, 0xba, (pdata
->hdmi_free_run_mode
<< 1) | 0x01); /* HDMI free run */
1873 cp_write(sd
, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1874 cp_write(sd
, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
1875 ADI recommended setting [REF_01, c. 2.3.3] */
1876 cp_write(sd
, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
1877 ADI recommended setting [REF_01, c. 2.3.3] */
1878 cp_write(sd
, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1879 for digital formats */
1881 /* TODO from platform data */
1882 afe_write(sd
, 0xb5, 0x01); /* Setting MCLK to 256Fs */
1884 afe_write(sd
, 0x02, pdata
->ain_sel
); /* Select analog input muxing mode */
1885 io_write_and_or(sd
, 0x30, ~(1 << 4), pdata
->output_bus_lsb_to_msb
<< 4);
1888 io_write(sd
, 0x40, 0xc2); /* Configure INT1 */
1889 io_write(sd
, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1890 io_write(sd
, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1891 io_write(sd
, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1892 io_write(sd
, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1894 return v4l2_ctrl_handler_setup(sd
->ctrl_handler
);
1897 static void adv7604_unregister_clients(struct adv7604_state
*state
)
1899 if (state
->i2c_avlink
)
1900 i2c_unregister_device(state
->i2c_avlink
);
1902 i2c_unregister_device(state
->i2c_cec
);
1903 if (state
->i2c_infoframe
)
1904 i2c_unregister_device(state
->i2c_infoframe
);
1905 if (state
->i2c_esdp
)
1906 i2c_unregister_device(state
->i2c_esdp
);
1908 i2c_unregister_device(state
->i2c_dpp
);
1910 i2c_unregister_device(state
->i2c_afe
);
1911 if (state
->i2c_repeater
)
1912 i2c_unregister_device(state
->i2c_repeater
);
1913 if (state
->i2c_edid
)
1914 i2c_unregister_device(state
->i2c_edid
);
1915 if (state
->i2c_hdmi
)
1916 i2c_unregister_device(state
->i2c_hdmi
);
1917 if (state
->i2c_test
)
1918 i2c_unregister_device(state
->i2c_test
);
1920 i2c_unregister_device(state
->i2c_cp
);
1922 i2c_unregister_device(state
->i2c_vdp
);
1925 static struct i2c_client
*adv7604_dummy_client(struct v4l2_subdev
*sd
,
1928 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
1931 io_write(sd
, io_reg
, addr
<< 1);
1932 return i2c_new_dummy(client
->adapter
, io_read(sd
, io_reg
) >> 1);
1935 static int adv7604_probe(struct i2c_client
*client
,
1936 const struct i2c_device_id
*id
)
1938 struct adv7604_state
*state
;
1939 struct adv7604_platform_data
*pdata
= client
->dev
.platform_data
;
1940 struct v4l2_ctrl_handler
*hdl
;
1941 struct v4l2_subdev
*sd
;
1944 /* Check if the adapter supports the needed features */
1945 if (!i2c_check_functionality(client
->adapter
, I2C_FUNC_SMBUS_BYTE_DATA
))
1947 v4l_dbg(1, debug
, client
, "detecting adv7604 client on address 0x%x\n",
1950 state
= devm_kzalloc(&client
->dev
, sizeof(*state
), GFP_KERNEL
);
1952 v4l_err(client
, "Could not allocate adv7604_state memory!\n");
1958 v4l_err(client
, "No platform data!\n");
1961 memcpy(&state
->pdata
, pdata
, sizeof(state
->pdata
));
1964 v4l2_i2c_subdev_init(sd
, client
, &adv7604_ops
);
1965 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
1966 state
->connector_hdmi
= pdata
->connector_hdmi
;
1968 /* i2c access to adv7604? */
1969 if (adv_smbus_read_byte_data_check(client
, 0xfb, false) != 0x68) {
1970 v4l2_info(sd
, "not an adv7604 on address 0x%x\n",
1975 /* control handlers */
1977 v4l2_ctrl_handler_init(hdl
, 9);
1979 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
1980 V4L2_CID_BRIGHTNESS
, -128, 127, 1, 0);
1981 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
1982 V4L2_CID_CONTRAST
, 0, 255, 1, 128);
1983 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
1984 V4L2_CID_SATURATION
, 0, 255, 1, 128);
1985 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
1986 V4L2_CID_HUE
, 0, 128, 1, 0);
1988 /* private controls */
1989 state
->detect_tx_5v_ctrl
= v4l2_ctrl_new_std(hdl
, NULL
,
1990 V4L2_CID_DV_RX_POWER_PRESENT
, 0, 1, 0, 0);
1991 state
->detect_tx_5v_ctrl
->is_private
= true;
1992 state
->rgb_quantization_range_ctrl
=
1993 v4l2_ctrl_new_std_menu(hdl
, &adv7604_ctrl_ops
,
1994 V4L2_CID_DV_RX_RGB_RANGE
, V4L2_DV_RGB_RANGE_FULL
,
1995 0, V4L2_DV_RGB_RANGE_AUTO
);
1996 state
->rgb_quantization_range_ctrl
->is_private
= true;
1998 /* custom controls */
1999 state
->analog_sampling_phase_ctrl
=
2000 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_analog_sampling_phase
, NULL
);
2001 state
->analog_sampling_phase_ctrl
->is_private
= true;
2002 state
->free_run_color_manual_ctrl
=
2003 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_free_run_color_manual
, NULL
);
2004 state
->free_run_color_manual_ctrl
->is_private
= true;
2005 state
->free_run_color_ctrl
=
2006 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_free_run_color
, NULL
);
2007 state
->free_run_color_ctrl
->is_private
= true;
2009 sd
->ctrl_handler
= hdl
;
2014 if (adv7604_s_detect_tx_5v_ctrl(sd
)) {
2019 state
->i2c_avlink
= adv7604_dummy_client(sd
, pdata
->i2c_avlink
, 0xf3);
2020 state
->i2c_cec
= adv7604_dummy_client(sd
, pdata
->i2c_cec
, 0xf4);
2021 state
->i2c_infoframe
= adv7604_dummy_client(sd
, pdata
->i2c_infoframe
, 0xf5);
2022 state
->i2c_esdp
= adv7604_dummy_client(sd
, pdata
->i2c_esdp
, 0xf6);
2023 state
->i2c_dpp
= adv7604_dummy_client(sd
, pdata
->i2c_dpp
, 0xf7);
2024 state
->i2c_afe
= adv7604_dummy_client(sd
, pdata
->i2c_afe
, 0xf8);
2025 state
->i2c_repeater
= adv7604_dummy_client(sd
, pdata
->i2c_repeater
, 0xf9);
2026 state
->i2c_edid
= adv7604_dummy_client(sd
, pdata
->i2c_edid
, 0xfa);
2027 state
->i2c_hdmi
= adv7604_dummy_client(sd
, pdata
->i2c_hdmi
, 0xfb);
2028 state
->i2c_test
= adv7604_dummy_client(sd
, pdata
->i2c_test
, 0xfc);
2029 state
->i2c_cp
= adv7604_dummy_client(sd
, pdata
->i2c_cp
, 0xfd);
2030 state
->i2c_vdp
= adv7604_dummy_client(sd
, pdata
->i2c_vdp
, 0xfe);
2031 if (!state
->i2c_avlink
|| !state
->i2c_cec
|| !state
->i2c_infoframe
||
2032 !state
->i2c_esdp
|| !state
->i2c_dpp
|| !state
->i2c_afe
||
2033 !state
->i2c_repeater
|| !state
->i2c_edid
|| !state
->i2c_hdmi
||
2034 !state
->i2c_test
|| !state
->i2c_cp
|| !state
->i2c_vdp
) {
2036 v4l2_err(sd
, "failed to create all i2c clients\n");
2039 state
->restart_stdi_once
= true;
2042 state
->work_queues
= create_singlethread_workqueue(client
->name
);
2043 if (!state
->work_queues
) {
2044 v4l2_err(sd
, "Could not create work queue\n");
2049 INIT_DELAYED_WORK(&state
->delayed_work_enable_hotplug
,
2050 adv7604_delayed_work_enable_hotplug
);
2052 state
->pad
.flags
= MEDIA_PAD_FL_SOURCE
;
2053 err
= media_entity_init(&sd
->entity
, 1, &state
->pad
, 0);
2055 goto err_work_queues
;
2057 err
= adv7604_core_init(sd
);
2060 v4l2_info(sd
, "%s found @ 0x%x (%s)\n", client
->name
,
2061 client
->addr
<< 1, client
->adapter
->name
);
2065 media_entity_cleanup(&sd
->entity
);
2067 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
2068 destroy_workqueue(state
->work_queues
);
2070 adv7604_unregister_clients(state
);
2072 v4l2_ctrl_handler_free(hdl
);
2076 /* ----------------------------------------------------------------------- */
2078 static int adv7604_remove(struct i2c_client
*client
)
2080 struct v4l2_subdev
*sd
= i2c_get_clientdata(client
);
2081 struct adv7604_state
*state
= to_state(sd
);
2083 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
2084 destroy_workqueue(state
->work_queues
);
2085 v4l2_device_unregister_subdev(sd
);
2086 media_entity_cleanup(&sd
->entity
);
2087 adv7604_unregister_clients(to_state(sd
));
2088 v4l2_ctrl_handler_free(sd
->ctrl_handler
);
2092 /* ----------------------------------------------------------------------- */
2094 static struct i2c_device_id adv7604_id
[] = {
2098 MODULE_DEVICE_TABLE(i2c
, adv7604_id
);
2100 static struct i2c_driver adv7604_driver
= {
2102 .owner
= THIS_MODULE
,
2105 .probe
= adv7604_probe
,
2106 .remove
= adv7604_remove
,
2107 .id_table
= adv7604_id
,
2110 module_i2c_driver(adv7604_driver
);