| blob | c61e0a41d799f061b712a09fbd6c6e53911e0564 |
1 config ARM
2 bool
3 default y
4 select ARCH_HAVE_CUSTOM_GPIO_H
5 select HAVE_AOUT
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
8 select HAVE_DMA_ATTRS
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
10 select HAVE_MEMBLOCK
11 select RTC_LIB
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
16 select HAVE_ARCH_KGDB
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
29 select HAVE_KERNEL_XZ
30 select HAVE_IRQ_WORK
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
44 select HAVE_BPF_JIT
45 select GENERIC_SMP_IDLE_THREAD
46 select KTIME_SCALAR
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
48 help
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
57 bool
59 config NEED_SG_DMA_LENGTH
60 bool
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
65 bool
67 config HAVE_PWM
68 bool
70 config MIGHT_HAVE_PCI
71 bool
73 config SYS_SUPPORTS_APM_EMULATION
74 bool
76 config GENERIC_GPIO
77 bool
79 config HAVE_TCM
80 bool
81 select GENERIC_ALLOCATOR
83 config HAVE_PROC_CPU
84 bool
86 config NO_IOPORT
87 bool
89 config EISA
90 bool
91 ---help---
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
102 Otherwise, say N.
104 config SBUS
105 bool
107 config STACKTRACE_SUPPORT
108 bool
109 default y
111 config HAVE_LATENCYTOP_SUPPORT
112 bool
113 depends on !SMP
114 default y
116 config LOCKDEP_SUPPORT
117 bool
118 default y
120 config TRACE_IRQFLAGS_SUPPORT
121 bool
122 default y
124 config GENERIC_LOCKBREAK
125 bool
126 default y
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
130 bool
131 default y
133 config RWSEM_XCHGADD_ALGORITHM
134 bool
136 config ARCH_HAS_ILOG2_U32
137 bool
139 config ARCH_HAS_ILOG2_U64
140 bool
142 config ARCH_HAS_CPUFREQ
143 bool
144 help
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
147 it.
149 config GENERIC_HWEIGHT
150 bool
151 default y
153 config GENERIC_CALIBRATE_DELAY
154 bool
155 default y
157 config ARCH_MAY_HAVE_PC_FDC
158 bool
160 config ZONE_DMA
161 bool
163 config NEED_DMA_MAP_STATE
164 def_bool y
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
167 bool
169 config GENERIC_ISA_DMA
170 bool
172 config FIQ
173 bool
175 config NEED_RET_TO_USER
176 bool
178 config ARCH_MTD_XIP
179 bool
181 config VECTORS_BASE
182 hex
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
185 default 0x00000000
186 help
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 default y
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
194 help
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
207 bool
208 help
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
214 bool
215 help
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
220 config PHYS_OFFSET
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
224 help
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
228 config GENERIC_BUG
229 def_bool y
230 depends on BUG
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
236 menu "System Type"
238 config MMU
239 bool "MMU-based Paged Memory Management Support"
240 default y
241 help
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
245 #
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
248 #
249 choice
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
255 select ARM_AMBA
256 select ARCH_HAS_CPUFREQ
257 select CLKDEV_LOOKUP
258 select HAVE_MACH_CLKDEV
259 select HAVE_TCM
260 select ICST
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
265 select SPARSE_IRQ
266 select MULTI_IRQ_HANDLER
267 help
268 Support for ARM's Integrator platform.
270 config ARCH_REALVIEW
271 bool "ARM Ltd. RealView family"
272 select ARM_AMBA
273 select CLKDEV_LOOKUP
274 select HAVE_MACH_CLKDEV
275 select ICST
276 select GENERIC_CLOCKEVENTS
277 select ARCH_WANT_OPTIONAL_GPIOLIB
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_CLCD
280 select ARM_TIMER_SP804
281 select GPIO_PL061 if GPIOLIB
282 select NEED_MACH_MEMORY_H
283 help
284 This enables support for ARM Ltd RealView boards.
286 config ARCH_VERSATILE
287 bool "ARM Ltd. Versatile family"
288 select ARM_AMBA
289 select ARM_VIC
290 select CLKDEV_LOOKUP
291 select HAVE_MACH_CLKDEV
292 select ICST
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
297 select PLAT_VERSATILE_FPGA_IRQ
298 select ARM_TIMER_SP804
299 help
300 This enables support for ARM Ltd Versatile board.
302 config ARCH_VEXPRESS
303 bool "ARM Ltd. Versatile Express family"
304 select ARCH_WANT_OPTIONAL_GPIOLIB
305 select ARM_AMBA
306 select ARM_TIMER_SP804
307 select CLKDEV_LOOKUP
308 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
310 select HAVE_CLK
311 select HAVE_PATA_PLATFORM
312 select ICST
313 select NO_IOPORT
314 select PLAT_VERSATILE
315 select PLAT_VERSATILE_CLCD
316 help
317 This enables support for the ARM Ltd Versatile Express boards.
319 config ARCH_AT91
320 bool "Atmel AT91"
321 select ARCH_REQUIRE_GPIOLIB
322 select HAVE_CLK
323 select CLKDEV_LOOKUP
324 select IRQ_DOMAIN
325 select NEED_MACH_IO_H if PCCARD
326 help
327 This enables support for systems based on Atmel
328 AT91RM9200 and AT91SAM9* processors.
330 config ARCH_BCMRING
331 bool "Broadcom BCMRING"
332 depends on MMU
333 select CPU_V6
334 select ARM_AMBA
335 select ARM_TIMER_SP804
336 select CLKDEV_LOOKUP
337 select GENERIC_CLOCKEVENTS
338 select ARCH_WANT_OPTIONAL_GPIOLIB
339 help
340 Support for Broadcom's BCMRing platform.
342 config ARCH_HIGHBANK
343 bool "Calxeda Highbank-based"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_AMBA
346 select ARM_GIC
347 select ARM_TIMER_SP804
348 select CACHE_L2X0
349 select CLKDEV_LOOKUP
350 select CPU_V7
351 select GENERIC_CLOCKEVENTS
352 select HAVE_ARM_SCU
353 select HAVE_SMP
354 select SPARSE_IRQ
355 select USE_OF
356 help
357 Support for the Calxeda Highbank SoC based boards.
359 config ARCH_CLPS711X
360 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
361 select CPU_ARM720T
362 select ARCH_USES_GETTIMEOFFSET
363 select NEED_MACH_MEMORY_H
364 help
365 Support for Cirrus Logic 711x/721x/731x based boards.
367 config ARCH_CNS3XXX
368 bool "Cavium Networks CNS3XXX family"
369 select CPU_V6K
370 select GENERIC_CLOCKEVENTS
371 select ARM_GIC
372 select MIGHT_HAVE_CACHE_L2X0
373 select MIGHT_HAVE_PCI
374 select PCI_DOMAINS if PCI
375 help
376 Support for Cavium Networks CNS3XXX platform.
378 config ARCH_GEMINI
379 bool "Cortina Systems Gemini"
380 select CPU_FA526
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
383 help
384 Support for the Cortina Systems Gemini family SoCs
386 config ARCH_PRIMA2
387 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
388 select CPU_V7
389 select NO_IOPORT
390 select GENERIC_CLOCKEVENTS
391 select CLKDEV_LOOKUP
392 select GENERIC_IRQ_CHIP
393 select MIGHT_HAVE_CACHE_L2X0
394 select PINCTRL
395 select PINCTRL_SIRF
396 select USE_OF
397 select ZONE_DMA
398 help
399 Support for CSR SiRFSoC ARM Cortex A9 Platform
401 config ARCH_EBSA110
402 bool "EBSA-110"
403 select CPU_SA110
404 select ISA
405 select NO_IOPORT
406 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
409 help
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
413 parallel port.
415 config ARCH_EP93XX
416 bool "EP93xx-based"
417 select CPU_ARM920T
418 select ARM_AMBA
419 select ARM_VIC
420 select CLKDEV_LOOKUP
421 select ARCH_REQUIRE_GPIOLIB
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
425 help
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
429 bool "FootBridge"
430 select CPU_SA110
431 select FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
433 select HAVE_IDE
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
436 help
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
440 config ARCH_MXC
441 bool "Freescale MXC/iMX-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
444 select CLKDEV_LOOKUP
445 select CLKSRC_MMIO
446 select GENERIC_IRQ_CHIP
447 select MULTI_IRQ_HANDLER
448 help
449 Support for Freescale MXC/iMX-based family of processors
451 config ARCH_MXS
452 bool "Freescale MXS-based"
453 select GENERIC_CLOCKEVENTS
454 select ARCH_REQUIRE_GPIOLIB
455 select CLKDEV_LOOKUP
456 select CLKSRC_MMIO
457 select COMMON_CLK
458 select HAVE_CLK_PREPARE
459 select PINCTRL
460 select USE_OF
461 help
462 Support for Freescale MXS-based family of processors
464 config ARCH_NETX
465 bool "Hilscher NetX based"
466 select CLKSRC_MMIO
467 select CPU_ARM926T
468 select ARM_VIC
469 select GENERIC_CLOCKEVENTS
470 help
471 This enables support for systems based on the Hilscher NetX Soc
473 config ARCH_H720X
474 bool "Hynix HMS720x-based"
475 select CPU_ARM720T
476 select ISA_DMA_API
477 select ARCH_USES_GETTIMEOFFSET
478 help
479 This enables support for systems based on the Hynix HMS720x
481 config ARCH_IOP13XX
482 bool "IOP13xx-based"
483 depends on MMU
484 select CPU_XSC3
485 select PLAT_IOP
486 select PCI
487 select ARCH_SUPPORTS_MSI
488 select VMSPLIT_1G
489 select NEED_MACH_MEMORY_H
490 select NEED_RET_TO_USER
491 help
492 Support for Intel's IOP13XX (XScale) family of processors.
494 config ARCH_IOP32X
495 bool "IOP32x-based"
496 depends on MMU
497 select CPU_XSCALE
498 select NEED_MACH_IO_H
499 select NEED_RET_TO_USER
500 select PLAT_IOP
501 select PCI
502 select ARCH_REQUIRE_GPIOLIB
503 help
504 Support for Intel's 80219 and IOP32X (XScale) family of
505 processors.
507 config ARCH_IOP33X
508 bool "IOP33x-based"
509 depends on MMU
510 select CPU_XSCALE
511 select NEED_MACH_IO_H
512 select NEED_RET_TO_USER
513 select PLAT_IOP
514 select PCI
515 select ARCH_REQUIRE_GPIOLIB
516 help
517 Support for Intel's IOP33X (XScale) family of processors.
519 config ARCH_IXP4XX
520 bool "IXP4xx-based"
521 depends on MMU
522 select ARCH_HAS_DMA_SET_COHERENT_MASK
523 select CLKSRC_MMIO
524 select CPU_XSCALE
525 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
527 select MIGHT_HAVE_PCI
528 select NEED_MACH_IO_H
529 select DMABOUNCE if PCI
530 help
531 Support for Intel's IXP4XX (XScale) family of processors.
533 config ARCH_DOVE
534 bool "Marvell Dove"
535 select CPU_V7
536 select PCI
537 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION
540 help
541 Support for the Marvell Dove SoC 88AP510
543 config ARCH_KIRKWOOD
544 bool "Marvell Kirkwood"
545 select CPU_FEROCEON
546 select PCI
547 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
549 select PLAT_ORION
550 help
551 Support for the following Marvell Kirkwood series SoCs:
552 88F6180, 88F6192 and 88F6281.
554 config ARCH_LPC32XX
555 bool "NXP LPC32XX"
556 select CLKSRC_MMIO
557 select CPU_ARM926T
558 select ARCH_REQUIRE_GPIOLIB
559 select HAVE_IDE
560 select ARM_AMBA
561 select USB_ARCH_HAS_OHCI
562 select CLKDEV_LOOKUP
563 select GENERIC_CLOCKEVENTS
564 select USE_OF
565 help
566 Support for the NXP LPC32XX family of processors
568 config ARCH_MV78XX0
569 bool "Marvell MV78xx0"
570 select CPU_FEROCEON
571 select PCI
572 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
574 select NEED_MACH_IO_H
575 select PLAT_ORION
576 help
577 Support for the following Marvell MV78xx0 series SoCs:
578 MV781x0, MV782x0.
580 config ARCH_ORION5X
581 bool "Marvell Orion"
582 depends on MMU
583 select CPU_FEROCEON
584 select PCI
585 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_CLOCKEVENTS
587 select PLAT_ORION
588 help
589 Support for the following Marvell Orion 5x series SoCs:
590 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
591 Orion-2 (5281), Orion-1-90 (6183).
593 config ARCH_MMP
594 bool "Marvell PXA168/910/MMP2"
595 depends on MMU
596 select ARCH_REQUIRE_GPIOLIB
597 select CLKDEV_LOOKUP
598 select GENERIC_CLOCKEVENTS
599 select GPIO_PXA
600 select IRQ_DOMAIN
601 select PLAT_PXA
602 select SPARSE_IRQ
603 select GENERIC_ALLOCATOR
604 help
605 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
607 config ARCH_KS8695
608 bool "Micrel/Kendin KS8695"
609 select CPU_ARM922T
610 select ARCH_REQUIRE_GPIOLIB
611 select ARCH_USES_GETTIMEOFFSET
612 select NEED_MACH_MEMORY_H
613 help
614 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
615 System-on-Chip devices.
617 config ARCH_W90X900
618 bool "Nuvoton W90X900 CPU"
619 select CPU_ARM926T
620 select ARCH_REQUIRE_GPIOLIB
621 select CLKDEV_LOOKUP
622 select CLKSRC_MMIO
623 select GENERIC_CLOCKEVENTS
624 help
625 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
626 At present, the w90x900 has been renamed nuc900, regarding
627 the ARM series product line, you can login the following
628 link address to know more.
630 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
631 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
633 config ARCH_TEGRA
634 bool "NVIDIA Tegra"
635 select CLKDEV_LOOKUP
636 select CLKSRC_MMIO
637 select GENERIC_CLOCKEVENTS
638 select GENERIC_GPIO
639 select HAVE_CLK
640 select HAVE_SMP
641 select MIGHT_HAVE_CACHE_L2X0
642 select ARCH_HAS_CPUFREQ
643 help
644 This enables support for NVIDIA Tegra based systems (Tegra APX,
645 Tegra 6xx and Tegra 2 series).
647 config ARCH_PICOXCELL
648 bool "Picochip picoXcell"
649 select ARCH_REQUIRE_GPIOLIB
650 select ARM_PATCH_PHYS_VIRT
651 select ARM_VIC
652 select CPU_V6K
653 select DW_APB_TIMER
654 select GENERIC_CLOCKEVENTS
655 select GENERIC_GPIO
656 select HAVE_TCM
657 select NO_IOPORT
658 select SPARSE_IRQ
659 select USE_OF
660 help
661 This enables support for systems based on the Picochip picoXcell
662 family of Femtocell devices. The picoxcell support requires device tree
663 for all boards.
665 config ARCH_PNX4008
666 bool "Philips Nexperia PNX4008 Mobile"
667 select CPU_ARM926T
668 select CLKDEV_LOOKUP
669 select ARCH_USES_GETTIMEOFFSET
670 help
671 This enables support for Philips PNX4008 mobile platform.
673 config ARCH_PXA
674 bool "PXA2xx/PXA3xx-based"
675 depends on MMU
676 select ARCH_MTD_XIP
677 select ARCH_HAS_CPUFREQ
678 select CLKDEV_LOOKUP
679 select CLKSRC_MMIO
680 select ARCH_REQUIRE_GPIOLIB
681 select GENERIC_CLOCKEVENTS
682 select GPIO_PXA
683 select PLAT_PXA
684 select SPARSE_IRQ
685 select AUTO_ZRELADDR
686 select MULTI_IRQ_HANDLER
687 select ARM_CPU_SUSPEND if PM
688 select HAVE_IDE
689 help
690 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
692 config ARCH_MSM
693 bool "Qualcomm MSM"
694 select HAVE_CLK
695 select GENERIC_CLOCKEVENTS
696 select ARCH_REQUIRE_GPIOLIB
697 select CLKDEV_LOOKUP
698 help
699 Support for Qualcomm MSM/QSD based systems. This runs on the
700 apps processor of the MSM/QSD and depends on a shared memory
701 interface to the modem processor which runs the baseband
702 stack and controls some vital subsystems
703 (clock and power control, etc).
705 config ARCH_SHMOBILE
706 bool "Renesas SH-Mobile / R-Mobile"
707 select HAVE_CLK
708 select CLKDEV_LOOKUP
709 select HAVE_MACH_CLKDEV
710 select HAVE_SMP
711 select GENERIC_CLOCKEVENTS
712 select MIGHT_HAVE_CACHE_L2X0
713 select NO_IOPORT
714 select SPARSE_IRQ
715 select MULTI_IRQ_HANDLER
716 select PM_GENERIC_DOMAINS if PM
717 select NEED_MACH_MEMORY_H
718 help
719 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
721 config ARCH_RPC
722 bool "RiscPC"
723 select ARCH_ACORN
724 select FIQ
725 select ARCH_MAY_HAVE_PC_FDC
726 select HAVE_PATA_PLATFORM
727 select ISA_DMA_API
728 select NO_IOPORT
729 select ARCH_SPARSEMEM_ENABLE
730 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_IDE
732 select NEED_MACH_IO_H
733 select NEED_MACH_MEMORY_H
734 help
735 On the Acorn Risc-PC, Linux can support the internal IDE disk and
736 CD-ROM interface, serial and parallel port, and the floppy drive.
738 config ARCH_SA1100
739 bool "SA1100-based"
740 select CLKSRC_MMIO
741 select CPU_SA1100
742 select ISA
743 select ARCH_SPARSEMEM_ENABLE
744 select ARCH_MTD_XIP
745 select ARCH_HAS_CPUFREQ
746 select CPU_FREQ
747 select GENERIC_CLOCKEVENTS
748 select CLKDEV_LOOKUP
749 select ARCH_REQUIRE_GPIOLIB
750 select HAVE_IDE
751 select NEED_MACH_MEMORY_H
752 select SPARSE_IRQ
753 help
754 Support for StrongARM 11x0 based boards.
756 config ARCH_S3C24XX
757 bool "Samsung S3C24XX SoCs"
758 select GENERIC_GPIO
759 select ARCH_HAS_CPUFREQ
760 select HAVE_CLK
761 select CLKDEV_LOOKUP
762 select ARCH_USES_GETTIMEOFFSET
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C_RTC if RTC_CLASS
765 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 select NEED_MACH_IO_H
767 help
768 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
769 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
770 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
771 Samsung SMDK2410 development board (and derivatives).
773 config ARCH_S3C64XX
774 bool "Samsung S3C64XX"
775 select PLAT_SAMSUNG
776 select CPU_V6
777 select ARM_VIC
778 select HAVE_CLK
779 select HAVE_TCM
780 select CLKDEV_LOOKUP
781 select NO_IOPORT
782 select ARCH_USES_GETTIMEOFFSET
783 select ARCH_HAS_CPUFREQ
784 select ARCH_REQUIRE_GPIOLIB
785 select SAMSUNG_CLKSRC
786 select SAMSUNG_IRQ_VIC_TIMER
787 select S3C_GPIO_TRACK
788 select S3C_DEV_NAND
789 select USB_ARCH_HAS_OHCI
790 select SAMSUNG_GPIOLIB_4BIT
791 select HAVE_S3C2410_I2C if I2C
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 help
794 Samsung S3C64XX series based systems
796 config ARCH_S5P64X0
797 bool "Samsung S5P6440 S5P6450"
798 select CPU_V6
799 select GENERIC_GPIO
800 select HAVE_CLK
801 select CLKDEV_LOOKUP
802 select CLKSRC_MMIO
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select GENERIC_CLOCKEVENTS
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C_RTC if RTC_CLASS
807 help
808 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
809 SMDK6450.
811 config ARCH_S5PC100
812 bool "Samsung S5PC100"
813 select GENERIC_GPIO
814 select HAVE_CLK
815 select CLKDEV_LOOKUP
816 select CPU_V7
817 select ARCH_USES_GETTIMEOFFSET
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C_RTC if RTC_CLASS
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 help
822 Samsung S5PC100 series based systems
824 config ARCH_S5PV210
825 bool "Samsung S5PV210/S5PC110"
826 select CPU_V7
827 select ARCH_SPARSEMEM_ENABLE
828 select ARCH_HAS_HOLES_MEMORYMODEL
829 select GENERIC_GPIO
830 select HAVE_CLK
831 select CLKDEV_LOOKUP
832 select CLKSRC_MMIO
833 select ARCH_HAS_CPUFREQ
834 select GENERIC_CLOCKEVENTS
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C_RTC if RTC_CLASS
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
838 select NEED_MACH_MEMORY_H
839 help
840 Samsung S5PV210/S5PC110 series based systems
842 config ARCH_EXYNOS
843 bool "SAMSUNG EXYNOS"
844 select CPU_V7
845 select ARCH_SPARSEMEM_ENABLE
846 select ARCH_HAS_HOLES_MEMORYMODEL
847 select GENERIC_GPIO
848 select HAVE_CLK
849 select CLKDEV_LOOKUP
850 select ARCH_HAS_CPUFREQ
851 select GENERIC_CLOCKEVENTS
852 select HAVE_S3C_RTC if RTC_CLASS
853 select HAVE_S3C2410_I2C if I2C
854 select HAVE_S3C2410_WATCHDOG if WATCHDOG
855 select NEED_MACH_MEMORY_H
856 help
857 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
859 config ARCH_SHARK
860 bool "Shark"
861 select CPU_SA110
862 select ISA
863 select ISA_DMA
864 select ZONE_DMA
865 select PCI
866 select ARCH_USES_GETTIMEOFFSET
867 select NEED_MACH_MEMORY_H
868 help
869 Support for the StrongARM based Digital DNARD machine, also known
870 as "Shark" (<http://www.shark-linux.de/shark.html>).
872 config ARCH_U300
873 bool "ST-Ericsson U300 Series"
874 depends on MMU
875 select CLKSRC_MMIO
876 select CPU_ARM926T
877 select HAVE_TCM
878 select ARM_AMBA
879 select ARM_PATCH_PHYS_VIRT
880 select ARM_VIC
881 select GENERIC_CLOCKEVENTS
882 select CLKDEV_LOOKUP
883 select HAVE_MACH_CLKDEV
884 select GENERIC_GPIO
885 select ARCH_REQUIRE_GPIOLIB
886 help
887 Support for ST-Ericsson U300 series mobile platforms.
889 config ARCH_U8500
890 bool "ST-Ericsson U8500 Series"
891 depends on MMU
892 select CPU_V7
893 select ARM_AMBA
894 select GENERIC_CLOCKEVENTS
895 select CLKDEV_LOOKUP
896 select ARCH_REQUIRE_GPIOLIB
897 select ARCH_HAS_CPUFREQ
898 select HAVE_SMP
899 select MIGHT_HAVE_CACHE_L2X0
900 help
901 Support for ST-Ericsson's Ux500 architecture
903 config ARCH_NOMADIK
904 bool "STMicroelectronics Nomadik"
905 select ARM_AMBA
906 select ARM_VIC
907 select CPU_ARM926T
908 select CLKDEV_LOOKUP
909 select GENERIC_CLOCKEVENTS
910 select PINCTRL
911 select MIGHT_HAVE_CACHE_L2X0
912 select ARCH_REQUIRE_GPIOLIB
913 help
914 Support for the Nomadik platform by ST-Ericsson
916 config ARCH_DAVINCI
917 bool "TI DaVinci"
918 select GENERIC_CLOCKEVENTS
919 select ARCH_REQUIRE_GPIOLIB
920 select ZONE_DMA
921 select HAVE_IDE
922 select CLKDEV_LOOKUP
923 select GENERIC_ALLOCATOR
924 select GENERIC_IRQ_CHIP
925 select ARCH_HAS_HOLES_MEMORYMODEL
926 help
927 Support for TI's DaVinci platform.
929 config ARCH_OMAP
930 bool "TI OMAP"
931 select HAVE_CLK
932 select ARCH_REQUIRE_GPIOLIB
933 select ARCH_HAS_CPUFREQ
934 select CLKSRC_MMIO
935 select GENERIC_CLOCKEVENTS
936 select ARCH_HAS_HOLES_MEMORYMODEL
937 help
938 Support for TI's OMAP platform (OMAP1/2/3/4).
940 config PLAT_SPEAR
941 bool "ST SPEAr"
942 select ARM_AMBA
943 select ARCH_REQUIRE_GPIOLIB
944 select CLKDEV_LOOKUP
945 select COMMON_CLK
946 select CLKSRC_MMIO
947 select GENERIC_CLOCKEVENTS
948 select HAVE_CLK
949 help
950 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
952 config ARCH_VT8500
953 bool "VIA/WonderMedia 85xx"
954 select CPU_ARM926T
955 select GENERIC_GPIO
956 select ARCH_HAS_CPUFREQ
957 select GENERIC_CLOCKEVENTS
958 select ARCH_REQUIRE_GPIOLIB
959 select HAVE_PWM
960 help
961 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
963 config ARCH_ZYNQ
964 bool "Xilinx Zynq ARM Cortex A9 Platform"
965 select CPU_V7
966 select GENERIC_CLOCKEVENTS
967 select CLKDEV_LOOKUP
968 select ARM_GIC
969 select ARM_AMBA
970 select ICST
971 select MIGHT_HAVE_CACHE_L2X0
972 select USE_OF
973 help
974 Support for Xilinx Zynq ARM Cortex A9 Platform
975 endchoice
977 #
978 # This is sorted alphabetically by mach-* pathname. However, plat-*
979 # Kconfigs may be included either alphabetically (according to the
980 # plat- suffix) or along side the corresponding mach-* source.
981 #
982 source "arch/arm/mach-at91/Kconfig"
984 source "arch/arm/mach-bcmring/Kconfig"
986 source "arch/arm/mach-clps711x/Kconfig"
988 source "arch/arm/mach-cns3xxx/Kconfig"
990 source "arch/arm/mach-davinci/Kconfig"
992 source "arch/arm/mach-dove/Kconfig"
994 source "arch/arm/mach-ep93xx/Kconfig"
996 source "arch/arm/mach-footbridge/Kconfig"
998 source "arch/arm/mach-gemini/Kconfig"
1000 source "arch/arm/mach-h720x/Kconfig"
1002 source "arch/arm/mach-integrator/Kconfig"
1004 source "arch/arm/mach-iop32x/Kconfig"
1006 source "arch/arm/mach-iop33x/Kconfig"
1008 source "arch/arm/mach-iop13xx/Kconfig"
1010 source "arch/arm/mach-ixp4xx/Kconfig"
1012 source "arch/arm/mach-kirkwood/Kconfig"
1014 source "arch/arm/mach-ks8695/Kconfig"
1016 source "arch/arm/mach-lpc32xx/Kconfig"
1018 source "arch/arm/mach-msm/Kconfig"
1020 source "arch/arm/mach-mv78xx0/Kconfig"
1022 source "arch/arm/plat-mxc/Kconfig"
1024 source "arch/arm/mach-mxs/Kconfig"
1026 source "arch/arm/mach-netx/Kconfig"
1028 source "arch/arm/mach-nomadik/Kconfig"
1029 source "arch/arm/plat-nomadik/Kconfig"
1031 source "arch/arm/plat-omap/Kconfig"
1033 source "arch/arm/mach-omap1/Kconfig"
1035 source "arch/arm/mach-omap2/Kconfig"
1037 source "arch/arm/mach-orion5x/Kconfig"
1039 source "arch/arm/mach-pxa/Kconfig"
1040 source "arch/arm/plat-pxa/Kconfig"
1042 source "arch/arm/mach-mmp/Kconfig"
1044 source "arch/arm/mach-realview/Kconfig"
1046 source "arch/arm/mach-sa1100/Kconfig"
1048 source "arch/arm/plat-samsung/Kconfig"
1049 source "arch/arm/plat-s3c24xx/Kconfig"
1051 source "arch/arm/plat-spear/Kconfig"
1053 source "arch/arm/mach-s3c24xx/Kconfig"
1054 if ARCH_S3C24XX
1055 source "arch/arm/mach-s3c2412/Kconfig"
1056 source "arch/arm/mach-s3c2440/Kconfig"
1057 endif
1059 if ARCH_S3C64XX
1060 source "arch/arm/mach-s3c64xx/Kconfig"
1061 endif
1063 source "arch/arm/mach-s5p64x0/Kconfig"
1065 source "arch/arm/mach-s5pc100/Kconfig"
1067 source "arch/arm/mach-s5pv210/Kconfig"
1069 source "arch/arm/mach-exynos/Kconfig"
1071 source "arch/arm/mach-shmobile/Kconfig"
1073 source "arch/arm/mach-tegra/Kconfig"
1075 source "arch/arm/mach-u300/Kconfig"
1077 source "arch/arm/mach-ux500/Kconfig"
1079 source "arch/arm/mach-versatile/Kconfig"
1081 source "arch/arm/mach-vexpress/Kconfig"
1082 source "arch/arm/plat-versatile/Kconfig"
1084 source "arch/arm/mach-vt8500/Kconfig"
1086 source "arch/arm/mach-w90x900/Kconfig"
1088 # Definitions to make life easier
1089 config ARCH_ACORN
1090 bool
1092 config PLAT_IOP
1093 bool
1094 select GENERIC_CLOCKEVENTS
1096 config PLAT_ORION
1097 bool
1098 select CLKSRC_MMIO
1099 select GENERIC_IRQ_CHIP
1100 select COMMON_CLK
1102 config PLAT_PXA
1103 bool
1105 config PLAT_VERSATILE
1106 bool
1108 config ARM_TIMER_SP804
1109 bool
1110 select CLKSRC_MMIO
1111 select HAVE_SCHED_CLOCK
1113 source arch/arm/mm/Kconfig
1115 config ARM_NR_BANKS
1116 int
1117 default 16 if ARCH_EP93XX
1118 default 8
1120 config IWMMXT
1121 bool "Enable iWMMXt support"
1122 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1123 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1124 help
1125 Enable support for iWMMXt context switching at run time if
1126 running on a CPU that supports it.
1128 config XSCALE_PMU
1129 bool
1130 depends on CPU_XSCALE
1131 default y
1133 config CPU_HAS_PMU
1134 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1135 (!ARCH_OMAP3 || OMAP3_EMU)
1136 default y
1137 bool
1139 config MULTI_IRQ_HANDLER
1140 bool
1141 help
1142 Allow each machine to specify it's own IRQ handler at run time.
1144 if !MMU
1145 source "arch/arm/Kconfig-nommu"
1146 endif
1148 config ARM_ERRATA_326103
1149 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1150 depends on CPU_V6
1151 help
1152 Executing a SWP instruction to read-only memory does not set bit 11
1153 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1154 treat the access as a read, preventing a COW from occurring and
1155 causing the faulting task to livelock.
1157 config ARM_ERRATA_411920
1158 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1159 depends on CPU_V6 || CPU_V6K
1160 help
1161 Invalidation of the Instruction Cache operation can
1162 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1163 It does not affect the MPCore. This option enables the ARM Ltd.
1164 recommended workaround.
1166 config ARM_ERRATA_430973
1167 bool "ARM errata: Stale prediction on replaced interworking branch"
1168 depends on CPU_V7
1169 help
1170 This option enables the workaround for the 430973 Cortex-A8
1171 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1172 interworking branch is replaced with another code sequence at the
1173 same virtual address, whether due to self-modifying code or virtual
1174 to physical address re-mapping, Cortex-A8 does not recover from the
1175 stale interworking branch prediction. This results in Cortex-A8
1176 executing the new code sequence in the incorrect ARM or Thumb state.
1177 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1178 and also flushes the branch target cache at every context switch.
1179 Note that setting specific bits in the ACTLR register may not be
1180 available in non-secure mode.
1182 config ARM_ERRATA_458693
1183 bool "ARM errata: Processor deadlock when a false hazard is created"
1184 depends on CPU_V7
1185 help
1186 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1187 erratum. For very specific sequences of memory operations, it is
1188 possible for a hazard condition intended for a cache line to instead
1189 be incorrectly associated with a different cache line. This false
1190 hazard might then cause a processor deadlock. The workaround enables
1191 the L1 caching of the NEON accesses and disables the PLD instruction
1192 in the ACTLR register. Note that setting specific bits in the ACTLR
1193 register may not be available in non-secure mode.
1195 config ARM_ERRATA_460075
1196 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1197 depends on CPU_V7
1198 help
1199 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1200 erratum. Any asynchronous access to the L2 cache may encounter a
1201 situation in which recent store transactions to the L2 cache are lost
1202 and overwritten with stale memory contents from external memory. The
1203 workaround disables the write-allocate mode for the L2 cache via the
1204 ACTLR register. Note that setting specific bits in the ACTLR register
1205 may not be available in non-secure mode.
1207 config ARM_ERRATA_742230
1208 bool "ARM errata: DMB operation may be faulty"
1209 depends on CPU_V7 && SMP
1210 help
1211 This option enables the workaround for the 742230 Cortex-A9
1212 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1213 between two write operations may not ensure the correct visibility
1214 ordering of the two writes. This workaround sets a specific bit in
1215 the diagnostic register of the Cortex-A9 which causes the DMB
1216 instruction to behave as a DSB, ensuring the correct behaviour of
1217 the two writes.
1219 config ARM_ERRATA_742231
1220 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1221 depends on CPU_V7 && SMP
1222 help
1223 This option enables the workaround for the 742231 Cortex-A9
1224 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1225 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1226 accessing some data located in the same cache line, may get corrupted
1227 data due to bad handling of the address hazard when the line gets
1228 replaced from one of the CPUs at the same time as another CPU is
1229 accessing it. This workaround sets specific bits in the diagnostic
1230 register of the Cortex-A9 which reduces the linefill issuing
1231 capabilities of the processor.
1233 config PL310_ERRATA_588369
1234 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235 depends on CACHE_L2X0
1236 help
1237 The PL310 L2 cache controller implements three types of Clean &
1238 Invalidate maintenance operations: by Physical Address
1239 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1240 They are architecturally defined to behave as the execution of a
1241 clean operation followed immediately by an invalidate operation,
1242 both performing to the same memory location. This functionality
1243 is not correctly implemented in PL310 as clean lines are not
1244 invalidated as a result of these operations.
1246 config ARM_ERRATA_720789
1247 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1248 depends on CPU_V7
1249 help
1250 This option enables the workaround for the 720789 Cortex-A9 (prior to
1251 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1252 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1253 As a consequence of this erratum, some TLB entries which should be
1254 invalidated are not, resulting in an incoherency in the system page
1255 tables. The workaround changes the TLB flushing routines to invalidate
1256 entries regardless of the ASID.
1258 config PL310_ERRATA_727915
1259 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1260 depends on CACHE_L2X0
1261 help
1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1263 operation (offset 0x7FC). This operation runs in background so that
1264 PL310 can handle normal accesses while it is in progress. Under very
1265 rare circumstances, due to this erratum, write data can be lost when
1266 PL310 treats a cacheable write transaction during a Clean &
1267 Invalidate by Way operation.
1269 config ARM_ERRATA_743622
1270 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1271 depends on CPU_V7
1272 help
1273 This option enables the workaround for the 743622 Cortex-A9
1274 (r2p*) erratum. Under very rare conditions, a faulty
1275 optimisation in the Cortex-A9 Store Buffer may lead to data
1276 corruption. This workaround sets a specific bit in the diagnostic
1277 register of the Cortex-A9 which disables the Store Buffer
1278 optimisation, preventing the defect from occurring. This has no
1279 visible impact on the overall performance or power consumption of the
1280 processor.
1282 config ARM_ERRATA_751472
1283 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1284 depends on CPU_V7
1285 help
1286 This option enables the workaround for the 751472 Cortex-A9 (prior
1287 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1288 completion of a following broadcasted operation if the second
1289 operation is received by a CPU before the ICIALLUIS has completed,
1290 potentially leading to corrupted entries in the cache or TLB.
1292 config PL310_ERRATA_753970
1293 bool "PL310 errata: cache sync operation may be faulty"
1294 depends on CACHE_PL310
1295 help
1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1298 Under some condition the effect of cache sync operation on
1299 the store buffer still remains when the operation completes.
1300 This means that the store buffer is always asked to drain and
1301 this prevents it from merging any further writes. The workaround
1302 is to replace the normal offset of cache sync operation (0x730)
1303 by another offset targeting an unmapped PL310 register 0x740.
1304 This has the same effect as the cache sync operation: store buffer
1305 drain and waiting for all buffers empty.
1307 config ARM_ERRATA_754322
1308 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1309 depends on CPU_V7
1310 help
1311 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1312 r3p*) erratum. A speculative memory access may cause a page table walk
1313 which starts prior to an ASID switch but completes afterwards. This
1314 can populate the micro-TLB with a stale entry which may be hit with
1315 the new ASID. This workaround places two dsb instructions in the mm
1316 switching code so that no page table walks can cross the ASID switch.
1318 config ARM_ERRATA_754327
1319 bool "ARM errata: no automatic Store Buffer drain"
1320 depends on CPU_V7 && SMP
1321 help
1322 This option enables the workaround for the 754327 Cortex-A9 (prior to
1323 r2p0) erratum. The Store Buffer does not have any automatic draining
1324 mechanism and therefore a livelock may occur if an external agent
1325 continuously polls a memory location waiting to observe an update.
1326 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1327 written polling loops from denying visibility of updates to memory.
1329 config ARM_ERRATA_364296
1330 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1331 depends on CPU_V6 && !SMP
1332 help
1333 This options enables the workaround for the 364296 ARM1136
1334 r0p2 erratum (possible cache data corruption with
1335 hit-under-miss enabled). It sets the undocumented bit 31 in
1336 the auxiliary control register and the FI bit in the control
1337 register, thus disabling hit-under-miss without putting the
1338 processor into full low interrupt latency mode. ARM11MPCore
1339 is not affected.
1341 config ARM_ERRATA_764369
1342 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1343 depends on CPU_V7 && SMP
1344 help
1345 This option enables the workaround for erratum 764369
1346 affecting Cortex-A9 MPCore with two or more processors (all
1347 current revisions). Under certain timing circumstances, a data
1348 cache line maintenance operation by MVA targeting an Inner
1349 Shareable memory region may fail to proceed up to either the
1350 Point of Coherency or to the Point of Unification of the
1351 system. This workaround adds a DSB instruction before the
1352 relevant cache maintenance functions and sets a specific bit
1353 in the diagnostic control register of the SCU.
1355 config PL310_ERRATA_769419
1356 bool "PL310 errata: no automatic Store Buffer drain"
1357 depends on CACHE_L2X0
1358 help
1359 On revisions of the PL310 prior to r3p2, the Store Buffer does
1360 not automatically drain. This can cause normal, non-cacheable
1361 writes to be retained when the memory system is idle, leading
1362 to suboptimal I/O performance for drivers using coherent DMA.
1363 This option adds a write barrier to the cpu_idle loop so that,
1364 on systems with an outer cache, the store buffer is drained
1365 explicitly.
1367 endmenu
1369 source "arch/arm/common/Kconfig"
1371 menu "Bus support"
1373 config ARM_AMBA
1374 bool
1376 config ISA
1377 bool
1378 help
1379 Find out whether you have ISA slots on your motherboard. ISA is the
1380 name of a bus system, i.e. the way the CPU talks to the other stuff
1381 inside your box. Other bus systems are PCI, EISA, MicroChannel
1382 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1383 newer boards don't support it. If you have ISA, say Y, otherwise N.
1385 # Select ISA DMA controller support
1386 config ISA_DMA
1387 bool
1388 select ISA_DMA_API
1390 # Select ISA DMA interface
1391 config ISA_DMA_API
1392 bool
1394 config PCI
1395 bool "PCI support" if MIGHT_HAVE_PCI
1396 help
1397 Find out whether you have a PCI motherboard. PCI is the name of a
1398 bus system, i.e. the way the CPU talks to the other stuff inside
1399 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1400 VESA. If you have PCI, say Y, otherwise N.
1402 config PCI_DOMAINS
1403 bool
1404 depends on PCI
1406 config PCI_NANOENGINE
1407 bool "BSE nanoEngine PCI support"
1408 depends on SA1100_NANOENGINE
1409 help
1410 Enable PCI on the BSE nanoEngine board.
1412 config PCI_SYSCALL
1413 def_bool PCI
1415 # Select the host bridge type
1416 config PCI_HOST_VIA82C505
1417 bool
1418 depends on PCI && ARCH_SHARK
1419 default y
1421 config PCI_HOST_ITE8152
1422 bool
1423 depends on PCI && MACH_ARMCORE
1424 default y
1425 select DMABOUNCE
1427 source "drivers/pci/Kconfig"
1429 source "drivers/pcmcia/Kconfig"
1431 endmenu
1433 menu "Kernel Features"
1435 config HAVE_SMP
1436 bool
1437 help
1438 This option should be selected by machines which have an SMP-
1439 capable CPU.
1441 The only effect of this option is to make the SMP-related
1442 options available to the user for configuration.
1444 config SMP
1445 bool "Symmetric Multi-Processing"
1446 depends on CPU_V6K || CPU_V7
1447 depends on GENERIC_CLOCKEVENTS
1448 depends on HAVE_SMP
1449 depends on MMU
1450 select USE_GENERIC_SMP_HELPERS
1451 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1452 help
1453 This enables support for systems with more than one CPU. If you have
1454 a system with only one CPU, like most personal computers, say N. If
1455 you have a system with more than one CPU, say Y.
1457 If you say N here, the kernel will run on single and multiprocessor
1458 machines, but will use only one CPU of a multiprocessor machine. If
1459 you say Y here, the kernel will run on many, but not all, single
1460 processor machines. On a single processor machine, the kernel will
1461 run faster if you say N here.
1463 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1464 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1465 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1467 If you don't know what to do here, say N.
1469 config SMP_ON_UP
1470 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1471 depends on EXPERIMENTAL
1472 depends on SMP && !XIP_KERNEL
1473 default y
1474 help
1475 SMP kernels contain instructions which fail on non-SMP processors.
1476 Enabling this option allows the kernel to modify itself to make
1477 these instructions safe. Disabling it allows about 1K of space
1478 savings.
1480 If you don't know what to do here, say Y.
1482 config ARM_CPU_TOPOLOGY
1483 bool "Support cpu topology definition"
1484 depends on SMP && CPU_V7
1485 default y
1486 help
1487 Support ARM cpu topology definition. The MPIDR register defines
1488 affinity between processors which is then used to describe the cpu
1489 topology of an ARM System.
1491 config SCHED_MC
1492 bool "Multi-core scheduler support"
1493 depends on ARM_CPU_TOPOLOGY
1494 help
1495 Multi-core scheduler support improves the CPU scheduler's decision
1496 making when dealing with multi-core CPU chips at a cost of slightly
1497 increased overhead in some places. If unsure say N here.
1499 config SCHED_SMT
1500 bool "SMT scheduler support"
1501 depends on ARM_CPU_TOPOLOGY
1502 help
1503 Improves the CPU scheduler's decision making when dealing with
1504 MultiThreading at a cost of slightly increased overhead in some
1505 places. If unsure say N here.
1507 config HAVE_ARM_SCU
1508 bool
1509 help
1510 This option enables support for the ARM system coherency unit
1512 config ARM_ARCH_TIMER
1513 bool "Architected timer support"
1514 depends on CPU_V7
1515 help
1516 This option enables support for the ARM architected timer
1518 config HAVE_ARM_TWD
1519 bool
1520 depends on SMP
1521 help
1522 This options enables support for the ARM timer and watchdog unit
1524 choice
1525 prompt "Memory split"
1526 default VMSPLIT_3G
1527 help
1528 Select the desired split between kernel and user memory.
1530 If you are not absolutely sure what you are doing, leave this
1531 option alone!
1533 config VMSPLIT_3G
1534 bool "3G/1G user/kernel split"
1535 config VMSPLIT_2G
1536 bool "2G/2G user/kernel split"
1537 config VMSPLIT_1G
1538 bool "1G/3G user/kernel split"
1539 endchoice
1541 config PAGE_OFFSET
1542 hex
1543 default 0x40000000 if VMSPLIT_1G
1544 default 0x80000000 if VMSPLIT_2G
1545 default 0xC0000000
1547 config NR_CPUS
1548 int "Maximum number of CPUs (2-32)"
1549 range 2 32
1550 depends on SMP
1551 default "4"
1553 config HOTPLUG_CPU
1554 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1555 depends on SMP && HOTPLUG && EXPERIMENTAL
1556 help
1557 Say Y here to experiment with turning CPUs off and on. CPUs
1558 can be controlled through /sys/devices/system/cpu.
1560 config LOCAL_TIMERS
1561 bool "Use local timer interrupts"
1562 depends on SMP
1563 default y
1564 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1565 help
1566 Enable support for local timers on SMP platforms, rather then the
1567 legacy IPI broadcast method. Local timers allows the system
1568 accounting to be spread across the timer interval, preventing a
1569 "thundering herd" at every timer tick.
1571 config ARCH_NR_GPIO
1572 int
1573 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1574 default 355 if ARCH_U8500
1575 default 264 if MACH_H4700
1576 default 0
1577 help
1578 Maximum number of GPIOs in the system.
1580 If unsure, leave the default value.
1582 source kernel/Kconfig.preempt
1584 config HZ
1585 int
1586 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1587 ARCH_S5PV210 || ARCH_EXYNOS4
1588 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1589 default AT91_TIMER_HZ if ARCH_AT91
1590 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1591 default 100
1593 config THUMB2_KERNEL
1594 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1595 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1596 select AEABI
1597 select ARM_ASM_UNIFIED
1598 select ARM_UNWIND
1599 help
1600 By enabling this option, the kernel will be compiled in
1601 Thumb-2 mode. A compiler/assembler that understand the unified
1602 ARM-Thumb syntax is needed.
1604 If unsure, say N.
1606 config THUMB2_AVOID_R_ARM_THM_JUMP11
1607 bool "Work around buggy Thumb-2 short branch relocations in gas"
1608 depends on THUMB2_KERNEL && MODULES
1609 default y
1610 help
1611 Various binutils versions can resolve Thumb-2 branches to
1612 locally-defined, preemptible global symbols as short-range "b.n"
1613 branch instructions.
1615 This is a problem, because there's no guarantee the final
1616 destination of the symbol, or any candidate locations for a
1617 trampoline, are within range of the branch. For this reason, the
1618 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1619 relocation in modules at all, and it makes little sense to add
1620 support.
1622 The symptom is that the kernel fails with an "unsupported
1623 relocation" error when loading some modules.
1625 Until fixed tools are available, passing
1626 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1627 code which hits this problem, at the cost of a bit of extra runtime
1628 stack usage in some cases.
1630 The problem is described in more detail at:
1631 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1633 Only Thumb-2 kernels are affected.
1635 Unless you are sure your tools don't have this problem, say Y.
1637 config ARM_ASM_UNIFIED
1638 bool
1640 config AEABI
1641 bool "Use the ARM EABI to compile the kernel"
1642 help
1643 This option allows for the kernel to be compiled using the latest
1644 ARM ABI (aka EABI). This is only useful if you are using a user
1645 space environment that is also compiled with EABI.
1647 Since there are major incompatibilities between the legacy ABI and
1648 EABI, especially with regard to structure member alignment, this
1649 option also changes the kernel syscall calling convention to
1650 disambiguate both ABIs and allow for backward compatibility support
1651 (selected with CONFIG_OABI_COMPAT).
1653 To use this you need GCC version 4.0.0 or later.
1655 config OABI_COMPAT
1656 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1657 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1658 default y
1659 help
1660 This option preserves the old syscall interface along with the
1661 new (ARM EABI) one. It also provides a compatibility layer to
1662 intercept syscalls that have structure arguments which layout
1663 in memory differs between the legacy ABI and the new ARM EABI
1664 (only for non "thumb" binaries). This option adds a tiny
1665 overhead to all syscalls and produces a slightly larger kernel.
1666 If you know you'll be using only pure EABI user space then you
1667 can say N here. If this option is not selected and you attempt
1668 to execute a legacy ABI binary then the result will be
1669 UNPREDICTABLE (in fact it can be predicted that it won't work
1670 at all). If in doubt say Y.
1672 config ARCH_HAS_HOLES_MEMORYMODEL
1673 bool
1675 config ARCH_SPARSEMEM_ENABLE
1676 bool
1678 config ARCH_SPARSEMEM_DEFAULT
1679 def_bool ARCH_SPARSEMEM_ENABLE
1681 config ARCH_SELECT_MEMORY_MODEL
1682 def_bool ARCH_SPARSEMEM_ENABLE
1684 config HAVE_ARCH_PFN_VALID
1685 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1687 config HIGHMEM
1688 bool "High Memory Support"
1689 depends on MMU
1690 help
1691 The address space of ARM processors is only 4 Gigabytes large
1692 and it has to accommodate user address space, kernel address
1693 space as well as some memory mapped IO. That means that, if you
1694 have a large amount of physical memory and/or IO, not all of the
1695 memory can be "permanently mapped" by the kernel. The physical
1696 memory that is not permanently mapped is called "high memory".
1698 Depending on the selected kernel/user memory split, minimum
1699 vmalloc space and actual amount of RAM, you may not need this
1700 option which should result in a slightly faster kernel.
1702 If unsure, say n.
1704 config HIGHPTE
1705 bool "Allocate 2nd-level pagetables from highmem"
1706 depends on HIGHMEM
1708 config HW_PERF_EVENTS
1709 bool "Enable hardware performance counter support for perf events"
1710 depends on PERF_EVENTS && CPU_HAS_PMU
1711 default y
1712 help
1713 Enable hardware performance counter support for perf events. If
1714 disabled, perf events will use software events only.
1716 source "mm/Kconfig"
1718 config FORCE_MAX_ZONEORDER
1719 int "Maximum zone order" if ARCH_SHMOBILE
1720 range 11 64 if ARCH_SHMOBILE
1721 default "9" if SA1111
1722 default "11"
1723 help
1724 The kernel memory allocator divides physically contiguous memory
1725 blocks into "zones", where each zone is a power of two number of
1726 pages. This option selects the largest power of two that the kernel
1727 keeps in the memory allocator. If you need to allocate very large
1728 blocks of physically contiguous memory, then you may need to
1729 increase this value.
1731 This config option is actually maximum order plus one. For example,
1732 a value of 11 means that the largest free memory block is 2^10 pages.
1734 config LEDS
1735 bool "Timer and CPU usage LEDs"
1736 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1737 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1738 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1739 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1740 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1741 ARCH_AT91 || ARCH_DAVINCI || \
1742 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1743 help
1744 If you say Y here, the LEDs on your machine will be used
1745 to provide useful information about your current system status.
1747 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1748 be able to select which LEDs are active using the options below. If
1749 you are compiling a kernel for the EBSA-110 or the LART however, the
1750 red LED will simply flash regularly to indicate that the system is
1751 still functional. It is safe to say Y here if you have a CATS
1752 system, but the driver will do nothing.
1754 config LEDS_TIMER
1755 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1756 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1757 || MACH_OMAP_PERSEUS2
1758 depends on LEDS
1759 depends on !GENERIC_CLOCKEVENTS
1760 default y if ARCH_EBSA110
1761 help
1762 If you say Y here, one of the system LEDs (the green one on the
1763 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1764 will flash regularly to indicate that the system is still
1765 operational. This is mainly useful to kernel hackers who are
1766 debugging unstable kernels.
1768 The LART uses the same LED for both Timer LED and CPU usage LED
1769 functions. You may choose to use both, but the Timer LED function
1770 will overrule the CPU usage LED.
1772 config LEDS_CPU
1773 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1774 !ARCH_OMAP) \
1775 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1776 || MACH_OMAP_PERSEUS2
1777 depends on LEDS
1778 help
1779 If you say Y here, the red LED will be used to give a good real
1780 time indication of CPU usage, by lighting whenever the idle task
1781 is not currently executing.
1783 The LART uses the same LED for both Timer LED and CPU usage LED
1784 functions. You may choose to use both, but the Timer LED function
1785 will overrule the CPU usage LED.
1787 config ALIGNMENT_TRAP
1788 bool
1789 depends on CPU_CP15_MMU
1790 default y if !ARCH_EBSA110
1791 select HAVE_PROC_CPU if PROC_FS
1792 help
1793 ARM processors cannot fetch/store information which is not
1794 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1795 address divisible by 4. On 32-bit ARM processors, these non-aligned
1796 fetch/store instructions will be emulated in software if you say
1797 here, which has a severe performance impact. This is necessary for
1798 correct operation of some network protocols. With an IP-only
1799 configuration it is safe to say N, otherwise say Y.
1801 config UACCESS_WITH_MEMCPY
1802 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1803 depends on MMU && EXPERIMENTAL
1804 default y if CPU_FEROCEON
1805 help
1806 Implement faster copy_to_user and clear_user methods for CPU
1807 cores where a 8-word STM instruction give significantly higher
1808 memory write throughput than a sequence of individual 32bit stores.
1810 A possible side effect is a slight increase in scheduling latency
1811 between threads sharing the same address space if they invoke
1812 such copy operations with large buffers.
1814 However, if the CPU data cache is using a write-allocate mode,
1815 this option is unlikely to provide any performance gain.
1817 config SECCOMP
1818 bool
1819 prompt "Enable seccomp to safely compute untrusted bytecode"
1820 ---help---
1821 This kernel feature is useful for number crunching applications
1822 that may need to compute untrusted bytecode during their
1823 execution. By using pipes or other transports made available to
1824 the process as file descriptors supporting the read/write
1825 syscalls, it's possible to isolate those applications in
1826 their own address space using seccomp. Once seccomp is
1827 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1828 and the task is only allowed to execute a few safe syscalls
1829 defined by each seccomp mode.
1831 config CC_STACKPROTECTOR
1832 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1833 depends on EXPERIMENTAL
1834 help
1835 This option turns on the -fstack-protector GCC feature. This
1836 feature puts, at the beginning of functions, a canary value on
1837 the stack just before the return address, and validates
1838 the value just before actually returning. Stack based buffer
1839 overflows (that need to overwrite this return address) now also
1840 overwrite the canary, which gets detected and the attack is then
1841 neutralized via a kernel panic.
1842 This feature requires gcc version 4.2 or above.
1844 config DEPRECATED_PARAM_STRUCT
1845 bool "Provide old way to pass kernel parameters"
1846 help
1847 This was deprecated in 2001 and announced to live on for 5 years.
1848 Some old boot loaders still use this way.
1850 endmenu
1852 menu "Boot options"
1854 config USE_OF
1855 bool "Flattened Device Tree support"
1856 select OF
1857 select OF_EARLY_FLATTREE
1858 select IRQ_DOMAIN
1859 help
1860 Include support for flattened device tree machine descriptions.
1862 # Compressed boot loader in ROM. Yes, we really want to ask about
1863 # TEXT and BSS so we preserve their values in the config files.
1864 config ZBOOT_ROM_TEXT
1865 hex "Compressed ROM boot loader base address"
1866 default "0"
1867 help
1868 The physical address at which the ROM-able zImage is to be
1869 placed in the target. Platforms which normally make use of
1870 ROM-able zImage formats normally set this to a suitable
1871 value in their defconfig file.
1873 If ZBOOT_ROM is not enabled, this has no effect.
1875 config ZBOOT_ROM_BSS
1876 hex "Compressed ROM boot loader BSS address"
1877 default "0"
1878 help
1879 The base address of an area of read/write memory in the target
1880 for the ROM-able zImage which must be available while the
1881 decompressor is running. It must be large enough to hold the
1882 entire decompressed kernel plus an additional 128 KiB.
1883 Platforms which normally make use of ROM-able zImage formats
1884 normally set this to a suitable value in their defconfig file.
1886 If ZBOOT_ROM is not enabled, this has no effect.
1888 config ZBOOT_ROM
1889 bool "Compressed boot loader in ROM/flash"
1890 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1891 help
1892 Say Y here if you intend to execute your compressed kernel image
1893 (zImage) directly from ROM or flash. If unsure, say N.
1895 choice
1896 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1897 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1898 default ZBOOT_ROM_NONE
1899 help
1900 Include experimental SD/MMC loading code in the ROM-able zImage.
1901 With this enabled it is possible to write the ROM-able zImage
1902 kernel image to an MMC or SD card and boot the kernel straight
1903 from the reset vector. At reset the processor Mask ROM will load
1904 the first part of the ROM-able zImage which in turn loads the
1905 rest the kernel image to RAM.
1907 config ZBOOT_ROM_NONE
1908 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1909 help
1910 Do not load image from SD or MMC
1912 config ZBOOT_ROM_MMCIF
1913 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1914 help
1915 Load image from MMCIF hardware block.
1917 config ZBOOT_ROM_SH_MOBILE_SDHI
1918 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1919 help
1920 Load image from SDHI hardware block
1922 endchoice
1924 config ARM_APPENDED_DTB
1925 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1926 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1927 help
1928 With this option, the boot code will look for a device tree binary
1929 (DTB) appended to zImage
1930 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1932 This is meant as a backward compatibility convenience for those
1933 systems with a bootloader that can't be upgraded to accommodate
1934 the documented boot protocol using a device tree.
1936 Beware that there is very little in terms of protection against
1937 this option being confused by leftover garbage in memory that might
1938 look like a DTB header after a reboot if no actual DTB is appended
1939 to zImage. Do not leave this option active in a production kernel
1940 if you don't intend to always append a DTB. Proper passing of the
1941 location into r2 of a bootloader provided DTB is always preferable
1942 to this option.
1944 config ARM_ATAG_DTB_COMPAT
1945 bool "Supplement the appended DTB with traditional ATAG information"
1946 depends on ARM_APPENDED_DTB
1947 help
1948 Some old bootloaders can't be updated to a DTB capable one, yet
1949 they provide ATAGs with memory configuration, the ramdisk address,
1950 the kernel cmdline string, etc. Such information is dynamically
1951 provided by the bootloader and can't always be stored in a static
1952 DTB. To allow a device tree enabled kernel to be used with such
1953 bootloaders, this option allows zImage to extract the information
1954 from the ATAG list and store it at run time into the appended DTB.
1956 config CMDLINE
1957 string "Default kernel command string"
1958 default ""
1959 help
1960 On some architectures (EBSA110 and CATS), there is currently no way
1961 for the boot loader to pass arguments to the kernel. For these
1962 architectures, you should supply some command-line options at build
1963 time by entering them here. As a minimum, you should specify the
1964 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1966 choice
1967 prompt "Kernel command line type" if CMDLINE != ""
1968 default CMDLINE_FROM_BOOTLOADER
1970 config CMDLINE_FROM_BOOTLOADER
1971 bool "Use bootloader kernel arguments if available"
1972 help
1973 Uses the command-line options passed by the boot loader. If
1974 the boot loader doesn't provide any, the default kernel command
1975 string provided in CMDLINE will be used.
1977 config CMDLINE_EXTEND
1978 bool "Extend bootloader kernel arguments"
1979 help
1980 The command-line arguments provided by the boot loader will be
1981 appended to the default kernel command string.
1983 config CMDLINE_FORCE
1984 bool "Always use the default kernel command string"
1985 help
1986 Always use the default kernel command string, even if the boot
1987 loader passes other arguments to the kernel.
1988 This is useful if you cannot or don't want to change the
1989 command-line options your boot loader passes to the kernel.
1990 endchoice
1992 config XIP_KERNEL
1993 bool "Kernel Execute-In-Place from ROM"
1994 depends on !ZBOOT_ROM && !ARM_LPAE
1995 help
1996 Execute-In-Place allows the kernel to run from non-volatile storage
1997 directly addressable by the CPU, such as NOR flash. This saves RAM
1998 space since the text section of the kernel is not loaded from flash
1999 to RAM. Read-write sections, such as the data section and stack,
2000 are still copied to RAM. The XIP kernel is not compressed since
2001 it has to run directly from flash, so it will take more space to
2002 store it. The flash address used to link the kernel object files,
2003 and for storing it, is configuration dependent. Therefore, if you
2004 say Y here, you must know the proper physical address where to
2005 store the kernel image depending on your own flash memory usage.
2007 Also note that the make target becomes "make xipImage" rather than
2008 "make zImage" or "make Image". The final kernel binary to put in
2009 ROM memory will be arch/arm/boot/xipImage.
2011 If unsure, say N.
2013 config XIP_PHYS_ADDR
2014 hex "XIP Kernel Physical Location"
2015 depends on XIP_KERNEL
2016 default "0x00080000"
2017 help
2018 This is the physical address in your flash memory the kernel will
2019 be linked for and stored to. This address is dependent on your
2020 own flash usage.
2022 config KEXEC
2023 bool "Kexec system call (EXPERIMENTAL)"
2024 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2025 help
2026 kexec is a system call that implements the ability to shutdown your
2027 current kernel, and to start another kernel. It is like a reboot
2028 but it is independent of the system firmware. And like a reboot
2029 you can start any kernel with it, not just Linux.
2031 It is an ongoing process to be certain the hardware in a machine
2032 is properly shutdown, so do not be surprised if this code does not
2033 initially work for you. It may help to enable device hotplugging
2034 support.
2036 config ATAGS_PROC
2037 bool "Export atags in procfs"
2038 depends on KEXEC
2039 default y
2040 help
2041 Should the atags used to boot the kernel be exported in an "atags"
2042 file in procfs. Useful with kexec.
2044 config CRASH_DUMP
2045 bool "Build kdump crash kernel (EXPERIMENTAL)"
2046 depends on EXPERIMENTAL
2047 help
2048 Generate crash dump after being started by kexec. This should
2049 be normally only set in special crash dump kernels which are
2050 loaded in the main kernel with kexec-tools into a specially
2051 reserved region and then later executed after a crash by
2052 kdump/kexec. The crash dump kernel must be compiled to a
2053 memory address not used by the main kernel
2055 For more details see Documentation/kdump/kdump.txt
2057 config AUTO_ZRELADDR
2058 bool "Auto calculation of the decompressed kernel image address"
2059 depends on !ZBOOT_ROM && !ARCH_U300
2060 help
2061 ZRELADDR is the physical address where the decompressed kernel
2062 image will be placed. If AUTO_ZRELADDR is selected, the address
2063 will be determined at run-time by masking the current IP with
2064 0xf8000000. This assumes the zImage being placed in the first 128MB
2065 from start of memory.
2067 endmenu
2069 menu "CPU Power Management"
2071 if ARCH_HAS_CPUFREQ
2073 source "drivers/cpufreq/Kconfig"
2075 config CPU_FREQ_IMX
2076 tristate "CPUfreq driver for i.MX CPUs"
2077 depends on ARCH_MXC && CPU_FREQ
2078 help
2079 This enables the CPUfreq driver for i.MX CPUs.
2081 config CPU_FREQ_SA1100
2082 bool
2084 config CPU_FREQ_SA1110
2085 bool
2087 config CPU_FREQ_INTEGRATOR
2088 tristate "CPUfreq driver for ARM Integrator CPUs"
2089 depends on ARCH_INTEGRATOR && CPU_FREQ
2090 default y
2091 help
2092 This enables the CPUfreq driver for ARM Integrator CPUs.
2094 For details, take a look at <file:Documentation/cpu-freq>.
2096 If in doubt, say Y.
2098 config CPU_FREQ_PXA
2099 bool
2100 depends on CPU_FREQ && ARCH_PXA && PXA25x
2101 default y
2102 select CPU_FREQ_TABLE
2103 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2105 config CPU_FREQ_S3C
2106 bool
2107 help
2108 Internal configuration node for common cpufreq on Samsung SoC
2110 config CPU_FREQ_S3C24XX
2111 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2112 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2113 select CPU_FREQ_S3C
2114 help
2115 This enables the CPUfreq driver for the Samsung S3C24XX family
2116 of CPUs.
2118 For details, take a look at <file:Documentation/cpu-freq>.
2120 If in doubt, say N.
2122 config CPU_FREQ_S3C24XX_PLL
2123 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2124 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2125 help
2126 Compile in support for changing the PLL frequency from the
2127 S3C24XX series CPUfreq driver. The PLL takes time to settle
2128 after a frequency change, so by default it is not enabled.
2130 This also means that the PLL tables for the selected CPU(s) will
2131 be built which may increase the size of the kernel image.
2133 config CPU_FREQ_S3C24XX_DEBUG
2134 bool "Debug CPUfreq Samsung driver core"
2135 depends on CPU_FREQ_S3C24XX
2136 help
2137 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2139 config CPU_FREQ_S3C24XX_IODEBUG
2140 bool "Debug CPUfreq Samsung driver IO timing"
2141 depends on CPU_FREQ_S3C24XX
2142 help
2143 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2145 config CPU_FREQ_S3C24XX_DEBUGFS
2146 bool "Export debugfs for CPUFreq"
2147 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2148 help
2149 Export status information via debugfs.
2151 endif
2153 source "drivers/cpuidle/Kconfig"
2155 endmenu
2157 menu "Floating point emulation"
2159 comment "At least one emulation must be selected"
2161 config FPE_NWFPE
2162 bool "NWFPE math emulation"
2163 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2164 ---help---
2165 Say Y to include the NWFPE floating point emulator in the kernel.
2166 This is necessary to run most binaries. Linux does not currently
2167 support floating point hardware so you need to say Y here even if
2168 your machine has an FPA or floating point co-processor podule.
2170 You may say N here if you are going to load the Acorn FPEmulator
2171 early in the bootup.
2173 config FPE_NWFPE_XP
2174 bool "Support extended precision"
2175 depends on FPE_NWFPE
2176 help
2177 Say Y to include 80-bit support in the kernel floating-point
2178 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2179 Note that gcc does not generate 80-bit operations by default,
2180 so in most cases this option only enlarges the size of the
2181 floating point emulator without any good reason.
2183 You almost surely want to say N here.
2185 config FPE_FASTFPE
2186 bool "FastFPE math emulation (EXPERIMENTAL)"
2187 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2188 ---help---
2189 Say Y here to include the FAST floating point emulator in the kernel.
2190 This is an experimental much faster emulator which now also has full
2191 precision for the mantissa. It does not support any exceptions.
2192 It is very simple, and approximately 3-6 times faster than NWFPE.
2194 It should be sufficient for most programs. It may be not suitable
2195 for scientific calculations, but you have to check this for yourself.
2196 If you do not feel you need a faster FP emulation you should better
2197 choose NWFPE.
2199 config VFP
2200 bool "VFP-format floating point maths"
2201 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2202 help
2203 Say Y to include VFP support code in the kernel. This is needed
2204 if your hardware includes a VFP unit.
2206 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2207 release notes and additional status information.
2209 Say N if your target does not have VFP hardware.
2211 config VFPv3
2212 bool
2213 depends on VFP
2214 default y if CPU_V7
2216 config NEON
2217 bool "Advanced SIMD (NEON) Extension support"
2218 depends on VFPv3 && CPU_V7
2219 help
2220 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2221 Extension.
2223 endmenu
2225 menu "Userspace binary formats"
2227 source "fs/Kconfig.binfmt"
2229 config ARTHUR
2230 tristate "RISC OS personality"
2231 depends on !AEABI
2232 help
2233 Say Y here to include the kernel code necessary if you want to run
2234 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2235 experimental; if this sounds frightening, say N and sleep in peace.
2236 You can also say M here to compile this support as a module (which
2237 will be called arthur).
2239 endmenu
2241 menu "Power management options"
2243 source "kernel/power/Kconfig"
2245 config ARCH_SUSPEND_POSSIBLE
2246 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2247 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2248 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2249 def_bool y
2251 config ARM_CPU_SUSPEND
2252 def_bool PM_SLEEP
2254 endmenu
2256 source "net/Kconfig"
2258 source "drivers/Kconfig"
2260 source "fs/Kconfig"
2262 source "arch/arm/Kconfig.debug"
2264 source "security/Kconfig"
2266 source "crypto/Kconfig"
2268 source "lib/Kconfig"