2 * MPC832x RDB Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
13 model = "MPC8323ERDB";
14 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <4000>; // L1, 16K
28 i-cache-size = <4000>; // L1, 16K
29 timebase-frequency = <0>;
31 clock-frequency = <0>;
36 device_type = "memory";
37 reg = <00000000 04000000>;
44 ranges = <0 e0000000 00100000>;
45 reg = <e0000000 00000200>;
49 device_type = "watchdog";
50 compatible = "mpc83xx_wdt";
58 compatible = "fsl-i2c";
61 interrupt-parent = <&pic>;
66 device_type = "serial";
67 compatible = "ns16550";
69 clock-frequency = <0>;
71 interrupt-parent = <&pic>;
75 device_type = "serial";
76 compatible = "ns16550";
78 clock-frequency = <0>;
80 interrupt-parent = <&pic>;
84 device_type = "crypto";
86 compatible = "talitos";
89 interrupt-parent = <&pic>;
92 channel-fifo-len = <18>;
93 exec-units-mask = <0000004c>;
94 descriptor-types-mask = <0122003f>;
100 #interrupt-cells = <2>;
102 device_type = "ipic";
107 device_type = "par_io";
112 /* port pin dir open_drain assignment has_irq */
113 3 4 3 0 2 0 /* MDIO */
114 3 5 1 0 2 0 /* MDC */
115 3 15 2 0 1 0 /* RX_CLK (CLK16) */
116 3 17 2 0 1 0 /* TX_CLK (CLK3) */
117 0 12 1 0 1 0 /* TxD0 */
118 0 13 1 0 1 0 /* TxD1 */
119 0 14 1 0 1 0 /* TxD2 */
120 0 15 1 0 1 0 /* TxD3 */
121 0 16 2 0 1 0 /* RxD0 */
122 0 17 2 0 1 0 /* RxD1 */
123 0 18 2 0 1 0 /* RxD2 */
124 0 19 2 0 1 0 /* RxD3 */
125 0 1a 2 0 1 0 /* RX_ER */
126 0 1b 1 0 1 0 /* TX_ER */
127 0 1c 2 0 1 0 /* RX_DV */
128 0 1d 2 0 1 0 /* COL */
129 0 1e 1 0 1 0 /* TX_EN */
130 0 1f 2 0 1 0>; /* CRS */
134 /* port pin dir open_drain assignment has_irq */
135 0 d 2 0 1 0 /* RX_CLK (CLK9) */
136 3 18 2 0 1 0 /* TX_CLK (CLK10) */
137 1 0 1 0 1 0 /* TxD0 */
138 1 1 1 0 1 0 /* TxD1 */
139 1 2 1 0 1 0 /* TxD2 */
140 1 3 1 0 1 0 /* TxD3 */
141 1 4 2 0 1 0 /* RxD0 */
142 1 5 2 0 1 0 /* RxD1 */
143 1 6 2 0 1 0 /* RxD2 */
144 1 7 2 0 1 0 /* RxD3 */
145 1 8 2 0 1 0 /* RX_ER */
146 1 9 1 0 1 0 /* TX_ER */
147 1 a 2 0 1 0 /* RX_DV */
148 1 b 2 0 1 0 /* COL */
149 1 c 1 0 1 0 /* TX_EN */
150 1 d 2 0 1 0>; /* CRS */
156 #address-cells = <1>;
160 ranges = <0 e0100000 00100000>;
161 reg = <e0100000 480>;
163 bus-frequency = <BCD3D80>;
166 device_type = "muram";
167 ranges = <0 00010000 00004000>;
176 compatible = "fsl_spi";
179 interrupt-parent = <&qeic>;
185 compatible = "fsl_spi";
188 interrupt-parent = <&qeic>;
193 device_type = "network";
194 compatible = "ucc_geth";
200 interrupt-parent = <&qeic>;
201 local-mac-address = [ 00 00 00 00 00 00 ];
204 phy-handle = <&phy00>;
205 pio-handle = <&ucc2pio>;
209 device_type = "network";
210 compatible = "ucc_geth";
216 interrupt-parent = <&qeic>;
217 local-mac-address = [ 00 00 00 00 00 00 ];
220 phy-handle = <&phy04>;
221 pio-handle = <&ucc3pio>;
225 #address-cells = <1>;
228 device_type = "mdio";
229 compatible = "ucc_geth_phy";
231 phy00:ethernet-phy@00 {
232 interrupt-parent = <&pic>;
235 device_type = "ethernet-phy";
237 phy04:ethernet-phy@04 {
238 interrupt-parent = <&pic>;
241 device_type = "ethernet-phy";
246 interrupt-controller;
247 device_type = "qeic";
248 #address-cells = <0>;
249 #interrupt-cells = <1>;
252 interrupts = <20 8 21 8>; //high:32 low:33
253 interrupt-parent = <&pic>;
258 interrupt-map-mask = <f800 0 0 7>;
260 /* IDSEL 0x10 AD16 (USB) */
263 /* IDSEL 0x11 AD17 (Mini1)*/
269 /* IDSEL 0x12 AD18 (PCI/Mini2) */
273 9000 0 0 4 &pic 11 8>;
275 interrupt-parent = <&pic>;
278 ranges = <42000000 0 80000000 80000000 0 10000000
279 02000000 0 90000000 90000000 0 10000000
280 01000000 0 d0000000 d0000000 0 04000000>;
281 clock-frequency = <0>;
282 #interrupt-cells = <1>;
284 #address-cells = <3>;
285 reg = <e0008500 100>;
286 compatible = "fsl,mpc8349-pci";